MP44018A
CrM/DCM Multi-Mode PFC Controller with
Enhanced Light-Load Efficiency
DESCRIPTION
FEATURES
The MP44018A is a CrM/DCM multi-mode PFC
controller that provides simple and highperformance active power factor correction
using minimal external components.
The MP44018A features a very low supply
current. This allows the device to achieve low
standby power loss, and the typical no load
power is below 30mW.
The switching frequency is reduced by dead time
extension technology under light-load conditions,
which improves light-load efficiency. The
MP44018A also achieves lower THD due to
variable-on-time control in discontinuous
conduction mode (DCM) when compared to
conventional constant-on-time (COT) control.
Multi-protection functionality largely enhances
the safety and reliability of the system. The
MP44018A feature over-voltage protection
(OVP), over-current limit (OCL), over-current
protection (OCP), under-voltage protection
(UVP), brown-in (BI) and brownout (BO), static
OVP, VCC under-voltage lockout (UVLO), and
over-temperature protection (OTP).
MP44018A is available in SOIC-8 package.
Valley Turn-On for Minimum Switching Loss
Frequency Reduction to Reduce Switching
Loss Under Light-Load Conditions
Low Supply Current in Burst Mode
Soft-On/Off Burst for Low Audible Noise
Mains Compensation
Improved THD
Under-Voltage Protection (UVP)
Over-Current Limit (OCL)
Over-Current Protection (OCP)
Over-Voltage Protection (OVP)
Brown-In (BI) and Brownout (BO)
Over-Temperature Protection (OTP)
Open/Short Pin Protection
Soft Start-Up
Enhanced Dynamic Response
Available in an SOIC-8 Package
APPLICATIONS
LCD and OLED TVs
Desktop PCs and Servers
High-Power Supply for Lighting
AC/DC Adapters, Open-Frame SMPS
Video Game Consoles
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions”
are trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
MP44018A Rev. 1.01
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL APPLICATION
L1
D1
VO
RO1
VCC
BD1
RZCD
F1
U1
C1
VAC
Cx1
CVCC
ZCD
VCC
RG
FB
CO
Q1
GATE
M44018A
MAINSIN
COMP
CS
RO2
GND
R4
RIN2 RZ
CZ
CP
C2
RCS
RIN1
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
ORDERING INFORMATION
Part Number*
MP44018-AGS
Package
SOIC-8
Top Marking
See Below
MSL Rating
2
*For Tape & Reel, add suffix –Z (e.g. MP44018-AGS–Z).
TOP MARKING
M44018-A: Part number
LLLLLLLL: Lot number
MPS: MPS prefix
Y: Year code
WW: Week code
PACKAGE REFERENCE
TOP VIEW
1
FB
2
COMP
3 MAINSIN
4
CS
VCC
8
GATE
7
GND
6
ZCD
5
SOIC-8
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
Output voltage sense. This pin senses the output voltage through a resistor divider, and
compares the sensed voltage to the reference voltage (VR) (typically 2.5V). This allows the
output voltage to be regulated. FB also integrates under-voltage protection (UVP) and overvoltage protection (OVP), described below:
1
FB
UVP: Pull the FB pin below 0.36V for a blanking time (tBL_UVP) of 55µs to shut down the IC,
or pull COMP down for the IC to enter low-supply current mode.
OVP: If FB exceeds VFB_OVP (typically 2.7V) for a blanking time (tBL_OVP) of 22µs, the IC stops
switching. It resumes switching when FB drops back to 2.62V.
2
3
COMP
MAINSIN
Error amplifier output. The compensation network is connected between this pin and
GND. If the internal COMP voltage (VCOMPI) drops below VCOMPI_BOFF (typically 60mV),
switching stops are five soft-off pulses. As VCOMPI ramps up to VCOMPI_BON (typically 120mV),
switching resumes after five soft-on pulses.
Mains voltage sense. MAINSIN is connected to the AC with a two-diode rectifier, or
connected just after the rectifier bridge. The rectifier voltage is scaled down by a resistor
divider to MAINSIN. The voltage on MAINSIN provides brown-in and brownout functions,
and provides feed-forward compensation for the COMP voltage.
If MAINSIN’s peak voltage exceeds VMAINS_BI (typically 1V), the device starts to switch with
COMP soft start-up. If MAINSIN’s peak voltage remains below VMAINS_BO (typically 0.9V) for
tBO (typically 50ms), a brownout condition is confirmed. The PFC stops switching, and
COMP is pulled down to zero.
Current sense. The CS pin provides monitoring for over-current protection (OCP) and overcurrent limiting (OCL). A lead-edge blanking time ensures that the CS pin does not
mistrigger OCP or OCL.
4
CS
OCL: If CS exceeds VOCL (typically 0.5V) with an LEB time (tOCL_LEB) of 300ns, the IC stops
switching. OCL is cycle-by- cycle current limited.
OCP: If the CS voltage exceeds VOCP (typically 0.75V) in two consecutive 180µs restart
switching cycles, the OCP flag is triggered, and the IC stops switching. OCP is reset by an
auto-recovery timer (tOCP_R) of 80ms, or by a brown-in, brownout, or VCC under-voltage
lockout (UVLO) event.
5
ZCD
Zero-current detection through auxiliary winding. A leading-edge blanking time
(tZCD_LEB) of 0.3µs is inserted to filter out the noise ringing on ZCD after the gate turns off.
The positive voltage on ZCD must exceed VZCD_H (typically 0.75V), then drop below VZCD_L
(typically 0.25V) for the next stoke. The valley switch must wait for the end of the minimum
period limitation time or dead time extension control.
The restart timer generates a signal to turn on the MOSFET when ZCD is not detected for
tZCD_TO (typically 180µs) after it switches off.
6
GND
7
GATE
8
VCC
Ground.
Gate driver output. The high output current of the gate driver can drive the low-cost power
MOSFET. If GATE is supplied with a high VCC, the high-level voltage of GATE is clamped
to 13V.
Supply voltage. VCC supplies power to the IC’s signal path and the gate driver. Connect
a bypass capacitor from VCC to ground to reduce noise.
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Supply voltage (VCC) ................... -0.3V to +35V
FB, COMP, MAINSIN, CS .............. -0.3V to +6V
GATE........................................... -0.3V to +14V
ZCD ............................................... -0.5V to +8V
ZCD current ............................ -10mA to +10mA
Continuous power dissipation (TA = 25°C) (2)
SOIC-8 ......................................................1.4W
Junction temperature……………………… 150°C
Lead temperature (solder) ....................... 260°C
Storage temperature ................ -55°C to +150°C
SOIC-8……………...................90.... .. 45 ... °C/W
Notes:
1)
2)
ESD Ratings
3)
Human body model (HBM) ........................ ±2kV
Charged device model (CDM).................... ±2kV
4)
Exceeding these ratings may damage the device.
The maximum allowable power dissipation is a function of the
maximum junction temperature, TJ (MAX), the junction-toambient thermal resistance, θJA, and the ambient
temperature, TA. The maximum allowable continuous power
dissipation at any ambient temperature is calculated by D
(MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum
allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal shutdown.
Internal thermal shutdown circuitry protects the device from
permanent damage.
The device is not guaranteed to function outside of its
operating conditions.
Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Supply voltage (VCC)………………… 12V to 32V
MAINSIN………………………………… 0V to 4V
Maximum junction temp (TJ) .................... 125°C
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
ELECTRICAL CHARACTERISTICS (5)
VCC = 20V, TA = TJ= -40°C to +125°C, min and max values are guaranteed by characterization.
Typical values are tested under 25°C, unless otherwise noted.
Parameter
Supply Voltage (VCC)
Symbol
Turn-on threshold
Turn-off threshold
Hysteresis
Supply Current
Min
Typ
Max
Units
VCC_ON
VCC_OFF
10.2
8.1
10.7
8.5
11.2
9.1
V
V
VCC_HYS
1.8
2.1
2.4
V
25
0.18
2.1
40
0.25
3
µA
mA
mA
Start-up current
ISTARTUP
Quiescent current
IQ
Operating current
ICC
Mains Voltage Sensing (MAINSIN)
Brown-in voltage
Brownout voltage
Brownout comparator
hysteresis
Brownout timer
Protection current for
MAINSIN open
Error Amplifier
Reference voltage
Transconductance
OVP hysteresis
OVP blanking time
Protection current for FB
open
VCC = 9.5V
No switch
fSW = 70kHz, CLOAD = 1nF
VMAINS_BI
VMAINS_BO
0.95
0.85
1
0.9
1.05
0.95
V
V
VBO(HYS)
0.05
0.1
0.14
V
tBO
50
ms
IMAINSIN_BIAS
20
nA
VR
GM1
GM2
2.463
80
160
2.5
105
280
2.538
125
400
V
uS
uS
660
40
3
-2.5
-25
780
70
5
-4.5
-50
940
100
7
-6.5
-75
uS
µA
µA
µA
µA
VFB_UVP
0.35
0.45
VFB_UVP_HYS
tBL_UVP
VFB_SGM3
VFB_SGM2
VFB_OVP
35
2.56
2.36
2.66
0.4
0.04
55
2.6
2.4
2.7
75
2.64
2.44
2.73
V
V
µs
V
V
V
15
0.08
22
32
V
µs
GM3
ISOURCE1(COMP)
Source current
ISOURCE2(COMP)
ISINK1(COMP)
Sink current
ISINK2(COMP)
Feedback Inverter Pin (FB)
UVP stop threshold
UVP hysteresis
UVP blanking time
FB start GM3 (5)
FB start GM2 (5)
OVP trigger threshold
Condition
VFB = 2.45V
VFB = 2.2V to 2.3V
VFB = 2.65V to 2.75V
VFB = VR - 0.3V
VFB = VR - 0.05V
VFB = VR + 0.05V
VFB = VR + 0.15V
VFB_OVP_HYS
tBL_OVP
IFB_BIAS
VFB = 2V
20
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nA
6
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 20V, TA = TJ = -40°C to +125°C, min and max values are guaranteed by characterization,
typical values are tested under 25°C, unless otherwise noted.
Parameter
Current Sense (CS)
Symbol
Protection current for CS
open
Over-current limit threshold
LEB time for OCL
Condition
Min
ICS_BIAS
Max
-220
VOCL
460
tOCL_LEB
Driver delay time
tCS_DELAY
Over-current protection
VOCP
threshold
Voltage difference between
VOCP_OCL
OCP and OCL
LEB time for OCP
tOCP_LEB
OCP recovery time
tOCP_R
Zero-Current Detection (ZCD)
Protection current for ZCD
open
Typ
500
300
Units
nA
530
100
mV
ns
ns
600
750
1000
mV
100
200
500
mV
IZCD_BIAS
250
80
ns
ms
5
nA
V
Upper clamp voltage
VZCD_CLAMP
IZCD = 3mA
7.2
7.8
Zero-current sensing
threshold
VZCD_H
VZCD rising
0.6
0.75
0.9
V
VZCD_L
VZCD falling
0.2
0.25
0.3
V
Turn-on delay after ZCD
detected
tZCD_DELAY
ZCD timer-out time
ZCD leading-edge blanking
time (5)
tZCD_TO
150
130
tZCD_LEB
tOFF_MINI
Minimum off time
180
ns
250
0.3
1
1.4
µs
µs
1.9
µs
Error Amplifier Output (COMP)
Comp voltage at max on
time (5)
Comp voltage at zero on
time (5)
Internal COMP voltage
transient CrM to DCM (5)
Internal COMP voltage to
enter burst off (6)
Internal COMP voltage to
enter burst on
Burst hysteresis
Soft-off burst pulses
counter (5)
Soft-on burst pulses
counter (5)
Maximum dead time
VCOMP_H
3.8
V
VCOMP_L
0.8
V
VCOMPI_C2D
0.38
V
VCOMPI_BOFF
30
60
90
mV
VCOMPI_BON
95
120
150
mV
VBURST_HYS
30
60
95
mV
29
µs
NSOFTOFF
5
NSOFTON
5
tDEAD_MAX
19
22
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 20V, TA = TJ = -40°C to +125°C, min and max values are guaranteed by characterization,
typical values are tested under 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Mains Compensation
tON_LL
VCOMP = 3.8V,
MAINSIN = 1.0V
20
24
29
µs
tON_HL
VCOMP = 3.8V,
MAINSIN = 3.38V
1.6
2.1
2.8
µs
ROH
ROL
IGDSOURCE = 20mA
IGDSINK = 20mA
10
2.5
16
6
Ω
Ω
On time
Gate Driver (GATE)
Drop voltage
Voltage falling time
tF
20
ns
Voltage rising time
Max output drive
voltage
Source current
capability (5)
Sink current capability
tR
120
ns
VGATE_MAX
11.5
13
15
V
IGATE_SOURCE
-600
mA
IGATE_SINK
1
A
(5)
UVLO saturation
voltage
VSATURATION
VCC = 0V to VCC_ON,
IGATE_SINK = 10mA
1.5
V
Internal OTP
OTP trig level (5)
OTP hysteresis (5)
TOTP
TOTP_HYS
150
40
°C
°C
Notes:
5) Guaranteed by design.
6) VCOMPI = (VCOMP - VCOMP_L) / 3
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 85VAC to 265VAC, VOUT = 400V, TA = 25°C, unless otherwise noted.
Supply Voltage vs. TJ
Supply Current vs. TJ
SUPPLY CURRENT (μA)
SUPPLY VOLTAGE (V)
12
11
10
9
8
7
Turn On Threshold
Turn Off Threshold
6
-50
0
50
100
TEMPERATURE (℃)
200
180
160
140
120
100
80
60
40
20
0
150
-50
Brown-In and Brownout Voltages vs.
TJ
150
Reference Voltage vs. TJ
REFERENCE VOLTAGE (V)
BI & BO VOLTAGES (mV)
0
50
100
TEMPERATURE (℃)
2.60
1020
1000
980
Brown In Voltage
960
Brown Out Voltage
940
920
900
880
-50
0
50
100
TEMPERATURE (℃)
Reference Voltage
2.55
2.50
2.45
2.40
-50
150
UVP and OVP Voltages vs. TJ
0
50
100
TEMPERATURE (℃)
150
OCL and OCP Thresholds vs. TJ
3.0
0.9
OCL & OCP THRESHOLDS (V)
UVP & OVP VOLTAGES (V)
Start-up Current
Quienscent Current
2.5
UVP Stop Threshold
OVP Trigger Threshold
2.0
1.5
1.0
0.5
0.0
-50
0
50
100
TEMPERATURE (℃)
150
0.8
0.7
0.6
0.5
0.4
0.3
0.2
OCL Threshold
OCP Threshold
0.1
0.0
-50
0
50
100
TEMPERATURE (℃)
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150
9
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 85VAC to 265VAC, VOUT = 400V, TA = 25°C, unless otherwise noted.
COMPI Voltage to Enter Burst On and
Off vs. TJ
0.8
140
0.7
120
COMPI VOLTAGE (mV)
ZCD VOLTAGE (V)
Zero-Current Detection Threshold vs.
TJ
0.6
0.5
0.4
0.3
0.2
ZCD falling
ZCD rising
0.1
0.0
100
80
60
40
0
-50
0
50
100
TEMPERATURE (℃)
150
-50
30
29
28
27
26
25
24
23
22
21
20
0
50
100
TEMPERATURE (℃)
150
On Time at Low and High Line vs. TJ
30
25
ON TIME (μs)
MAXIMUM DEAD TIME (μs)
Maximum Dead Time vs. TJ
20
On time at low line
15
On time at high line
10
5
DT_MAX
-50
0
50
100
TEMPERATURE (℃)
0
150
-50
No-Load Consumption
29.7
30
150
99%
31.5
98%
97%
23.8
25
0
50
100
TEMPERATURE (℃)
Efficiency
35
21.6
EFFICIENCY
NO-LOAD CONSUMPTION
(mW)
burst off
burst on
20
20
15
10
96%
95%
94%
93%
90VAC
120VAC
220VAC
260VAC
92%
5
91%
0
90%
60
90
120
150
180
VAC (V)
210
240
270
0%
20%
40%
60% 80%
LOAD
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100% 120%
10
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 85VAC to 265VAC, VOUT = 400V, TA = 25°C, unless otherwise noted.
Power Factor
THD
14
100%
12
10
THD (%)
PF
98%
96%
8
6
94%
4
92%
120VAC
240VAC
90%
40% 50% 60% 70% 80% 90% 100% 110%
LOAD
2
120VAC
240VAC
0
40% 50% 60% 70% 80% 90% 100% 110%
LOAD
Harmonics
VIN = 230VAC, POUT = 240W
HARMONIC RATIO (%)
35
MP44018A
30
IEC 1000-3-2 Class C
25
20
15
10
5
0
3
7
11 15 19 23 27 31 35 39
HARMONIC ORDER
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 85VAC to 265VAC, VOUT = 400V, TA = 25°C, unless otherwise noted.
Steady State
Steady State
VIN = 120VAC, POUT = 240W
VIN = 120VAC, POUT = 120W
CH1: GATE
CH1: GATE
CH2: VDS
CH2: VDS
CH4: IL
CH4: IL
Steady State
Steady State
VIN = 230VAC, POUT = 240W
VIN = 230VAC, POUT = 120W
CH1: GATE
CH1: GATE
CH2: VDS
CH2: VDS
CH4: IL
CH4: IL
CH2: VBUS
Start-Up
Start-Up
VIN = 120VAC, POUT = 240W
VIN = 230VAC, POUT = 240W
CH2: VBUS
CH1: COMP
CH4: IL
CH1:
COMP
CH4: IL
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 85VAC to 265VAC, VOUT = 400V, TA = 25°C, unless otherwise noted.
Shutdown
Shutdown
VIN = 120VAC, POUT = 240W
VIN = 230VAC, POUT = 240W
CH2: VBUS
CH2: VBUS
CH1: COMP
CH1: COMP
CH4: IL
CH4: IL
Brown-In
Brownout
POUT = 240W
POUT = 240W
CH3: VAC
CH3: VAC
CH1: COMP
CH1: COMP
CH2: VBUS
CH4: IL
CH2: VBUS
CH4: IL
Load Transient
Load Transient
VIN = 120VAC, 0W to 240W
VIN = 230VAC, 0W to 240W
CH2: VBUS
CH2: VBUS
CH1: COMP
CH1: COMP
CH4: IL
CH4: IL
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
FUNCTIONAL BLOCK DIAGRAM
MAINSIN
+
OTP
BI/BO
50ms
1V/0.9V
TSD
2
VCC
+
PWM
10.7V/8.6V
DT
x
VAC_PK
UVLO
Peak
Holder
FAULT
UVP
BIBO
OCP
kVAC2
PWM
Restart
=180µs
S
Q
R
Q
GATE
SOFF
COMP
STOP
+
OVP
ZCD
LEB
TCD
S Q
R
PWM
COM
tON_MAX
-
-
+
0.75V
0.25V
SOFF
ZCD
THD_DIS
STOP
RAMP Circuit
THD
Improver
UVP
LEB time
300ns
+
PFOK
OCL
-
0.5V
+
-
Burst
PWM
2.7V/2.6V
-
Blank
55µs
+
0.36V/0.4V
kVAC2 TCD
CS
+
PFOK
PWM
GND
Blanking
22µs
-
UVLO
60mV
/120mV
+
2.35V/
2.05V
1/3
LEB Time =
250ns
0.75V
OCL
OCP
OVP
BURST
SOVP
2nd OVP
+
Consecutive
Count = 3
-
S Q
R
OCP
0.8V
UVLO
+
FAULT
STOP
FAULT
OCP
Timer
= 80ms
FB
Gm
2.5V
OCP
COMP
Figure 1: Functional Block Diagram
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
OPERATION
The MP44018A is designed to provide simple,
high-performance active power factor correction
(PFC) using minimal external components.
CrM/DCM multi-mode allows the MP44018A to
operate in transition mode at heavy load. Multimode allows the device to then convert
seamlessly into discontinuous conduction mode
(DCM) at light loads, which maximizes operating
efficiency.
The MP44018A features a very low supply
current, which meets typical standby power
requirements. The no-load power is usually
below 30mW.
Start-Up and Brown-In
Figure 2 shows the typical start-up timing
diagram.
As VCC gradually builds up and reaches VCC_ON
(typically 10.7V) at time t1, the IC is enabled.
Then the IC starts to sense the brown-in
condition through MAINSIN. When the sampled
peak voltage exceeds VMAINS_BI (typically 1V), it
starts to switch at time t2. The MP44018A
implements a COMP soft start-up, and the bus
voltage achieves its regulation voltage at t3.
PFC VOUT
VREC
t
VCC
At this point, the PFC stops switching and COMP
is pulled down to zero. The device restarts with
a COMP soft start if the peak MAINSIN voltage
exceeds VMAINS_BI (typically 1V).
Enhanced Dynamic Response
The boost PFC output voltage is sensed on FB,
and is compared with the internal reference VR
(typically 2.5V) (see Figure 13 on page 19). RO1
is recommended to be 10MΩ to minimize power
consumption. RO2 can be calculated with
Equation (1):
RO2
RO1 VR
VO VR
(1)
The voltage compensation tank is connected
from COMP to GND. Proportional integral (PI)
control with a high-frequency pole is typically
used for compensation.
Figure 3 shows a nonlinear GM, which achieves
both good loop regulation in steady state and
enhanced dynamic response during load
transient. If the output voltage is detected with an
undershoot of 4%, the gain increases to four
times the normal gain. A higher gain can pull up
COMP quickly and reduce the voltage drop
during load step.
If the output voltage is above or below the normal
voltage with an overshoot of 4%, the gain
increases to eight times the normal gain. This
ensures that COMP is quickly pulled down to
avoid triggering over-voltage protection (OVP).
PFC_VCCON =
10.7V
PFC_VCCOFF =
8.7V
t
COMP
0.8
(typically 50ms) ends at t5. Then the IC confirms
the brownout condition.
t
ICOMP
BO Timer out =
50ms
BIBO
t
UVLO
70µA
300µs
t
FAULT
100µs
t
10µA
PFC_GATE
t
t1
t2
t3
t4
-10µA
2.5
2.2
2.6
2.4
2.65
FB
t5
Figure 2: Start-Up and Brown-In/Brownout
Brownout Function
The AC peak voltage is continuously sensed by
MAINSIN. Because the AC peak voltage falls
below VMAINS_BO (typically 0.9V) at t4, the device
continues switching until the brownout timer
0.8ms
-50µA
Figure 3: Nonlinear GM
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
Valley Switching
To minimize the switching loss, the MP44018A
always achieves valley switching through zerocurrent detection (ZCD) under any condition,
regardless of whether the device is operating in
DCM or critical conduction mode (CrM). Figure 4
shows the internal functional block and its
peripheral circuitry.
RZCD
VO
(3)
N IZCD _ MAX
A restart timer (tZCD_TO) of 180µs generates a
signal to turn on the MOSFET after it switches
off. This also allows the MOSFET to turn on
during the start-up period, since no valley signal
can be detected on ZCD.
L1
IL
RZCD
tR
VDS
ZCD
VO
VIN
LEB
2VIN - VO
-
SOFF
+
0.75V
0.25V
GATE
DT
Restart =
180µs
S
Q
R
Q
RG
tON
R4
DT
ZCD
CS
LEB
ZCD
LEB
STOP
tSMIN
(VO - VIN) / N
150ns ZCD delay
time can be tuned
with the capacitor on
ZCD
RCS
0.75V/0.25V
0
ZCD
Detection
-
+
COM
RAMP
-VIN / N
VCOMPD
GATE
Figure 4: ZCD Functional Block
A leading-edge blanking time (tZCD_LEB) of about
0.3µs is inserted to filter out the noise on ZCD
right after the gate turns off.
The positive voltage on ZCD must exceed VZCD_H
(typically 0.75V), then drop below VZCD_L
(typically 0.25V) for the next trigger condition. In
addition to waiting for a ZCD trigger condition,
the actual turn-on action should wait for the end
of the dead time extension (DTE) signal (see the
Frequency Reduction Function section below).
As soon as the DTE signal ends and the ZCD
trigger condition is fulfilled, the controller
switches on the MOSFET after a delay time
(tZCD_DELAY) of 150ns at the minimum drain source
voltage (see Figure 5).
The turn ratio of the auxiliary winding is
determined by a sufficient positive voltage,
estimated with Equation (2):
n<
VO 2VAC
0.75
COMP
Ramp
Figure 5: ZCD Timing Diagram
Frequency Reduction Function
The MP44018A reduces the switching frequency
with DTE technology under light loads. The
MP44018A works in CrM under heavy loads. In
CrM, the PFC’s frequency increases as the load
reduces, which means the switching loss
becomes dominant. The MP44018A gradually
inserts a dead time (tD) as the load becomes
lighter.
Figure 6 shows how the dead time is extended
when the COMP voltage drops.
tD
22µs
(2)
Where VAC is the maximum RMS input voltage.
RZCD can be calculated with Equation (3):
VCOMPI_BOFF
VCOMPI_C2D
VCOMPI
Figure 6: Dead Time Extension
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
The maximum dead time (tDEAD_MAX) is 23µs,
when COMP reaches its minimum voltage and
linearly reaches zero as the internal COMP
(VCOMPI) approaches the threshold VCOMP_C2D
(typically 0.38V).
With this control scheme, the system alternates
between CrM and DCM smoothly as the load is
gradually reduced. This means the switching
frequency is automatically reduced for maximum
efficiency as shown in figure 7 and figure 8.
VAC = 230V
During the burst-off period, the IC shuts down
most of internal block and ensures that the
supply current is below IQ (typically 180µA).
100% Load
fSW
(Hz)
Based on how the COMP voltage indicates load
information, the controller enters DCM. It enters
burst mode at certain loads to improve light-load
efficiency and standby power loss. As the load
decreases, COMP gradually drops. When VCOMPI
drops below VCOMPI_BOFF (typically 60mV),
switching stops with five soft-off pulses. As
VCOMPI ramps up to VCOMPI_BON (typically 120mV),
switching resumes with five soft-on pulses. This
soft-on/off control avoids abrupt inductor current
changes, and attenuates the acoustic noise
accordingly.
Improved THD
Under heavy loads, the MP44018A works in CrM.
The average input current in one cycle can be
estimated with Equation (4):
64%
Load
25% Load
π
θ
Figure 7: Switching Frequency in a Line Cycle
IIN ( )
v AC ( )
v ( )
t ON ( ) AC
2L
REQ1
Where VAC is the RMS of the line voltage,
calculated with Equation (5):
v AC ( ) 2VAC sin( )
VAC = 90V
REQ1
VAC = 265V
0%
20%
40% 60%
Load
80%
100%
Figure 8: Switching Frequency vs. Load
Burst Mode Operation
Figure 9 shows a burst mode control diagram.
Vo
(5)
And REQ1 is the equivalent input resistor, which
can be can be calculated with Equation (6):
fSW
(Hz)
430v
400v
393v
383v
(4)
OVP
2L
t ON ( )
(6)
Where tON (θ) is the on time.
Since tON (θ) is generated by an internal ramp
current compared to the COMP voltage, tON (θ)
stays constant in one AC line cycle. REQ behaves
like a resistant load. This means the input
average current is proportional to VAC (θ).
Along with reducing the load, the MP44018A
gradually works from CrM to DCM to reduce the
switching loss in light-load.
Io
Soft On
ip
Soft
Off
IL
t
COMPI
tON
120mV
60mV
0
Figure 10: DCM Operation
Figure 9: Burst Mode Control
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
The average input current in one cycle can be
estimated with Equation (7):
IIN ( )
v AC ( )
v ( )
t ON ( ) DC ( ) AC
2L
REQ2
(7)
Where REQ2 can be estimated with Equation (8):
REQ2
2L
tON ( ) DC ( )
To compensate for the mains input voltage
influence, the MP44018A contains a square of
VAC compensation circuits. The AC peak voltage
is sensed at MAINSIN, and is fed to the
generation of internal ramp current.
The internal COMP voltage can be estimated
with Equation (14):
(8)
VCOMPI
And DC can be estimated with Equation (9):
DC ( )
t ON tOND
t ON tOND tD
(9)
A dedicated variable-on-time control circuit is
integrated, and tON can be calculated with
Equation (10):
t ON ( )
DC ( )
2L
tON
MAINSIN =
1V
MAINSIN =
3.38V
2.1µs
VCOMP_L
VCOMP_H
(12)
This means the AC transient response is
suboptimal due to the square of the mains input
voltage.
Over-Current Limit (OCL)
Figure 12 shows the block diagram of overcurrent limit (OCL) and over-current protection
(OCP). The current is sensed by the CS pin. It
can limit the current cycle by cycle when CS
exceeds VOCL (0.5V). An LEB time (tOCL_LEB) of
300ns is applied during OCL to avoid
mistriggering the OCL due to a spike current
raised by discharging the drain-source capacitor
of the MOSFET.
Gate
CS
LEB Time
= 300ns
LEB Time
= 250ns
(13)
VCOMP varies between low-line and high-line. For
general design, the burst mode load is
determined by VCOMP. In high-line, the converter
easily enters burst mode in heavy load condition.
The audible noise comes out accordingly.
+
0.75V
OCL
-
0.5V
The COMP voltage (VCOMP) can be estimated
with Equation (13):
1
VCOMP ~
VAC2
VCOMP
Figure 11: tON vs. COMP
(11)
Mains Compensation
The input power for the boost PFC converter can
be estimated with Equation (12):
VAC2
t ON
2L
Figure 11 shows tON.
(10)
REQ2 also behaves like a resistant load, and the
input average current is proportional to VAC (θ).
PIN
(14)
Where KMAIN is the voltage divider ratio of
MAINSIN, and KRAMP is equal to tON_LL (typically
24µs/V).
24µs
Where is a constant defined by the internal
parameters. REQ2 can also be calculated with
Equation (11):
REQ2
KMAIN2
4 L PIN
KRAMP
+
Consecutive
Count = 3
S Q
R
-
OCP
UVLO
OCP
Timer
= 80ms
OCP
Figure 12: OCL and OCP
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
Over-Current Protection (OCP)
A second OCP is also integrated in CS with a
shorter LEB time (tOCP_LEB) of 250ns. If the CS
voltage exceeds VOCP (typically 0.75V) in two
consecutive 180µs restart switching cycles, the
OCP flag is triggered and the IC stops switching.
OCP is reset by an auto-recovery timer (tOCP_R)
of 80ms, or brown-in, brownout, or VCC UVLO.
OCP only protects from big faults, such as an
inductor short or a bypass diode short.
Under-Voltage Protection (UVP) and OverVoltage Protection (OVP)
The scaled-down voltage is connected to FB,
which is the input of the under-voltage protection
(UVP) and over-voltage protection (OVP)
comparators, as well as the error amplifier.
The UVP function can disable switching when
FB is open, or the FB feedback loop is open.
The UVP and OVP comparators value are set as
below:
OVP: 108% of VR. Normal operation
resumes at 104% of VR.
UVP: 12% of VR. Normal operation resumes
at 16% of VR.
The UVP comparator shuts down operation if FB
drops below 0.36V for a blanking time (tBL_UVP) of
55µs. The UVP comparator’s hysteresis is 40mV.
COMP is discharged to zero, and the device’s
supply current is reduced to a minimum when
UVP is triggered.
+
+
PFOKc
+
-
2.7V/2.6V
+
Blanking
55µs
UVP
Burst
Figure 13 shows that if the FB voltage exceeds
the OVP trigger threshold (typically 2.7V), the
OVP comparator shuts down the output of the
gate drive circuit after a blanking time (tBL_OVP) of
22µs. Switching resumes when FB drops to
2.62V.
-
Blanking
22µs
OVP
-
UVLO
60mV
120mV
0.36/0.4
2.35V/2.05V
VO
R1
1/3
FB
0.8V
Gm
1
+
FAULT
2.5V
R2
Burst
COMP
RZ
CP
CZ
Figure 13: FB Function Block
Gate Driver
The IC includes a push-pull gate driver that can
directly drive the MOSFET. The peak source
current is 600mA, and the peak sink current
capability is 1A.
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
APPLICATION INFORMATION
Design Requirements
Table 1 lists recommended design requirements.
Table 1: Recommended Designs
Parameter
Symbol
Input AC RMS voltage
Input AC voltage
frequency
Output voltage
Output voltage ripple
Output voltage OVP
threshold
Output power
Efficiency
VO
VO_RIPPLE
Value
85VAC to
265VAC
47Hz to
63Hz
400V
≤3% VO
∆OVP
40V
PO
η
240W
≥93%
VAC
fLINE
Power Stage Design
Selecting the Bridge
The diode bridge should withstand the maximum
reverse input AC voltage and the maximum input
current. When selecting a diode bridge, consider
the maximum instantaneous voltage (the peak
voltage of the line voltage), and the maximum
input RMS current (the input RMS current at lowline). In addition, package size and thermal
performance should also be considered. To
handle the line frequency current, use a standard
low-cost diode bridge with slow recovery.
In this case, the maximum input RMS current
can be calculated with Equation (15):
IAC_MAX
PO
=
= 3.04(A)
MIN VAC_MIN
(15)
The maximum instantaneous voltage can be
estimated with Equation (16):
VIN_MAX = 2 VAC_MAX = 375(V)
(16)
A standard 600V/8A bridge can be selected to
provide enough margin.
Selecting the Input Capacitor
The input capacitor before the boost inductor is
used to provide a bypass path for the high
switching frequency current, and to minimize
fluctuation on the rectified sinusoidal input
voltage. In general, a voltage drop up to 10% on
the input capacitor may be expected. The worstcase scenario occurs when the input voltage is
below its minimum threshold voltage due to a
large current ripple.
The input capacitor (CIN) can be calculated with
Equation (17):
CIN =
IAC_MAX
(17)
2 fSW r VAC_MIN
Where r is the coefficient (0.01 to 0.1), and fSW is
the switching frequency at the peak of the
minimum input AC voltage.
Select a capacitor with good high-frequency
performance, such as a film capacitor. Assume
a minimum fSW (e.g. 40kHz) and set coefficient r
to be 0.05. The input capacitance can be
calculated with Equation (18):
CIN =
IAC_MAX
2 fSW r VAC_MIN
= 2.85F (18)
Two 1μF film capacitors with a 450V voltage
rating are recommended as the input capacitors
because they provide high-frequency energy
during the switching cycle.
Boost Inductor Design
The boost inductance value (LMAX), which is
required to ensure that the maximum load can
be delivered from the minimum input voltage,
can be estimated with Equation (19):
LMAX =
V 2 AC_MIN t ON_MAX
2 PO
(19)
The boost inductance value should be below
LMAX. A normal inductance is recommended to
use 60%-70% ratio of LMAX to avoid tON being
close to tON_MAX.
If ratio is selected as 60%, the actual inductance
of this case is,
L ACTUAL =
V 2 AC_MIN tON_MAX Ratio
2 PO
= 182H (20)
The boost inductance value should exceed LMIN.
To avoiding triggering over-current protection
(OCP) when triggering the over-current limit
(OCL), there is a delay time (tCS_DELAY) of 100ns,
as well as a MOSFET turn-off delay.
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
The minimum boost inductance
estimated with Equation (21):
LMIN =
2VAC_MAX 300ns
VOCP_OCL
can
be
RCS = 37.5H (21)
Selecting the Boost MOSFET
The voltage rating of the MOSFET is determined
by the output voltage, over-voltage protection
(OVP) threshold, plus some margin, such that
VDS > VO + ΔVOVP. The current rating of the
MOSFET is determined by the RMS value of the
current flowing through the MOSFET.
VDS can be calculated with Equation (22):
VDS > VO + ∆VOVP = 440V
(22)
The RMS current of MOSFET can be estimated
with Equation (23):
1 4√2 VAC_MIN
IQRMS =2√2×IAC_MAX ×√6 - 9π × V
=3A
O
(23)
In addition, the MOSFET pulsed-drain current
should exceed the peak inductor current,
calculated with Equation (24):
ID_PULSE > ILPK_MAX = 2√2×IAC_MAX = 8.6A (24)
Selecting the Boost Diode
The boost diode should have the same voltage
rating as the boost MOSFET.
The average current of output diode is the same
as the output current of PFC regulator,
calculated with Equation (25):
IDAVG = IO = 0.6A
(25)
To estimate the power consumption of the diode,
the RMS current can be calculated with Equation
(26):
4√2 VAC_MIN
×
9π
VO
IDRMS = 2√2×IAC_MAX ×√
= 1.82A (26)
The boost diode must have average and RMS
current ratings that exceed IDAVG and IDRMS,
respectively.
Diodes are available with a range of different
speed/recovery charges. Fast diodes typically
have higher conduction loss but lower switching
loss. Slow diodes typically have lower
conduction loss but higher switching loss.
Maximum efficiency is achieved when the diode
speed rating matches the application. In this
case, a boost diode with a fast recovery is
recommended.
Selecting the Output Capacitor
Consider the following when selecting an output
capacitor: the output voltage ripple (VO_RIPPLE),
ripple current rating, and hold-up time.
The output ripple is a function of the effective
series resistance (ESR) of the capacitor, the
output voltage, and the line frequency (fLINE). The
output ripple can be estimated with Equation (27):
VO_RIPPLE = 2x
PO
1
2
x√(2π×2f
2 +ESR
VO
LINE xCO )
(27)
In this case, the calculated ripple with the
selected capacitor should be below 3% of the
output voltage, and the ESR of the output
capacitor is assumed to be 1Ω. CO can be
calculated with Equation (28):
CO ≥
1
2
3%×V2
O ) -ESR2
2πx2fLINE √(
2xPO
= 160μF
(28)
To ensure that the error amplifier’s nonlinear
gain is not activated by the extremes of the
output voltage ripple, the output voltage ripple
amplitude should satisfy the condition calculated
with Equation (29):
VO_RIPPLE
VO
≤
2x100mV
VR
= 8%
(29)
The maximum RMS ripple current flowing in the
output capacitor can be estimated with Equation
(30):
P 2
VO
IO_RIPPLE_MAX =√I2DRMS - ( O ) = 1.72A
(30)
This current flowing into the output capacitor is
made up of a switching frequency component
(50Hz) and a twice line frequency ripple
component (100kHz), calculated with Equation
(31) and Equation (32), respectively:
IO_RIPPLE_50Hz =
1
√2
P
x VO = 0.424A
O
3
(31)
2
P
IO_RIPPLE_100KHz =√I2DRMS - 2 x (VO ) = 1.67A (32)
O
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MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
The capacitor should be chosen so that the holdup time satisfies the relationship calculated with
Equation (33):
CO =
2∙PO ×tHOLDUP
2
2
η×(VO -VO_HOLDUP )
(33)
Where VO is the minimum output voltage under
all normal operating conditions, and VO_HOLDUP is
the required minimum operating output voltage
to supply the downstream DC/DC converter
when the line voltage is shut down. The
maximum voltage at the output is a combination
of the output voltage, output voltage ripple, and
OVP threshold. Therefore, the voltage rating of
the capacitor must be greater than this maximum
output voltage at the worst case.
In this example design, an aluminum electrolytic
capacitor with specification of 450V/180µF is
recommended.
Control Circuit Design
The VCC Pin
If an external VCC power supply is not used, a
simple approach to handling start-up is to use a
start-up resistor connected to the input AC
voltage. As the VCC capacitor’s charge rises
above the turn-on threshold through the start-up
resistor, the IC begins to work.
The MP44018A needs a minimum 40µA start-up
current when VCC is 9.5V. The start-up
resistance can be calculated with Equation (34):
RSTARTUP ≤
√2xVAC_MIN -9.5
ISTARTUP
= 2.9MΩ
(34)
Since the start-up resistor causes a voltage drop
between the input AC voltage and the supply
voltage of the chip, use a resistor with higher
resistance to minimize the power consumption.
The FB Pin
VO can be set by using the appropriate FB
resistors. Output voltage regulation accuracy
degrades with higher-value resistors due to the
effect of the FB bias current. Ensure that the FB
bias current degrades the output voltage
regulation less than 1%, by calculating the upper
voltage divider resistor value with Equation (35):
RO_UPPER ≤ 1%x I
VO
O_BIAS
= 40MΩ
(35)
Considering the power consumption, it is
recommended to use three 3.3MΩ resistors in
series for the FB upper voltage divider resistor.
The lower voltage divider resistor value can be
calculated with Equation (36):
RO_LOWER = V
VR
O -VR
xRO_UPPER = 62.3kΩ
(36)
The MAINSIN Pin
The MAINSIN voltage range related to VAC range
is between 1V and 3.38V. In this case, an 85VAC
voltage can be set as the brown-in voltage. The
MAINSIN voltage divider can be calculated with
Equation (37):
RI_LOWER
RI_LOWER +RI_UPPER
=
VMAINS_BI
VAC_MIN
=
1
120
(37)
Considering the power consumption, a highervalue resistor is recommended. In this case,
three 3.3MΩ resistors in series is recommended
for the MAINSIN upper voltage divider resistor.
The lower voltage divider resistor value can be
calculated with Equation (38):
RI_LOWER =
RI_UPPER
120-1
= 83.2kΩ
(38)
The CS Pin
CS is used for OCP and OCL. The current
flowing through the MOSFET should be below
the OCL threshold. The CS resistor value can be
estimated with Equation (39):
RCS ≤
VOCL
2√2xIAC_MAX
= 58mΩ
(39)
In this case, two 100mΩ resistors in parallel are
recommended (specifically, two 2512 SMT
resistors).
To enhance the ability of anti-interference, a 1kΩ
resistor is connected in series to CS. To pass the
surge test, a 100pF capacitor must be connected
from CS to GND.
The ZCD Pin
The ZCD resistor connects the ZCD of the chip
to the auxiliary winding. The main purpose of the
resistor is to avoid excessive current on ZCD.
Therefore, a minimum ZCD resistor is required
to ensure that the current flowing through ZCD is
below the ZCD maximum current under the
maximum auxiliary winding voltage. The ZCD
current can be calculated with Equation (40):
IZCD =
VAUX_MAX -VZCD_CLAMP
RZCD
≤ 10mA
(40)
Where VAUX_MAX is the maximum voltage on the
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22
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
auxiliary winding (VO / N), N is the ratio of winding,
and VZCD_CLAMP is the upper clamp voltage of the
ZCD pin.
In addition, the auxiliary winding voltage cannot
be so low such that it triggers the zero-current
sense threshold, which controls the gate of
MOSFET to turn off. This threshold can be
calculated with Equation (41):
VAUX_MIN =
VO -√2xVAC_MAX
N
≥ 0.75V
(41)
Where N can be estimated with Equation (42):
N≤
VO -√2xVAC_MAX
0.75
= 34
(42)
Considering the design of the boost inductor,
26:3 is selected as the winding ratio. Then RZCD
can be calculated with Equation (43):
RZCD ≥
VAUX_MAX -VZCD_CLAMP
10mA
= 3.8kΩ
(43)
The COMP Pin
Based on the small signal modeling, the control
to output voltage transfer function (resistive load)
can be estimated with Equation (44):
KRAMP
2
3×KMAIN
x 2V
1
x
O CO L
1
2
+s
RO CO
(44)
In this case, GVC is calculated with Equation (45):
4706.67
s+16.67
+s
1
CZ RZ
x
C
+C
Z P +s
CP xs
(46)
CZ CP RZ
Where KFB is the FB voltage divider ratio, and
GM1 is the transconductance value when FB is
about equal to VR (about 104µs).
Then the open voltage loop transfer function can
be calculated with Equation (47):
G(s) = GVC (s)xGEA (s)
(47)
In this case, to design a high-stability voltage
loop, 12Hz is recommended as a suitable
crossover frequency, and the phase margin must
exceed 45°. 5Hz is the recommended zero value,
and 50Hz is designed as the pole with high
frequency.
RZ = K
-ΦVC (12)
1
20
x10
=
FB xGM1
28.5kΩ
(48)
Where CZ can be estimated with Equation (49):
1
CZ = 2πx5xR = 1.1μF
Z
(49)
And CP can be estimated with Equation (50):
Where KMAIN is the MAINSIN voltage divider ratio,
and KRAMP is equal to tON_LL.
GVC (s) =
1
GEA (s) = KFB xGM1 x
The value of the compensation network can be
calculated with Equation (48):
RZCD is recommended to be 33kΩ.
GVC (s) =
The transfer function of the transconductance
amplifier can be calculated with Equation (46):
(45)
CP =
1
=
2πx50xRZ
0.1μF
(50)
RZ = 30kΩ, CZ = 1µF, and CP = 220pF are the
recommended values of the compensation
network.
In addition, the voltage error amplifier is a
transconductance amplifier. The voltage
compensation tank is connected from COMP to
GND. A Type-II compensation network is
recommended.
MP44018A Rev. 1.0
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23
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
PCB Layout Guidelines
PCB layout is a critical factor for stable operation
and EMI performance. The device can
malfunction due to noise coupling. For the best
results, refer to Figure 14 and follow the
guidelines below:
CO
RCS
Loop 1
D2
D3
RO1
RG
VCC
VCC
GATE
RIN1
C2
C5
NS
MP44018A
FB
RO2
C6
Cz
RIN2
C4
Cp
Rz
C3
COMP
R4
CS
4. Separate the reference ground of the IC and
control signals circuit from the ground of the
power loop. Then connect this signal ground
to the ground of the output capacitor with a
single-point junction.
Q1
RZCD
CX1
MAINSIN
3. Make the areas of high dV/dt junctions (e.g.
the drain of the external primary MOSFET)
as small as possible. Place the IC and control
circuits far away from these areas.
C1
VAC
GND
2. Do not place the IC in power loop 1 or power
loop 2.
VO
Loop 2
F1
ZCD
1. Make power loop 1 and power loop 2 as
small as possible.
D1
L1
BD1
Figure 14: Recommended PCB Layout
5. Connect the VCC-GND capacitor close to IC.
6. Connect the FB-GND capacitor close to IC.
7. Connect the MAINS-GND capacitor close to
IC. Ensure that the CS wiring does not cross
MAINSIN. Otherwise, the CS noise may
couple to MAINSIN and impact peak voltage
sensing.
8. If the PFC stage is connected to a cascade
DC/DC stage, separate both GNDs with an
output capacitor, so that GND noises do not
interfere with one another.
MP44018A Rev. 1.01
MonolithicPower.com
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24
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
TYPICAL APPLICATION CIRCUIT
Figure 15: MP44018A Typical Application Circuit
MP44018A Rev. 1.01
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25
MP44018A – CRM/DCM MULTI-MODE PFC CONTROLLER
CONTROL FLOWCHARTS
Start
N
VCC > VCC_ON
Y
Monitor
VMAINSIN
N
VMAINSIN >
VMAINS_BI
Y
Brown-In
Main On
Figure 16: Start-Up Flowchart
Main On
UVP
OCL
OCP
OVP
Monitor VFB
Monitor VFB
Monitor VCS
Monitor
VMAINSIN
VCS > 0.5V
VMAINSIN <
0.9V
N
VFB > 2.7V
N
N
VCS > 0.75V
Y
Y
Stop
Switching
Stop
Switching
N
Clear
Counter
Y
Consecutive
Counter = 3
Y
N
VFB < 2.62V
Stop
Switching
Y
Resume Switching
N
>150°C?
Y
VMAINSIN > 1V
Y
Stop
Switching
Stop
Switching
Y
BO Timer = 0
BO Timer =
50ms
N
Y
BIBO = 0
Resume switching
after ZCD, or restart
the timer after
180µs elapses
Y
Resume Switching
after 80ms
FAULT = 1
FAULT = 0
Stop
Switching
N
FAULT = 1
COMP = 0
VFB > 0.4V
Y
N
BO Timer Start
Y
Fault = 1
COMP = 0
OTP
Monitor Temp
BI
N
VFB < 0.36V
BO
Monitor VCS
Start
BIBO = 1
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