MP4575GF-Z

MP4575 5A, 4.5V - 55V Input, Frequency-Programmable, Fully Integrated, Synchronous, Step-Down Converter DESCRIPTION FEATURES The MP4575 is a frequency-programmable, step-down, switching converter with integrated, internal, high-side and low-side power MOSFETs. The MP4575 can provide 5A of continuous output current with peak current control for excellent transient response and efficiency performance.   The wide 4.5V to 55V input voltage range accommodates a variety of step-down applications, including industrial, PoE, automotive, and printers with a DC high-voltage bus. The MP4575 uses peak-current-mode control to regulate the output voltage. The MP4575 provides over-current protection (OCP) with valley current detection, which is used to prevent the current from running away. The MP4575 also has accurate and reliable overvoltage protection (OVP) and auto-recovery thermal protection. An optional external soft start is available. Enable and power good indication functions can be used to track the power easily. To increase efficiency, the MP4575 scales down the switching frequency automatically when the load is light. Meanwhile, the low-side MOSFET is turned off to reduce driver loss when zero inductor current is detected.           Wide 4.5V to 55V Input Voltage Range 90mΩ and 70mΩ Internal High-Side and Low-Side Power MOSFETs Peak-Current-Mode Control Programmable Switching Frequency Optional External Soft Start Over-Current Protection (OCP) with Valley Current Detection Supports External Synchronous Clock Over-Voltage Protection (OVP) Current Limit Decreases during Output Short for Better Thermal Performance Power Good Indication Thermal Shutdown Protection Available in a TSSOP-20 EP Package APPLICATIONS      PoE Input Non-Isolated Buck Industrial Power Systems Printers and Scanners Automotive Power Systems Distributed Power Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. Synchronous operation mode with the integrated low-side MOSFET is useful for reducing conduction loss and reducing external components space to save cost. The MP4575 is available in a TSSOP-20 EP package with an exposed pad. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 1 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL APPLICATION L1 C1 OFF ON R5 VDD R4 C7 VIN SW EN BST PG MP4575 FREQ SS VDD R1 FB BIAS C5 MP4575 Rev. 1.0 8/16/2016 C2 C6 COMP GND 5V_EX or NC R2 R3 C4 C3 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 2 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER ORDERING INFORMATION Part Number* MP4575GF Package TSSOP-20 EP Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP4575GF–Z) TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP4575: Product code of MP4575GF LLLLLLLLL: Lot number PACKAGE REFERENCE 1 20 AGND FB 2 19 SS FREQ 3 18 EN 4 17 BIAS BST 5 16 VIN 6 15 GND VIN 7 14 GND VIN 8 13 GND NC 9 12 NC SW 10 11 SW COMP PG VDD TSSOP-20 EP MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 3 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (3) Supply voltage (VIN) ....................................60V VSW ................................... -0.5V to (VIN + 0.5V) VBS .......................................................VSW + 6V All other pins .................................. -0.3V to +6V EN sink current ........................................150μA Continuous power dissipation (TA = 25°C) (2) TSSOP-20 EP ......................................... 2.78W Junction temperature ............................... 150°C Lead temperature .................................... 260°C Storage temperature ................ -65°C to +150°C TSSOP-20 EP ....................... 45 ....... 10 ... °C/W Recommended Operating Conditions Supply voltage (VIN) ....................... 4.5V to 55V Output voltage (VOUT) ................... 1V to 0.9xVIN Operating junction temp. (TJ). .. -40°C to +125°C MP4575 Rev. 1.0 8/16/2016 θJA θJC NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 4 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 48V, VEN = 3.3V, TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units 0.98 1 10 540 20 1.02 50 720 30 V nA μA/V μA Error Amplifier (EA) Feedback voltage FB current Error amp transconductance COMP sink/source current VFB IFB 4.5V ≤ VIN ≤ 55V VFB = 1.07V 380 10 ICOMP Switch Characteristic Upper switch on resistance RON_HS 90 160 mΩ Lower switch on resistance RON_LS 70 120 mΩ Upper switch leakage ILKG_SW 10 300 nA 8.5 11 A 450 7 670 12 µA µA 3.4 4.6 3.6 4.8 3.8 V V VEN = 0V, VSW = 0V Current Limit Peak current limit ILIMIT 10% duty cycle IQ ISHDN No load, without switching VEN = 0V VDD VDD BIAS = NC BIAS = external 5V power 5.5 Quiescent Supply Quiescent supply current Shutdown supply current VDD Regulator VDD regulator output voltage VDD regulator output voltage Threshold Voltage EN rising threshold VEN_R 1.4 1.6 1.8 V EN falling threshold VEN_F 1.1 1.3 1.5 V EN threshold hysteresis VIN UVLO rising threshold VIN UVLO falling threshold VIN UVLO threshold hysteresis VEN_HYS 300 VINUV_R VINUV_F VINUV_HYS mV 3.7 3.3 3.9 3.5 400 4.1 3.7 V V mV 2.5 4 5.5 μA Soft Start (SS) External soft start capacitor charging current ISS VSS = 1V PWM Comparator Minimum off time (4) Minimum on time (4) MP4575 Rev. 1.0 8/16/2016 tOFF_MIN tON_MIN 100 90 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ns ns 5 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS (continued) VIN = 48V, VEN = 3.3V, TJ = 25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units RFREQ = 100kΩ 400 520 640 kHz VFB(OVP)/VFB 108 115 122 % VOUT rising, VFB(PG)/VFB 86 90 94 VOUT falling, VFB(PG)/VFB 81 85 89 Oscillator Frequency Switching frequency fSW Over-Voltage Protection (OVP) Output OVP threshold VOVP Power Good (PG) Power good threshold VPG_TH Power good hysteresis VPG_HYS Power good delay tPG_DL % ∆VFB(PG)/VFB 5 % VOUT rising 8 22 37 μs VOUT falling 8 21 33 μs 10 100 nA 1000 kHz Frequency SYNC SYNC leakage current ILKG_SYNC SYNC frequency range fSYNC 100 TSD 150 Thermal Thermal shutdown (4) Thermal shutdown hysteresis (4) TSD_HYS 170 °C 10 °C NOTE: 4) Derived from bench characterization. Not tested in production. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 6 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS VIN = 48V, unless otherwise noted. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 7 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS (continued) VIN = 48V, unless otherwise noted. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 8 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 48V, VOUT = 3.3V, COUT = 2x22µF, L = 10µH, fSW = 500kHz, TA = +25°C, unless otherwise noted. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 9 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VOUT = 3.3V, COUT = 2x22µF, L = 10µH, fSW = 500kHz, TA = +25°C, unless otherwise noted. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 10 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 48V, VOUT = 3.3V, COUT = 2x22µF, L = 10µH, fSW = 500kHz, TA = +25°C, unless otherwise noted. MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 11 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER PIN FUNCTIONS Pin # Name 1 COMP 2 FB 3 FREQ 4 EN 5 BST 6, 7, 8 VIN 9, 12 10, 11 13, 14, 15, Exposed Pad 16 NC SW GND Power ground for the internal power MOSFETs. VDD Power for the internal MOSFET driver and BST charging circuit. Optional supply for the internal circuit. For better thermal performance, connect BIAS to an external 5V source. VDD and the internal circuit are powered by BIAS. Since there is a diode between BIAS and the internal circuit, leave BIAS floating or connect it to GND if BIAS is not used. 17 BIAS 18 PG 19 SS 20 AGND MP4575 Rev. 1.0 8/16/2016 Description Compensation network setting. Connect an external resistor in series with a capacitor between COMP and GND. Feedback. FB is the input to the PWM comparator. Place an external resistor divider between the output and GND. Switching frequency setting. Connect a resistor from FREQ to GND to set the switching frequency. If an external synchronous clock is applied to FREQ, the converter follows this clock’s frequency. Enable input. Pull EN below the specified threshold to shut down the MP4575. There is no internal pull-up or pull-down circuit. Do not float EN. Bootstrap. BST is the positive power supply for the internal floating high-side MOSFET driver. Connect a capacitor between BST and SW. Input supply. VIN supplies power to all of the internal control circuitries and VDD regulator. A decoupling capacitor to ground must be placed close to VIN to minimize switching spikes. No connection. Leave NC floating. Switch node. SW is the output node from the internal high-side MOSFET source. Power good indicator. Connect a resistor to a pull-up power source if used. Optional external soft-start time setting. Connect an external capacitor between SS and GND to set the soft-start time externally. Float SS to activate the internal 0.5ms soft-start setting. Ground for internal logic and signal circuit. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 12 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER BLOCK DIAGRAM BIAS VDD Internal Regulator (2.5V) EN House Keeping Voltage Reference Current Reference BST VIN CLK LS DRVL LOW NO OC VDD Regulator (3.6V or 4.8V) HS DMOS Thermal Shutdown HS Current Limit COMP VIN UVLO SW FB Fsw Foldback 400mV ISW FREQ Setting PLL Fsw Setting FREQ CLK CLK ZC PLL ON PLL RB LS DMOS Q COMP Fsw Foldback SW LOW OC CPB ZC CLK 2V PGND PG FB 110%REF ISW FB SS_Internal 1V SS_Internal 90%REF COMP SS Figure 1: Functional Block Diagram MP4575 Rev. 1.0 8/16/2016 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 13 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER OPERATION The MP4575 is a step-down switching regulator with integrated, high-voltage, power MOSFETs. The MP4575 features a wide input voltage range, high efficiency, external and internal soft start, programmable frequency, and comprehensive protection modes. Pulse-Width Modulation (PWM) Control The MP4575 uses peak-current-mode control to regulate the output voltage. A PWM cycle is initiated by the internal clock at the beginning of every cycle. After the high-side MOSFET (HS-FET) turns on, the inductor current rises linearly to provide energy to the load. The HS-FET remains on until its current reaches the COMP voltage (VCOMP), which is the output of the internal error amplifier (EA). The output voltage of the EA depends on the difference of the output feedback voltage and the internal high-precision reference, and VCOMP decides how much energy should be transferred to the load. The higher the load current, the higher VCOMP. After the high-side switch is off, the low-side switch turns on, and the inductor current flows through the low-side switch. To prevent a shoot-through, a dead time is inserted to prevent the HS-FET and LS-FET from turning on at the same time. For each turnon and turn-off in a switching cycle, the HS-FET remains on and off with a minimum on and off time limit. Light-Load Operation The MP4575 can achieve high efficiency during light load in two ways. First, when the load current decreases, the inductor current drops at same time. The LS-FET turns off to save driver loss when the inductor current drops to zero. Second, when the load decreases, the switching frequency is scaled down to reduce switching loss after VCOMP drops below a certain threshold. Error Amplifier (EA) The error amplifier (EA) compares the FB voltage with the internal reference and outputs a current proportional to the difference between the two. This current is used to charge the external compensation networks to form VCOMP, MP4575 Rev. 1.0 8/16/2016 which is used to control the HS-FET peak current and regulate the output voltage. Oscillator and SYNC Function The internal oscillator frequency is set by a single external resistor (RFREQ) connected between FREQ and GND. The frequencysetting resistor should be located close to the device. The relationship between the oscillator frequency and RFREQ is shown in Table 1 on page 17. During light load, the switching frequency is scaled down according to VCOMP. The switching frequency begins decreasing when VCOMP is below about 0.8V. Switching is disabled when VCOMP drops below about 0.7V. To reduce switching loss and thermal dissipation, the switching frequency is decreased according to the FB voltage. When FB is lower than 25%xREF, the switching frequency starts to decrease from the normal value and drops to 5% of the normal value when FB is zero. FREQ can be used to synchronize the internal oscillator rising edge to an external clock falling edge. Ensure that the high amplitude of the synchronous (SYNC) clock is higher than 1.5V and the low amplitude is lower than 1V to drive the internal logic. The recommended external SYNC frequency is in the range of 100kHz and 1MHz. There is no pulse width requirement, but there is always a parasitic capacitance of the pad. If the pulse width is too short, a clear rising and falling edge may not be seen due to the parasitic capacitance. A pulse longer than 100ns is recommended in application. Enable (EN) Control Enable (EN) is a control pin that turns the regulator on and off. Drive EN higher than 1.6V to turn on the regulator; drive EN lower than 1.3V to turn off the regulator. There is no internal pull-up or pull-down circuitry at EN, so when EN is floating, its status is uncertain. EN is clamped internally using a 6.5V Zener diode between EN and GND. Connecting EN to a voltage source directly without any pull-up resistor requires limiting the voltage amplitude to ≤6V to prevent damage to the Zener diode. EN can be connected to a higher voltage (e.g.: VIN) through a pull-up resistor if the system www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 14 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER does not have another logic signal acting as the enable signal. Ensure that the pull-up resistor is high enough to ensure that the sink current going into EN is less than 150µA to avoid damaging the Zener diode. For example, when connecting EN to VIN = 12V, RPULL-UP ≥ (12V 6.5V) ÷ 150µA = 37kΩ. Soft Start (SS) Soft start (SS) is implemented to ensure a smooth start-up of the output voltage during power-on and power-off. The soft start function also helps to reduce inrush current at start-up. The soft start function is achieved by ramping SS up slowly and overriding the internal reference (REF) when SS - 900mV is lower than REF. When SS - 900mV is higher than REF, REF regains control. 900mV is the offset voltage of SS, which means that SS is detected as 0 internally when it is lower than 900mV. To minimize the delay for SS to reach 0.9V, an internal pull-up circuit with about 30µA of average current pulls SS up to 600mV first. Then use a 4µA constant current to charge SS until it reaches 2.5V. When SS is in the range of 0.9V to 1.9V, it overrides REF as the reference voltage of the error amplifier. During this period, the output voltage ramps up from 0 to the regulated value following SS rising. The softstart time (tSS) set by the external SS capacitor can be calculated with Equation (1): t SS (ms)  CSS (nF)  VREF (V) ISS ( μA) (1) Where CSS is the external SS capacitor, VREF is the internal reference voltage (1V), and ISS is the 4µA SS charge current. The delay time for SS reaching 900mV can be estimated with Equation (2): C (nF)  0.6V CSS (nF)  0.3V (2) t SS _delay (ms)  SS  30 μA 4 μA There is also an internal, fixed, 500µs soft start. The final SS time is determined by the longer time between 500μs and the external SS setting time. When the output voltage is shorted to GND, the feedback voltage is pulled low, and then SS is discharged. The MP4575 soft starts again when the short at the output is removed. MP4575 Rev. 1.0 8/16/2016 Internal Regulator and BIAS An internal 2.5V regulator powers all of the internal control circuits. This regulator uses VIN as the power supply when BIAS is lower than 3.2V and uses BIAS as the supply when BIAS is higher than 3.2V. The VDD regulator powers the low-side driver and the BST regulator when the VDD voltage is higher than 4.5V. VDD is powered by VIN when BIAS is floating and is regulated at 3.6V. When BIAS is higher than 4.2V, it powers VDD. VDD increases as BIAS rises with a 600mV voltage drop and is regulated at 4.8V when BIAS is higher than 5.4V. A 1µF decoupling capacitor is needed at VDD to make the capacitor as close to VDD as possible. Using BIAS to power the internal regulator can improve efficiency. It is recommended to connect BIAS to an external power supply in the range of 3.3V to 5.5V. The output voltage is a good choice for this power supply if it is in above range. A 0.1µF to 1µF decoupling capacitor at BIAS is recommended. Over-Voltage Protection (OVP) The MP4575 monitors the feedback output voltage to achieve over-voltage protection (OVP). If the FB voltage is higher than 103%xREF, the MP4575 switches to sleep mode, the HS-FET turn offs, and the LS-FET turns on to discharge the output energy. The MP4575 returns to normal after the FB voltage drops below 103%xREF. If the FB voltage is higher than 110%xREF, the HS-FET and LS-FET are turned off immediately. Both MOSFETs are latched, and the PG signal is asserted to indicate the fault status and if EN or VIN must be recycled to clear the protection. Over-Current Protection (OCP) The MP4575 has a cycle-by-cycle peak-currentlimit protection and valley current detection protection. The inductor current is monitored during the HS-FET on state. If the inductor current exceeds the current limit value set by VCOMP, the HS-FET turns off immediately. Then, the LS-FET is turned on to discharge the energy, and the inductor current decreases. The HS-FET does not turn on again until the inductor valley current is below a certain current www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 15 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER threshold (valley current limit). This is useful for preventing an inductor current runaway. Both the peak current limit and the valley current limit values are dependent on the FB voltage. If the feedback output voltage is higher than 50%xREF, the current limit value is normal. If the feedback output voltage is lower than 50%xREF, the current limit decreases to half the normal value when the feedback output voltage is zero. This feature is useful for reducing OCP thermal dissipation, which may worsen when the output voltage is shorted. It is also useful for reducing high inrush current during start-up. Under-Voltage Lockout (UVLO) Protection The MP4575 has an input under-voltage lockout (UVLO) protection. When EN is active, the MP4575 is powered on when the input voltage is higher than the UVLO rising threshold, and is powered off when the input voltage drops below the UVLO falling threshold. Thermal Shutdown Protection The thermal shutdown is employed in the MP4575 by monitoring the IC temperature internally. If the junction temperature exceeds the threshold (typically 170°C), the regulator shuts off and turns on again when the temperature drops below 160°C. There is a hysteresis of about 10°C. Power Good (PG) The MP4575 uses one power good (PG) pin out to indicate normal operation after the soft-start time. PG is the open drain of the internal MOSFET. PG should be connected to VDD or an external voltage source through a resistor (i.e.: 100kΩ). After the input voltage is applied, the MOSFET is turned on, and PG is pulled to GND before SS is ready. After the FB voltage reaches 90% of the REF voltage, the MOSFET turns off, and PG is pulled high by an external voltage source. When the FB voltage drops to 85% of the REF voltage, the PG voltage is pulled to GND to indicate a failure output status. MP4575 Rev. 1.0 8/16/2016 Floating Driver and Bootstrap Charging An external bootstrap capacitor (typically 0.1µF) between BST and SW powers the floating power MOSFET driver. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.3V with a hysteresis of 300mV. The driver’s UVLO is soft-start related. When the bootstrap voltage reaches its UVLO threshold, the soft-start circuit resets. When the bootstrap UVLO is removed, the soft-start reset is off, and the soft-start process resumes. The dedicated internal bootstrap regulator regulates and charges the bootstrap capacitor to 4.2V. When the voltage between the BST and SW nodes is less than its regulation, a PMOS pass transistor from VIN to BST turns on. The charging current path is from VIN to BST to SW. As long as VIN is sufficiently higher than VSW, the bootstrap capacitor can be charged. When the HS-FET is on, VIN ≈ VSW, so the bootstrap capacitor cannot be charged. When the LS-FET is on, the difference between VIN and VSW is at its largest, making this the best period to charge. When there is no current in the inductor, VSW = VOUT, so the difference between VIN and VOUT can charge the bootstrap capacitor. At higher duty cycles, the time period available for bootstrap charging is shorter, so the bootstrap capacitor may not be sufficiently charged. If the internal circuit does not have sufficient voltage, and the bootstrap capacitor is not charged, extra external circuitry can be used to ensure that the bootstrap voltage is within the normal operating region. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 16 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER APPLICATION INFORMATION Setting the Switching Frequency The MP4575 has an externally adjustable frequency. The switching frequency (fSW) can be set using a resistor at FREQ (RFREQ). Table 1 shows recommended RFREQ values for various fSW values. Refer to the fSW vs. RFREQ curve in the Typical Characteristics section on page 8 for more detailed values. Table 1: fSW vs. RFREQ fSW (kHz) 1000 900 800 700 600 500 400 300 200 100 RFREQ (kΩ) 47.5 56 63.4 73.2 84.5 102 133 178 261 523 Setting the Output Voltage A resistive voltage divider from the output voltage to FB sets the output voltage. The voltage divider divides the output voltage down to the feedback voltage by the ratio shown in Equation (3): VFB =VOUT  R2 VOUT =VFB  R1+R2 (3) R1+R2 Calculated the output voltage with Equation (4): (4) R2 For example, if R1 is 10kΩ, then R2 can be calculated with Equation (5): 10 (5) R2  kΩ VOUT  1 So for a 3.3V output voltage, R1 is 10kΩ, and R1 is 4.32kΩ. Selecting the Inductor The inductor provides a constant current to the output load while being driven by the switched input voltage. A larger-value inductor results in a lower ripple current and lower output ripple voltage, but also is physically larger, has a MP4575 Rev. 1.0 8/16/2016 higher series resistance, and lower saturation current. To determine the inductance, allow the inductor’s peak-to-peak ripple current to equal approximately 30% of the maximum switch current limit. Ensure that the peak inductor current is less than the maximum switch current limit. The inductance value can be calculated with Equation (6): L1  VOUT fSW  ΔI L  V  1  OUT VIN     (6) Where VOUT is the output voltage, VIN is the input voltage, fS is the switching frequency, and ∆IL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated with Equation (7): ILP  ILOAD   V VOUT  1  OUT 2  fSW  L1  VIN    (7) Where ILOAD is the load current. Selecting the Input Capacitor The input current to the step-down converter is discontinuous and requires a capacitor to supply AC current to the step-down converter while maintaining the DC input voltage. Use capacitors with low equivalent series resistances (ESR) for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also be sufficient. For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor (C1) can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, place a small, high-quality, ceramic capacitor (0.1μF) as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at the input. The input voltage ripple caused by capacitance can be approximated with Equation (8): www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 17 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER ΔVIN   V ILOAD V  OUT  1  OUT fSW  C1 VIN  VIN    (8) Selecting the Output Capacitor The output capacitor (C2) maintains the DC output voltage. Use ceramic, tantalum, or lowESR electrolytic capacitors. Low ESR capacitors are recommended to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (9): ΔV OUT  VOUT  VOUT  1  fSW  L  VIN  (9)   1     RESR  8  f  C2 SW    Where L is the inductor value, and RESR is the ESR value of the output capacitor. For ceramic dominates the frequency and output voltage output voltage Equation (10): ΔV OUT  capacitors, the capacitance impedance at the switching contributes the most to the ripple. For simplification, the ripple can be estimated with  V VOUT  1  OUT VIN 8  f  L  C2  2 SW   (10)  For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (11):    RESR (11)  The characteristics of the output capacitor also affect the stability of the regulation system. The MP4575 can be optimized for a wide range of capacitances and ESR values. ΔV OUT  VOUT  VOUT  1  fSW  L  VIN Compensation Components The MP4575 employs current-mode control for easy compensation and fast transient response. COMP is the output of the internal error amplifier and controls system stability and transient response. A series resistor-capacitor combination sets a pole-zero combination to control the control system’s characteristics. The DC gain of the voltage feedback loop can be calculated with Equation (12): A VDC  RLOAD  GCS  A VEA  MP4575 Rev. 1.0 8/16/2016 VFB VOUT (12) Where AVEA is the error amplifier voltage gain (1000V/V), GCS is the current-sense transconductance (12A/V), and RLOAD is the load resistor value. The system has two important poles: one from the compensation capacitor (C3) and the output resistor of error amplifier, and the other due to the output capacitor and the load resistor. These poles can be determined with Equation (13) and Equation (14): fP1  GEA 2π  C3  A VEA (13) fP2  1 2π  C2  RLOAD (14) Where GEA is the transconductance (540μA/V). error-amplifier The system has one important zero due to the compensation capacitor and the compensation resistor (R3). This zero can be determined with Equation (15): fZ1  1 2π  C3  R3 (15) The system may have another significant zero if the output capacitor has a large capacitance or a high ESR value. This zero can be determined with Equation (16): fESR  1 2π  C2  RESR In this case, a third pole set by compensation capacitor (C4) and compensation resistor can compensate for effect of the ESR zero. This pole can determined with Equation (17): fP3  1 2π  C4  R3 (16) the the the be (17) The goal of compensation design is to shape the converter transfer function for a desired loop gain. The system crossover frequency where the feedback loop has unity gain is important, since lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies lead to system instability. Generally, set the crossover frequency to ~0.1xfSW. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 18 MP4575 – 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER Use the following compensation: steps to design the 1. Choose R3 to set the desired crossover frequency. R3 can be determined with Equation (18): R3  Where fC frequency. 2π  C2  fC VOUT  GEA  GCS VFB is the desired (18) crossover 2. Choose C3 to achieve the desired phase margin. For applications with typical inductor values, set the compensation zero (fZ1) to 65%, the time period available to the bootstrap charging is less, so the bootstrap capacitor may not be charged sufficiently. This affects efficiency and normal operation. An external bootstrap diode from the 3V - 5V rail to BST can help charge the bootstrap capacitor and enhance efficiency (see Figure 2). The output voltage is a good choice for this power supply if it is in above range. The bootstrap diode can be a low-cost one such as IN4148 or BAT54. BST 3V-5V Rail 1N4148 C3  4 2π  R3  fC (19) 3. Determine if C4 is required. C4 is required if the ESR zero of the output capacitor is located at