MP5000DQ-LF-P

MP5000 12V, 5A Programmable Current Limit Switch The Future of Analog IC Technology DESCRIPTION FEATURES The MP5000 is a protection device designed to protect circuitry on the output (source) from transients on input (VCC). It also protects VCC from undesired shorts and transients coming from the source. • • • • • • At start up, inrush current is limited by limiting the slew rate at the source. The slew rate is controlled by a small capacitor at the dv/dt pin. The dv/dt pin has an internal circuit that allows the customer to float this pin (no connect) and still receive 1.1ms ramp time at the source. Integrated 44mΩ Power FET Enable/Fault Pin Adjustable Slew Rate for Output Voltage Adjustable Current Limit: 1-5A Thermal Protection Over Voltage Limit APPLICATIONS • • • The max load at the output (source) is current limited. This is accomplished by utilizing a sense FET topology. The magnitude of the current limit is controlled by an external resistor from the ILimit pin to the Source pin. Hot Swap PC Cards Laptops For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. An internal charge pump drives the gate of the power device, allowing a very low on-resistance DMOS power FET of just 44mΩ. The source is protected from the VCC input being too low or too high. Under Voltage Lockout (UVLO) assures that VCC is above the minimum operating threshold, before the power device is turned on. If VCC goes above the high output threshold, the source voltage will be limited. TYPICAL APPLICATION RLIMIT VIN 11 5 4 3 EN 2 Cdv/dt 1 VCC N/C I-Limit Source Source MP5000 Enable/Fault Source dv/dt Source GND Source 6 VOUT 7 8 9 10 U1 MP5000 Rev. 1.41 9/2/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 1 MP5000 – 12V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH ORDERING INFORMATION Part Number* Package Top Marking Free Air Temperature (TA) MP5000DQ QFN10 (3 x3mm) V6 -40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP5000DQ–Z); For RoHS Compliant Packaging, add suffix –LF (e.g. MP5000DQ–LF–Z) PACKAGE REFERENCE TOP VIEW GND 1 DV/DT 2 ENABLE/FAULT 3 I-LIMIT 4 N/C 5 ABSOLUTE MAXIMUM RATINGS (1) VCC, SOURCE, I-LIMIT .................. -0.3V to 22V dv/dt, ENABLE/FAULT..................... -0.3V to 6V Storage Temperature ............... -65°C to +155°C Continuous Power Dissipation (TA = +25°C) (2) ............................................................2.5W Operating Junction Temperature . -40°C to 150°C Input Voltage Operating Range........ 10V to 18V Input Voltage Transient (100mS) ......... VIN=25V MP5000 Rev. 1.41 9/2/2014 EXPOSED PAD VCC 10 SOURCE 9 SOURCE 8 SOURCE 7 SOURCE 6 SOURCE Thermal Resistance (3) θJA θJC QFN10 .................................... 50 ...... 12 ... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 MP5000 – 12V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH ELECTRICAL CHARACTERISTICS VCC = 12V, RLIMIT=22Ω, Capacitive Load = 100μF, TA=25°C, unless otherwise noted. Parameters Power FET Symbol Delay Time tDLY ON Resistance (4) Off State Output Voltage Continuous Current Thermal Latch Shutdown Temperature Under/Over Voltage Protection RDSon VOFF ID VCLAMP Under Voltage Lockout VUVLO Intermediate Level Input Voltage High Level Input Voltage High State Maximum Voltage Low Level Input Current (Sink) Enabling of chip to ID=100mA with a 1A resistive load TJ=25°C TJ=80°C VCC=18Vdc, VENABLE=0Vdc, RL= 500Ω 2 0.5 in pad, Minimum Copper, TA=80°C Overvoltage Protection VCC=17V Turn on, Voltage going high ILIM-SS ILIM-OL Typ Max Units 0.15 44 95 ms 82 mΩ 120 mV 4.2 2.3 A 175 °C 13.8 15 16.2 V 7.7 8.5 9.3 V 0.80 VHYST V RLIM=22Ω RLIM=22Ω, 2.4 3.7 5.0 5.0 A A Tr Float dv/dt pin, Note 5 0.64 1.1 2.1 ms VIL Output Disabled Thermal Fault, Disabled Output Enabled 0.5 V 1.95 V -50 V V μA 3 Units VCC V VI (INT) VIH VI (MAX) IIL Maximum Fanout for Fault Signal Maximum Voltage on Enable/Fault Pin Total Device Min TSD Output Clamping Voltage Under Voltage Lockout (UVLO) Hysteresis Current Limit (4) Hold Current Trip Current dv/dt Circuit Rise Time Enable/Fault Low Level Input Voltage Condition Output VENABLE=0V Total number of chips that can be connected for simultaneous shutdown VMAX Note 6 Bias Current IBIAS Device Operational Thermal Shutdown Minimum Operating Voltage for UVLO VMIN Enable