MP5007DQ-LF-Z

MP5007 5V, 1A- 5A Programmable Current Limit Switch The Future of Analog IC Technology DESCRIPTION FEATURES The MP5007 is a protection device designed to protect circuitry on the output (source) from transients on input (VCC). It also protects VCC from undesired shorts and transients coming from the source. • • • • • At start up, inrush current is limited by limiting the slew rate at the source. The slew rate is controlled by a small capacitor at the dv/dt pin. The dv/dt pin has an internal circuit that allows the customer to float this pin and still receives a 1.1ms ramp time at the source. • Integrated 37mΩ Power FET Enable/Fault Pin Adjustable Slew Rate for Output Voltage Adjustable Current Limit Thermal Protection Over Voltage Limit Available in 3x3mm QFN10 Package • APPLICATIONS • • • • The max load at the output (source) is current limited. This is accomplished by utilizing a sense FET topology. The magnitude of the current limit is controlled by an external resistor from the ILimit pin to the Source pin. Hot Swap PC Cards Cell Phones Laptops All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. An internal charge pump drives the gate of the power device, allowing a very low on-resistance DMOS power FET of just 37mΩ. The source is protected from the VCC input being too low or too high. Under Voltage Lockout (UVLO) assures that VCC is above the minimum operating threshold, before the power device is turned on. If VCC goes above the high output threshold, the source voltage will be limited. TYPICAL APPLICATION RLIMIT VCC 11 C2 C3 10V 10V 6 7 8 EN N/C I-Limit MP5007 Rev.1.1 9/2/2014 10 Source Source MP5007 Enable/Fault 9 dv/dt Cdv/dt VCC GND Source Source 5 4 3 VOUT C4 10V 2 Source 1 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 1 MP5007 – 5V, 1A- 5A PROGRAMMABLE CURRENT LIMIT SWITCH ORDERING INFORMATION Part Number* Package Top Marking Free Air Temperature (TA) MP5007DQ QFN10 (3x3) 3R -40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP5007DQ–Z); For RoHS Compliant Packaging, add suffix –LF (e.g. MP5007DQ–LF–Z) PACKAGE REFERENCE 1 10 2 9 3 8 4 7 5 6 ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance VCC, SOURCE, I-LIMIT................. -0.3V to 22V dv/dt, ENABLE/FAULT..................... -0.3V to 6V Continuous Power Dissipation (TA = +25°C)(2) ……………………………………………….2.5W Storage Temperature ............... -65°C to +155°C QFN10 .................................... 50 ...... 12 ... °C/W Recommended Operating Conditions VCC Operating Range ........................ 4V to 6V Operating Junct. Temp. (TJ)……-40°C to +125°C MP5007 Rev.1.1 9/2/2014 (3) θJA θJC Notes: 1) Exceeding these ratings may damage the device 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage... 3) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 MP5007 – 5V, 1A- 5A PROGRAMMABLE CURRENT LIMIT SWITCH ELECTRICAL CHARACTERISTICS VCC = 5V, RLIMIT=22Ω, COUT= 10μF, TJ=25°C, unless otherwise noted. Parameters Power FET Symbol Delay Time tDLY ON Resistance RDSon Off State Output Voltage Continuous Current Thermal Latch Shutdown Temperature Under/Over Voltage Protection VOFF ID TSD Output Clamping Voltage VCLAMP Under Voltage Lockout VUVLO Under Voltage Lockout (UVLO) Hysteresis Current Limit Condition Min Enabling of chip to ID=100mA with a 12Ω resistive load TJ=25°C TJ=80°C, Note 4 VCC=18V, Enable=0V, RL=500Ω 2 0.5 in pad, TJ=25°C minimum copper, TJ=80°C 37 45 43 ILIM-SS Trip Current dv/dt Circuit Rise Time Enable/Fault Low Level Input Voltage ILIM-OL RLIMIT=22Ω, 0Ω short resistance, Note 4 RLIMIT=22Ω, Note 4 Tr Float dv/dt pin, Note 5 VIL Intermediate Level Input Voltage VI (INT) High Level Input Voltage High State Maximum Voltage Low Level Input Current (Sink) VIH VI (MAX) IIL Output Disabled, Thermal Fault, Output Disabled Output Enabled VENABLE=0V Total number of chips that can be connected for simultaneous shutdown Note 6 Maximum Voltage on Enable Pin Total Device VMAX Bias Current IBIAS Device Operational Thermal Shutdown Minimum Operating Voltage for UVLO VMIN Enable