MP5010SDQ-LF-Z

MP5010S EC R NE O EF W M ER D M E TO ES ND I E G M D N P5 S F O 01 R 3A 5V, 1A- 5A Programmable Current Limit Switch DESCRIPTION The MP5010S is a protection device designed to protect circuitry on the output (source) from transients on input (VCC). It also protects VCC from undesired shorts and transients coming from the source. At start up, inrush current is limited by limiting the slew rate at the source. The slew rate is controlled by a small capacitor at the dv/dt pin. The dv/dt pin has an internal circuit that allows the customer to float this pin (no connect) and still receive 1.1ms ramp time at the source.       Wide 3.6V-to-18V Operating Input Range Integrated 40mΩ Power FET Enable/Fault Pin Adjustable Slew Rate for Output Voltage Adjustable Current Limit Thermal Protection APPLICATIONS     Hot Swap Wireless Modem Data Cards PC Cards Laptops All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. R The maximum load at the output (source) is current limited. This is accomplished by utilizing a sense FET topology. The magnitude of the current limit is controlled by an external resistor from the I-Limit pin to the Source pin. An internal charge pump drives the gate of the power device, allowing a very low on-resistance DMOS power FET of just 40mΩ. The source is protected from the VCC input being too low or too high. Under Voltage Lockout (UVLO) assures that VCC is above the minimum operating threshold, before the power device is turned on. If VCC goes above the high output threshold, the source voltage will be limited. FEATURES N O T TYPICAL APPLICATION MP5010S Rev. 1.0 www.MonolithicPower.com 8/4/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 1 MP5010S – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH ORDERING INFORMATION Package QFN10 (3mmx3mm) Top Marking AGK EC R NE O EF W M ER D M E TO ES ND I E G M D N P5 S F O 01 R 3A Part Number* MP5010SDQ * For Tape & Reel, add suffix –Z (e.g. MP5010SDQ–Z). For RoHS compliant packaging, add suffix –LF (e.g. MP5010SDQ-LF-Z). PACKAGE REFERENCE ABSOLUTE MAXIMUM RATINGS (1) VCC, SOURCE, I-LIMIT ................. –0.3V to 22V dv/dt, ENABLE/FAULT.................... –0.3V to 6V Storage Temperature .............. –65°C to +155C Junction Temperature ............................... +150C Lead Temperature .................................... +260C (2) Continuous Power Dissipation (TA=+25oC) …………………………………………………2.5W R Recommended Operating Conditions T Input Voltage Operating Range......... 4V to 18V Continuous Current 0.5 in2 pad, TA=25C ...................................4.2A For Minimum Copper, TA=80C ..................... 2.3A Operating Junction Temp. (TJ)...... -40C to +125C O N (3) Thermal Resistance (4) θJA θJC QFN10 (3mmx3mm) ............... 50 ...... 12 ... C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX) ， the junction-toambient thermal resistance JA，and the ambient temperature TA, the maximum allowable power dissipation at any ambient temperature is calculated using: PD(MAX)=(TJ(MAX)-TA)/ JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Reduce 0.2 Watts for every 10oC ambient temperature increasing 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7 4-layer board. MP5010S Rev. 1.0 www.MonolithicPower.com 8/4/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2 MP5010S – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH ELECTRICAL CHARACTERISTICS EC R NE O EF W M ER D M E TO ES ND I E G M D N P5 S F O 01 R 3A VCC = 5V, RLIMIT=22Ω, Capacitive Load= 10μF, TA=25C, unless otherwise noted. Parameters Power FET Delay Time Symbol (5) tDLY ON Resistance RDSon Off State Output Voltage VOFF Thermal Latch (6) Shutdown Temperature Under/Over Voltage Protection TSD VCLAMP Under Voltage Lockout Under Voltage Lockout (UVLO) Hysteresis (7) Current Limit VUVLO Hold Current ILIM-SS Trip Current dv/dt Circuit (8) Rise Time Enable/Fault Low Level Input Voltage ILIM-OL Intermediate Level Input Voltage VI (INT) High Level Input Voltage High State Maximum Voltage Pull Up Current (Source) VIH VI (MAX) IIL R Output Clamping Voltage Enabling of chip to ID=40mA with a 5Ω resistive load TJ=25°C (6) TJ=85°C VCC=18V, VEN=0V, RL=500Ω Overvoltage Protection VCC=8V Rising Edge Max 0.2 0Ω Short Resistance, RLIM=22Ω RLIM=22Ω Float dv/dt pin VIL Output Disabled Thermal Fault, Output Disabled Output Enabled VENABLE=0V Total number of chips that can be connected for simultaneous shutdown 40 52 55 120 Device Operational Thermal Shutdown Minimum Operating Voltage for UVLO VMIN Enable