MP5014AGJ-Z

MP5014A The Future of Analog IC Technology 12 V, 5 A, Programmable Current-Limit Switch with Over-Volatge Clamp and Slew-Rate Control in TSOT23-8 DESCRIPTION FEATURES The MP5014A is a protection device designed to protect circuitry on the output (source) from transients on the input (VCC). Also, it protects VCC from undesired shorts and transients coming from the source. • • • • • • • • • • • At start-up, the inrush current is limited by restricting the slew rate at the source. The slew rate is controlled by a small capacitor at DV/DT. DV/DT has an internal circuit that allows this pin to float (no connection) and still receive 1 ms ramp time at the source. The maximum load at the output is current limited. This is accomplished by utilizing a sense FET topology. The magnitude of the current limit is controlled by an external resistor from I-LIMIT to SOURCE. An internal charge pump drives the gate of the power device, allowing a very low on-resistance DMOS power FET of just 36 mΩ. The source is protected from the VCC input going too low or too high. Under-voltage lockout (UVLO) assures that VCC is above the minimum operating threshold before the power device is turned on. If VCC rises above the high output threshold, the source voltage is limited. 10 V to 13.8 V Operating Input Range 15 V Typical Output Over-Voltage Clamp Absolute Maximum Voltage of 22 V Input Under-Voltage Lockout Low Inrush Current during Start-Up Integrated 36 mΩ Power FET Enable/Fault Pin Adjustable Slew Rate for Output Voltage Adjustable Current Limit Thermal Protection TSOT23-8 Package APPLICATIONS • • • • Storage (HDDs, SSDs) Hot-Swap Systems Set-Top Boxes Gaming All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 1 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH ORDERING INFORMATION Part Number* Package Top Marking MP5014AGJ TSOT23-8 See Below * For Tape & Reel, add suffix –Z (e.g. MP5014AGJ–Z) TOP MARKING AMJ: Product code of MP5014AGJ Y: Year code PACKAGE REFERENCE ABSOLUTE MAXIMUM RATINGS (1) VCC, SOURCE, I-LIMIT................-0.3 V to 22 V DV/DT, ENABLE/FAULT.................-0.3 V to 6 V Storage temperature ................ -65°C to +155°C (2) Continuous power dissipation (TA = +25°C) .......................................................... 1.25 W Junction temperature ................................ 150°C Input voltage transient (100 ms) ........VIN = 25 V Recommended Operating Conditions (3) Input voltage operating range…….10 V to 13.8 V Continuous current 0.5 in2 pad ................. 4.2 A For minimum copper, TA= 80°C ................. 2.3 A Operating junction temp. (TJ). .. -40°C to +125°C Thermal Resistance (4) θJA θJC TSOT23-8 ..............................100 ..... 55 ... °C/W NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will produce an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 2 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH ELECTRICAL CHARACTERISTICS VCC = 12 V, RLIMIT = 22 Ω, capacitive load = 10 μF, TJ=25°C, unless otherwise noted. Parameters Power FET Symbol Delay time tDLY On resistance RDSon Off-state output voltage VOFF Thermal latch Shutdown temperature(5) Under/over voltage protection TSD Output clamping voltage VCLAMP Under-voltage lockout VUVLO Under-voltage lockout hysteresis Current limit(5) Hold current Trip current DV/DT circuit (UVLO) Rise time ENABLE/FAULT Low-level input voltage Intermediate level input voltage High-level input voltage High-state maximum voltage Low-level input current (source) Min Enabling of chip to ID = 100 mA with a 1 A resistive load, float DV/DT TJ = 25°C TJ = 85°C (5) VCC = 18 Vdc, VENABLE = 0 Vdc, RL= 500 Ω ILIM-SS ILIM-OL Tr VIL VI (INT) VIH VI (MAX) IIL Typ Max Units 0.4 ms 36 48 mΩ 120 mV 175 Over-voltage protection, VCC = 17 V Turn on, voltage goes high °C 13.8 15 16.2 V 7.7 8.5 9.3 V VHYST Maximum fanout for fault signal Maximum voltage on ENABLE/FAULT(6) Total device Condition 0.80 RLIM = 22 Ω RLIM = 22 Ω 2.8 Float DV/DT, output rises from 10% to 90% Output disabled Thermal fault, output disabled Output enabled VENABLE = 0 V Total number of chips that can be connected for simultaneous shutdown 3.8 5.6 Bias current IBIAS Minimum operating voltage for UVLO VMIN Enable < 0.5 V 4.9 A A 1 0.82 2.5 15 ms 1.4 0.5 1.95 5 25 35 V V V V μA 3 Units VCC V 1200 400 500 μA 5 V VMAX Device operational Enable shutdown Thermal shutdown V 1000 300 400 NOTES: 5) Guaranteed by characterization test. 6) Maximum input voltage on ENABLE/FAULT is ≤ 6 V if VCC ≥ 6 V. Maximum input voltage on ENABLE/FAULT is VCC if VCC ≤ 6 V. MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 3 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12 V, VEN = 5 V, RLIMIT = 22 Ω, COUT = 10 μF, CDV/DT = float, TA = 25°C, unless otherwise noted. 9 330 1.16 8 7 320 1.12 6 310 5 1.08 4 300 3 1.04 2 290 1 0 0 20 40 60 80 100 120 36 1 10 11 12 13 14 15 120 280 10 11 12 13 14 15 4 100 35 3.9 80 34 60 3.8 40 33 3.7 20 32 10 11 12 13 14 15 0 0 0.5 1 1.5 2 2.5 3 3.6 9 10 11 12 13 14 15 60 6 5.8 50 5.6 40 5.4 30 5.2 5 9 10 11 12 13 14 15 20 0 5 10 15 20 25 30 35 40 MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 4 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12 V, VEN = 5 V, RLIMIT = 22 Ω, COUT = 10 μF, CDV/DT = float, TA = 25°C, unless otherwise noted. MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 5 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12 V, VEN = 5 V, RLIMIT = 22 Ω, COUT = 10 μF, CDV/DT = Float, TA = 25°C, unless otherwise noted. MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 6 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH PIN FUNCTIONS Pin # 1 2 3 4 5,6 7,8 Name Description Current limit set. A resistor between I-LIMIT and SOURCE sets the overload and short-circuit current limit levels. Tri-state, bi-directional interface. ENABLE/FAULT is floated to enable the output of the device. ENABLE/FAULT disables the chip by pulling it to ground (using an open ENABLE/FAULT drain or open collector device). If a thermal fault occurs, the voltage on ENABLE/FAULT enters an intermediate state, which signals a monitoring circuit that the device is in thermal shutdown. Slew rate of the output voltage at turn on control. DV/DT has an internal capacitor that allows it to ramp up over 1 ms. An external capacitor can be added to DV/DT to DV/DT increase the ramp time. If an additional time delay is not required, DV/DT should be left open. GND Negative input voltage to the device. This is used as the internal reference for the IC. SOURCE Source of the internal power FET and the output terminal of the IC. VCC Input. Positive input voltage. I-LIMIT MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 7 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH FUNCTIONAL BLOCK DIAGRAM Figure 1—Functional block diagram MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 8 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH OPERATION The MP5014A limits the inrush current to the load when a circuit card connects to a live backplane power source, thereby limiting the backplane’s voltage drop and the dv/dt of the voltage to the load. It offers an integrated solution to monitor the input voltage, output voltage, output current, and die temperature, eliminating the external current-sense power resistor, power MOSFET, and thermal sensor. (if uncontrolled), the temperature will rise above the MP5014A thermal protection (+175°C) and shut down the device to cause the temperature to drop. Proper heat sink must be used if the device is intended to supply the hold current and not shut down. Without a heat sink, the hold current should be maintained below 125 mA at +25°C and below 75 mA at +85°C to prevent the device from activating a thermal shutdown. Under-Voltage Lockout Operation (UVLO) If the supply (input) is below the UVLO threshold, the output is disabled, and the ENABLE/FAULT line is driven low. Thermal protection When thermal protection is triggered, the output is disabled, and the ENABLE/FAULT line is driven to the middle level. The thermal fault condition is latched, and the part will remain in a latched off state until the power is re-started, or ENABLE/FAULT is re-set. When the supply rises above the UVLO threshold, the output is enabled and the fault line is released. When the fault line is released, the supply is pulled high by a 25 μA current source. No external pull-up resistor is required. In addition, the pull-up voltage is limited to 5 V. Output Over-Voltage Protection (OVP) If the input voltage is higher than the OVP threshold, the output is clamped at 15 V, typically. Current Limit When the part is active, if the load reaches the trip current (the minimum threshold current triggers over-current protection) or a short is present, the part switches into constant-current (hold current) mode. The part is shutdown only if the over-current condition remains long enough to trigger thermal protection. However, when the part is powered up by VCC or EN, the load current should be less than the hold current. Otherwise, the part cannot be turned on fully. In a typical application using a current limit resistor of 22 Ω, the trip current is 5.6 A, and the hold current is 3.8 A. If the device is in its normal operating state and passing 2 A, it will need to dissipate only 144 mW with the very low on resistance of 36 mΩ. For the package dissipation of 100°C/W, the temperature rise is only +14°C. Combined with a 25°C ambient temperature, this is only a 39°C total package temperature. ENABLE/FAULT ENABLE/FAULT is a bi-directional, three level I/O with a weak pull-up current (25 μA typically). The three levels are low, mid, and high. ENABLE/FAULT functions to enable/disable the part and to relay fault information. ENABLE/FAULT as an input: 1. Low and mid disable the part. 2. Low, in addition to disabling the part, clears the fault flag. 3. High enables the part (if the fault flag is clear). ENABLE/FAULT as an output: 1. The pull-up current may (if not over ridden) allow a “wired nor” pull up to enable the part. 2. An under voltage causes a low on ENABLE/FAULT and clears the fault flag. 3. A thermal fault causes a mid level on ENABLE/FAULT and sets the fault flag. During a short-circuit condition, the device has 12 V across it. The hold current clamps at 3.8 A and therefore must dissipate 45.6 W. At 100°C/W MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 9 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH The ENABLE/FAULT line must be high level for the output to turn on. During a thermal shutdown, ENABLE/FAULT is driven to the mid level. The fault flag is an internal flip-flop that can be set or re-set under the conditions below: There are four types of faults, and each fault has a direct and indirect effect on ENABLE/FAULT and the internal fault flag (see Table 1). 1. Thermal Shutdown: sets fault flag. 2. Under Voltage: re-sets fault flag. 3. Low Voltage on ENABLE/FAULT: re-sets fault flag. 4. Mid Voltage on ENABLE/FAULT: no effect. In a typical application there are one or more of the MP5014A chips in a system. The ENABLE/FAULT lines will be connected to each other typically. Table 1—Fault function influence in application Fault Description Internal Action Effect on Fault Pin Short/over current Limits current None Under voltage Output is turned off Internally drives ENABLE/FAULT to logic low Over voltage Limits output voltage None Thermal shutdown Shuts down the part. The part is latched off until UVLO or driven to ground externally Internally drives ENABLE/FAULT to mid level Effect on Flag None Flag is re-set None Flag is set Effect on Secondary Part None Secondary part output is disabled, and the fault flag is re-set None Secondary part output is disabled MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 10 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH APPLICATION INFORMATION Current Limit The desired current limit is a function of the external current limit resistor (see Table 2). Table 2—Current limit vs. current limit resistor (VCC = 12 V) RLIMIT (Ω) Trip current (A) Hold current (A) 15.4 22 24.9 30 49.9 100 7.95 5.62 5.23 4.57 3.43 2.64 5.61 3.81 3.35 2.78 1.69 0.88 PCB LAYOUT GUIDELINES Efficient PCB layout is critical to achieve stable operation. Please refer to Figure 3 and follow the guidelines below: 1. Place RLIMIT close to I-LIMIT. 2. Place CDV/DT close to DV/DT and the input capacitor close to VCC. 3. Ensure there is a large enough copper area near VCC and source to achieve better thermal performance. Rise Time The rise time is a function of the capacitor (CDV/DT) on DV/DT (see Table 3). Table 3—Rise time vs. CDV/DT CDV/DT Rise time (typically, ms) none 33 pF 470 pF 1 nF 1 1.45 9.6 20.3 * NOTE: Rise Time = KRT*(50 Pf + Cdv/dt), KRT = 18.1E6 The rise time is measured from 10 percent to 90 percent of the output voltage (see Figure 2). Top Layer Figure 2—Rise time Bottom Layer Figure 3―Recommended PCB layout MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 11 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH Design Example Table 4 is a design example following the application guidelines for the given specifications: Table 4—Design example VIN Trip current Hold current 12 V 5.6 A 3.8 A Figure 4 shows the application schematic. The Typical Performance Characteristics section shows the circuit waveforms. For additional device applications, please refer to the related evaluation board datasheet. MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 12 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH TYPICAL APPLICATION CIRCUITS 7 C1 10 µF 5 C3 10 µF C2 NS 6 8 2 R1 22 Ω 3 1 C4 NS 4 Figure 4―Typical application schematic MP5014A Rev. 1.0 www.MonolithicPower.com 6/23/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 13 MP5014A – 12 V, 1A-5 A, PROGRAMMABLE CURRENT-LIMIT SWITCH PACKAGE INFORMATION TSOT23-8 See note 7 EXAMPLE TOP MARK PIN 1 ID IAAAA RECOMMENDED LAND PATTERN TOP VIEW SEATING PLANE SEE DETAIL ''A'' FRONT VIEW SIDE VIEW NOTE: DETAIL ''A'' 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-193, VARIATION BA. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP5014A Rev 1.0 6/23/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 14