MP5034
USB Charging Port Controller
Integrating QC 3.0 Protocol
DESCRIPTION
FEATURES
The MP5034 supports DCP schemes for
battery charging specification (BC1.2), divider
mode, 1.2V/1.2V mode, and quick-charge
specification (QC 3.0) without the need for
outside user interaction.
Full protection features include input overvoltage protection (OVP) and thermal
shutdown.
The MP5034 requires a minimal number of
readily
available,
standard,
external
components to complete the USB switch and
charging mode auto-detection solution. The
MP5034 is available in an 8-pin TSOT23
package.
Wide 3.6V to 14V Operating Input Voltage
Range
Supports QC 3.0 (3.6V - 12Vbus with 1%
Accuracy) and DCP Schemes for BC1.2,
Divider Mode, and 1.2V/1.2V Mode
Input Discharge during High Voltage to Low
Voltage Change
Compatible with Buck, Boost, and AC/DC
Converters
Available in a TSOT23-8 Package
APPLICATIONS
USB Charger Controller
AC/DC Wall Adapter with USB Ports
Power Bank Controller
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
Note: Set MP2499M original output to 3.5V by R1 and R2.
VIN
12V-36V
C2
22μF
BST
IN
MP2499M
SW
C4
0.1μF
L1
15μH
FB
VCC
AGND
PGND
MP5034 Rev 1.0
10/20/2017
QC3.0
IN
ISENSE
R3
33kΩ
R2
24.3kΩ
3.6V-12V
MP5034
R1
82.5kΩ
EN/SYNC
C3
0.1μF
C1
66μF
DM
DP
ADJ
Type-A
EN
GND
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1
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
ORDERING INFORMATION
Part Number*
MP5034GJ
Package
TSOT23-8
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g.MP5034GJ-Z)
TOP MARKING
AYQ: Product code of MP5034GJ
Y: Year code
PACKAGE REFERENCE
TOP VIEW
EN
DP
IN
DM
IN
NC
GND
ADJ
TSOT23-8
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply voltage (VIN) ..................... -0.3V to +16V
All other pins .................................. -0.3V to +6V
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Continuous power dissipation (TA = +25°C) (2)(5)
................................................................ 1.89W
TSOT23-8
θJA
θJC
(5)
EV5034-J-00A .................. 66 ....... 23 ... °C/W
JESD51-7 (6) ........................ 100 ...... 55 ... °C/W
Recommended Operating Conditions (3)
Supply voltage (VIN) .................... 3.6V to 14V (4)
Operating junction temp. (TJ). .. -40°C to +125°C
MP5034 Rev 1.0
10/20/2017
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of
the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient
temperature TA. The maximum allowable continuous power
dissipation at any ambient temperature is calculated by P D
(MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum
allowable power dissipation produces an excessive die
temperature, causing the regulator to go into thermal
shutdown. Internal thermal shutdown circuitry protects the
device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) For lower VIN applications, refer to the Operation section.
5) Measured on EV5034-J-00A, 2-layer PCB, 58mmx32mm,
2Oz copper.
6) Measured on JESD51-7, 4-layer PCB.
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2
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = -40°C to 125°C (7), typical value is tested at TJ = +25°C, unless otherwise noted.
Parameter
VIN under-voltage lockout
rising threshold
UVLO hysteresis
EN rising threshold
EN hysteresis
EN auto pull-up current
Symbol
Condition
Min
Typ
Max
Units
VIN_UVLO
ADJ starts to work
2.7
3.0
3.3
V
16
mV
V
mV
μA
280
250
320
μA
μA
5.05
5
8.82
5.10
5.10
9
5.15
5.2
9.18
V
V
V
11.76
500
12
12.24
V
μA
VIN rising edge, VIN = 5V
VIN rising edge, VIN = 9V
VIN rising edge, VIN = 12V
110
110
110
115
115
115
120
120
120
VIN OVP recovery threshold
Shutdown temperature (8)
Hysteresis (8)
BC 1.2 DCP Mode
VOV_Recovery Reset mode to 5V default
TSTD
THYS
5.35
5.5
160
35
5.65
V
°C
°C
DP/DM short resistance
1.2V/1.2V Mode
RDP/DM_Short VDP = 0.8V, IDM = 1mA
50
Ω
Shutdown current
Supply current
Voltage Control
Default VIN voltage
9VIN voltage
12VIN voltage
VADJ sink current capability
Protection
VIN OVP threshold
VUVLOHYS
VEN_R
VEN_HYS
IEN_UP
IQ_STD
IQ
VIN_Def1
VIN_Def2
VIN_9
1.17
7
EN = 0, VIN = 5V
VIN = 5V, no load
IOUT = 0A, TJ = 25°C
IOUT = 0A, TJ = -40°C to 125°C
VIN_12
VADJ = 0.8V
VOV_TH
880
1.21
200
11.5
1.25
%
DP/DM output voltage
VDP/DM_1.2V
1.1
1.2
1.3
V
DP/DM output impedance
Divider Mode
RDP/DM_1.2V
200
300
400
kΩ
DP/DM output voltage
DP/DM output impendence
Quick Charge 3.0 Mode
VDP/DM
RDP/DM
2.5
18
2.7
22
2.85
28
V
kΩ
VIN = 5V
DP/DM low voltage
VQC_LOW
0.25
0.3
0.4
V
DP/DM high voltage
DP output impendence
DM output impendence
DM low glitch time (8)
DP high glitch time
VQC_High
RDP_QC
RDM_QC
TGlitch_DM
TGlitch_DP
1.8
250
15
2
400
20
10
2.2
450
25
V
kΩ
kΩ
ms
ms
MP5034 Rev 1.0
10/20/2017
1000
1500
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3
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
ELECTRICAL CHARACTERISTICS (continued)
VIN = 5V, TJ = -40°C to 125°C (7), typical value is tested at TJ = +25°C, unless otherwise noted.
Parameter
Symbol
Bus voltage change glitch time
Bus voltage step
Time for VBUS to discharge to
5V when DP < 0.6V (8)
Condition
TGlitch_V_Change
VBUS_CONT_STEP
Min
Typ
Max
Units
20
150
40
200
60
250
ms
mV
500
ms
TV_UNPLUG
NOTES:
7) Guaranteed by over-temperature correlation, not tested in production.
8) Guaranteed by engineering sample characterization.
MP5034 Rev 1.0
10/20/2017
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4
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
TYPICAL CHARACTERISTICS
VIN_MP5034 = 5V, TA = 25°C, unless otherwise noted.
Quiescent Current vs. Input Voltage
EN floating
QUIESCENT CURRENT (µA)
400
350
300
250
200
150
100
3
MP5034 Rev 1.0
10/20/2017
4
5
6
7
8
9
INPUT VOLTAGE (V)
10
11
12
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5
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
TYPICAL CHARACTERISTICS (continued)
VIN_MP5034 = 5V, TA = 25°C, unless otherwise noted.
MODE Transition from 5V to 9V
MODE Transition from 5V to 9V
IOUT = 0A, from QC 2.0_5V to 9V
Zoom in 5V to 9V slew rate
CH1: VIN
5V/div.
CH1: VIN
5V/div.
CH2: D+
2V/div.
CH2: D+
2V/div.
CH3: D2V/div.
CH4: IOUT
500mA/div.
CH3: D2V/div.
CH4: IOUT
500mA/div.
10ms/div.
500µs/div.
MODE Transition from 9V to 12V
MODE Transition from 9V to 12V
IOUT = 0A, from QC 2.0_9V to 12V
Zoom in 9V to 12V slew rate
CH1: VIN
5V/div.
CH2: D+
2V/div.
CH1: VIN
5V/div.
CH2: D+
2V/div.
CH3: D2V/div.
CH4: IOUT
500mA/div.
CH3: D2V/div.
CH4: IOUT
500mA/div.
10ms/div.
500µs/div.
MODE Transition from 12V to 9V
MODE Transition from 9V to 5V
IOUT = 0A, from QC 2.0_12V to 9V
IOUT = 0A, from QC 2.0_9V to 5V
CH1: VIN
5V/div.
CH1: VIN
5V/div.
CH2: D+
2V/div.
CH2: D+
2V/div.
CH3: D2V/div.
CH4: IOUT
500mA/div.
CH3: D2V/div.
CH4: IOUT
500mA/div.
10ms/div.
MP5034 Rev 1.0
10/20/2017
10ms/div.
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6
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
TYPICAL CHARACTERISTICS (continued)
VIN_MP5034 = 5V, TA = 25°C, unless otherwise noted.
QC 3.0 Device Charging Test
CH1: VIN
5V/div.
CH2: D+
2V/div.
CH3: D2V/div.
CH4: ICHARGE
1A/div.
2s/div.
MP5034 Rev 1.0
10/20/2017
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7
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
PIN FUNCTIONS
Package
Pin #
Name
1
EN
2, 3
IN
4
GND
5
ADJ
6
NC
7
DM
8
DP
MP5034 Rev 1.0
10/20/2017
Description
Enable control. EN has an internal auto pull-up current to 5V. Float EN or apply a logic
high voltage to EN to enable the IC. Pull EN to logic low to disable the IC.
Supply voltage. The two input voltage pins must be connected together on the PCB.
Ground.
Input voltage adjustment. ADJ sinks a current from the upstream DC/DC converter's
FB pin to ground to regulate the DC/DC converter's output voltage.
No connection. Connect NC to ground during application in the PCB layout. Do not
connect NC to any other >500mV pin.
D- data line to USB connector. DM is the input/output used for handshaking with
portable devices.
D+ data line to USB connector. DP is the input/output used for handshaking with
portable devices.
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8
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
BLOCK DIAGRAM
NC
IN
Vin
sense
5V
Vcc Regulator
R1
EN control
Thermal
Protection
VFB
Vo Reference and
Slew Rate
R2
DP
VREF
Auto Charging Mode
Detection
IN
IN
ADJ
EN
Over-Voltage
Protection
DM
Compensation
Discharge
GND
Figure 1: Functional Block Diagram
MP5034 Rev 1.0
10/20/2017
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9
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
OPERATION
Table 1: QC Mode Definition
The MP5034 supports the latest quick-charge
specification (QC 3.0) and is back-compatible
with QC 2.0, DCP schemes for battery charging
specification (BC1.2), divider mode, and
1.2V/1.2V mode without the need for outside
user interaction.
Fault condition protection includes input overvoltage protection (OVP) and thermal
shutdown.
Operation Supply Voltage
The MP5034’s input voltage threshold is around
3V. When VIN is higher than the threshold,
MP5034's ADJ block begins working, which
sinks a current to adjust the upstream
regulator's output to an accurate 5.1V.
QC Mode Voltage Transition - Class A
If the downstream device of the MP5034
supports QC specification, the device can
require a higher USB bus voltage than 5V by
DM and DP communication. If a higher bus
voltage is required, ADJ must be used. ADJ is
connected to the feedback pin (FB) of an
upstream voltage converter, typically. After the
handshake, the MP5034 sinks a controlled
current gradually via ADJ to adjust the VBUS
value to 9V, 12V, or another voltage (200mV
step-by-step). Because of smart controller
mode, only one ADJ pin can set a different high
voltage, which meets the QC specification. The
bus voltage transition is smooth and has no
undershoot/overshoot (see Figure 2 and Table
1).
Tglitch_V_Change
DP=0.6V
DM=GND
Tglitch_V_Change
DP=0.6V
DM=0.6V
Portable Device
DM
0.6V
0.6V
12V
3.3V
0.6V
9V
0.6V
3.3V
3.6V - 12V, 200mV step
according to QC3.0
3.3V
3.3V
No action
0.6V
GND
5V
When the downstream device is removed, the
bus voltage returns to the default 5V
automatically. The input-to-ground discharge
resistor helps quicken this procedure.
Input Voltage Adjust
In no-load condition, if the input voltage is lower
than 5.1V (typical), ADJ sinks a current to
regulate the upstream regulator's output voltage
to 5.1V. If the input voltage is higher than 5.1V,
the MP5034 stops regulating the input voltage.
Figure 3 shows the typical ADJ usage. The ADJ
sink current capability is 500µA. The feedback
current through R1 must be less than 500µA.
Calculate R1 with Equation (1):
R1k
VOUT(V) VFB (V)
0.5
(1)
Where VOUT is the maximum output voltage that
can be adjusted to.
IN
OUT
Converter
DP=3.3V
DM=0.6V
USB Bus Voltage
DP
C1
MP5034
R1
ADJ
FB
R2
12V
9V
5V
Figure 3: ADJ Configure
TV_New_Request
Figure 2: QC Mode Transition
MP5034 Rev 1.0
10/20/2017
Input Over-Voltage Protection (OVP) and
Discharge
To protect the downstream device over-voltage,
the MP5034 provides an input OVP discharge
function. Because the MP5034 supports the QC
3.0 protocol, it has a dynamic OVP threshold.
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10
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
An accurate and fast comparator monitors the
over-voltage condition of the input. If the input
voltage rises above the threshold, the input-toground discharge path is active. When the input
voltage falls below 5.5V (typical), the MP5034
exits OVP mode.
Auto Detection
The MP5034 integrates a USB-dedicated
charging port auto-detect function, which
recognizes most mainstream portable devices.
The MP5034 supports the following charging
schemes:
The input-to-ground discharge resistance is
always active during the high-to-low voltage
mode change period. The discharge path is
turned off when FB becomes less than 108% *
VREF with 20ms of additional delay (see Figure
4).
V
VIN
Discharge
Enable
USB battery charging specification BC1.2/
Chinese
Telecommunications
Industry
Standard YD/T 1591-2009
Divider mode
1.2V/1.2V mode
Qualcomm quick-charge mode 3.0 and 2.0
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die temperature exceeds
160°C, the entire chip shuts down. When the
temperature falls below its lower threshold
(typically 125°C), the chip is enabled again.
VFB=108%*Vref
20ms
t
Figure 4: Input Discharge during the High
Voltage to Low Voltage Transition
MP5034 Rev 1.0
10/20/2017
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MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
Selecting VADJ Resistor
ADJ has an internal, controlled, current sink. A
QC mode transition can be achieved through
ADJ. The ADJ sink current capability is 500μA.
For the pre-side converter, it is recommended
to use a kΩ-level feedback resistor. Limit the
current through the high-side feedback resistor
below 500μA (see Figure 5).
There is another VADJ configuration value to limit
the maximum output voltage and insert a
resistor (R3) between FB and ADJ. With R3,
the maximum output voltage can be limited with
Equation (3):
VOUT_MAXV
R1 R2 //R 3
VFB V
R2 //R 3
(3)
The required feedback resistor value of R1
must be greater than 30kΩ.
IN
OUT
Converter
C1
MP5034
R1
R3
ADJ
FB
R2
1. Use short, direct, and wide traces to
connect the IC’s IN pin.
2. Keep the ADJ trace to the upstream
converter FB pin as short as possible and
routed far from the switching node to
prevent noise injection.
IN
EN
IN
IN
C1
GND
GND
GND
DP
DP
DM
DM
NC
VBUS
Type-A
Selecting Input Capacitor
Use low ESR capacitors for the best
performance. Ceramic capacitors with X5R or
X7R dielectrics are highly recommended
because of their low ESR and small
temperature coefficients. A 22μF ceramic
capacitor is recommended for most applications.
When selecting the input capacitor, also
consider the pre-stage converter stability. The
input capacitor of the MP5034 is the output
capacitor of the converter. Ensure that the
converter is stable with additional output
capacitors.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation and thermal dissipation. For best
results, refer to Figure 6 and follow the
guidelines below.
MP5034
APPLICATION INFORMATION
ADJ
GND
Top Layer
DCDC
FB
R3
Bottom Layer
Figure 6: Recommended Layout
Design Example
Table 2 is a design example following the
application
guidelines
for
the
given
specifications.
Table 3: Design Example
VIN (V)
Current (A)
3.6 - 12
3
The detailed application schematic is shown in
Figure 7 through Figure 9. The typical
performance and circuit waveforms are shown
in the Typical Performance Characteristics
section. For more detailed device applications,
please refer to the related evaluation board
datasheet.
Figure 5: VADJ Set Maximum VOUT
MP5034 Rev 1.0
10/20/2017
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12
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
TYPICAL APPLICATION CIRCUITS
VIN
12V-36V
1,2
C2
22μF
10
BST
IN
MP2499M
5
C3
0.1μF
7
C4
0.1μF L1
15μH
9
SW
6
FB
8 AGND
4
ISENSE
C1
66μF
R4 R2
33kΩ 24.3kΩ
QC3.0
IN
2 IN
R1
82.5kΩ
EN/SYNC
VCC
3
5
R3
6.49kΩ
MP5034
ADJ
PGND
11,12,13
3.6V-12V
DM 7
DP
NC
EN
GND
6
Type-A
8
1
4
Figure 7: MP5034 + MP2499M for CLA Car Charger
12
J1
11
10
R6
130kΩ
R7
20kΩ
13
VIN
R8
30kΩ
3
2
1
1-2: FCCM
2-3: PSM
Float 2: USM
0.1µF
BST
1
1.5µH
2
C4
4.7µF
3
OUT
MP3431
EN
FB
3
8
C1A
0.1µF
C6
COMP
VDD
SS
C8
22nF
ILIM
R1
49.9kΩ
C1
2
IN
IN
44µF
5
MODE
PGND
C3C
22µF
SW
C3B
22µF
AGND
C3A
22µF
6
VIN
C5
L1
7
3-4.2V
R2
14.3kΩ
4
9
R4
8.2nF
1kΩ
C7
10nF
R5
34kΩ
R9
3kΩ
R3
5.49kΩ
QC3.0
4.5V-12V
MP5034
DM
7
Type-A
5
ADJ
DP
NC
6
GND
EN
8
1
4
Figure 8: MP5034 + MP3431 for Power Bank
MP5034 Rev 1.0
10/20/2017
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13
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
TYPICAL APPLICATION CIRCUITS (continued)
Figure 9: MP5034 + MP2669 for Power Bank
MP5034 Rev 1.0
10/20/2017
www.MonolithicPower.com
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14
MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL
PACKAGE INFORMATION
TSOT23-8
See note 7
EXAMPLE
TOP MARK
PIN 1 ID
IAAAA
RECOMMENDED LAND PATTERN
TOP VIEW
SEATING PLANE
SEE DETAIL ''A''
FRONT VIEW
SIDE VIEW
NOTE:
DETAIL ''A''
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS
AFTER FORMING) SHALL BE 0.10 MILLIMETERS
MAX.
5) JEDEC REFERENCE IS MO-193, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP
MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP
MARK)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP5034 Rev 1.0
10/20/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
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