MP5424
5V PMIC with Four 4.5A/2.5A/4.5A/2A
Buck Converters, 3 LDOs, 1 Load Switch,
and Flexible System Settings via I2C and MTP
DESCRIPTION
The MP5424 is a complete power management
solution that integrates four high-efficiency stepdown DC/DC converters, three low-dropout
(LDO) regulators, one load switch, and a flexible
logic interface.
Constant-on-time (COT) control in the DC/DC
converter provides fast transient response. The
1.1MHz default switching frequency (fSW) during
continuous conduction mode (CCM) greatly
reduces
the
external
inductance
and
capacitance. Full protection features include
under-voltage lockout (UVLO) protection, overcurrent
protection
(OCP),
over-voltage
protection (OVP), and thermal shutdown.
•
•
•
The output voltage (VOUT) can be adjusted via the
I2C bus or preset by the multiple-time
programmable (MTP) interface. The startup/shutdown sequence can also be configured
via the MTP and controlled via the I2C bus.
The MP5424 requires a minimal number of
external components, and is available in a small
QFN-26 (3.5mmx4.5mm) package.
FEATURES
•
High-Efficiency Step-Down Converters:
o Buck 1: 4.5A DC/DC Converter
o Buck 2: 2.5A DC/DC Converter
o Buck 3: 4.5A DC/DC Converter
o Buck 4: 2A DC/DC Converter
o Buck 1 and Buck 3 Can Work in Parallel
o Buck 2 and Buck 4 Can Work in Parallel
o 2.7V to 5.5V Operating VIN Range
o Buck 1, Buck 2, and Buck 3 Selectable
VOUT Range: 0.4V to 2.2V/7.4mV Step or
0.4V to 3.58V VOUT/12.5mV Step
o Buck 4 VOUT Range: 0.4V to 3.58V
VOUT/12.5mV Step
o Adjustable Switching Frequency (fSW)
o Adjustable Soft-Start Time (tSS)
o Adjustable Phase Delay
o Configurable Forced PWM (FPWM)
Mode or Auto-PFM/PWM Mode
o Output OCP and OVP
MP5424 Rev. 1.0
12/6/2021
Low-Dropout (LDO) Regulators:
o Three 300mA, Low-Noise LDOs
o Two Separate Input Power Supplies
o 50mV Dropout at 300mA Load
Load Switch:
o 2.7V to 5.5V/3A Load Switch
o 50mΩ On Resistance at VIN = 5V
o On/Off Control via the I2C and
Programmable Sequence
o Configurable Output Discharge Function
via the I2C (Default: On)
System:
o I2C Bus and User-Programmable MTP
o Two-Time Programmable MTP (1)
o Start-Up/Shutdown Control
o Enable Pin (EN1) for Sleep Mode Entry
and Recovery Control
o Start-Up Reset Output
o Flexible Start-Up/Shutdown Sequence
via MTP (0.5ms, 2ms, 8ms, or 16ms
Selectable Time Slot)
o Available in a QFN-26 (3.5mmx4.5mm)
Package
Optimized Performance with
MPS Inductor MPL-AL6050
Series
Note:
1) The two-time programmable MTP is only for the standard
version of the MP5424GRM-0000.
APPLICATIONS
•
•
•
•
General Consumer
Camera Modules
3.3V/5V Powered Systems
Space-Limited Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
registered trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
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© 2021 MPS. All Rights Reserved.
1
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
TYPICAL APPLICATION
VIN5 = 5V
R1
100k
3.3V
3.3V
3.3V
C14
2.2µF
C13
2.2µF
RSTO PWRON OUT4
VIN1 = 2.7V
to 5.5V
OUT5
C15
10µF
L1
1µH
VIN5
SW1
C6
22µF x 2
VIN1
C1
22µF
FB1
L2
1.5µH
GND1
SW2
VIN2
C2
22µF
MP5424
GND2
L3
1µH
SW3
C3
22µF
L4
1.5µH
SW4
VIN4
FB4
R2
.
SDA
VOUT3 =
1.05V
C8
22µF x 2
FB3
C4
22µF
VOUT2 =
1.0375V
C7
22µF x 2
FB2
VIN3
VOUT1 =
1.05V
VOUT4 =
1.35V
C9
22µF x 2
SCL
AVIN
C5
0.1µF
LSWI
AGND
3.3V/
5V
LSWO
/EN1
C10
10µF
VOUT
OUT2
C12
2.2µF
1.8V
C11
10µF
MTP-EFUSE SELECTED TABLE BY DEFAULT (MP5424GRM-0000)
Buck 1
Buck 2
Buck 3
Buck 4
LSWO (2)
LDO 2
LDO 4
LDO 5
1.05V
1.0375V
1.05V
1.35V
3.3V/5V
1.8V
3.3V
3.3V
On
On
On
On
On
On
On
On
Mode
FPWM
FPWM
FPWM
FPWM
Start-up delay
1.5ms
1ms
1.5ms
0.5ms
5ms
5.5ms
Soft-start time (tSS)
300μs
300μs
300μs
300μs
MTP Items
Output voltage
Initial on/off
Switching frequency (fSW)
PWRON MODE
N/A
2ms
0ms
N/A
1.1MHz
0 (level trigger)
RSTODELAY
50ms
Buck 1 peak current limit
7.6A
Buck 2 peak current limit
3.9A
Buck 3 peak current limit
7.6A
Buck 4 peak current limit
3.9A
I2C slave address
0x69
MTP configuration code
0000
Note:
2) The load switch supply is on the LSWI pin. The supply voltage range is between 2.7V and 5.5V.
MP5424 Rev. 1.0
12/6/2021
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2
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
ORDERING INFORMATION
Part Number*
MP5424GRM-xxxx**
MP5424GRM-0000
Package
QFN-26 (3.5mmx4.5mm)
QFN-26 (3.5mmx4.5mm)
Top Marking
See Below
See Below
MSL
1
1
* For Tape & Reel, add suffix -Z (e.g. MP5424GRM-0000-Z, MP5424GRM-xxxx-Z).
** “xxxx” is the configuration code identifier for the register setting stored in the MTP.
The default number is “0000”. Each “x” can be a hexadecimal value between 0 and F. Contact an MPS FAE to
create this unique number.
TOP MARKING
MPS: MPS prefix
Y: Year code
W: Week code
M5424: Part number
LLLLL: Lot number
EVALUATION KIT EVKT-MP5424
EVKT-MP5424 kit contents (items below can be ordered separately):
#
Part Number
Item
Quantity
1
EV5424-R-00A
2
EVKT-USBI2C-02
3
MP5424-0000
MP5424GRM evaluation board
Includes one USB to I2C communication interface device, one USB
cable, and one ribbon cable
MP5424 IC which can be used for MTP programming
1
1
2
Order direct from MonolithicPower.com or our distributors.
Input Power Supply
Input
USB Cable
GUI
Ribbon Cable
USB to I2C
Communication
Interface
Evaluation Board
Output
Load
Load
Figure 1: EVKT-MP5424 Evaluation Kit Set-Up
MP5424 Rev. 1.0
12/6/2021
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3
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
PACKAGE REFERENCE
TOP VIEW
AVIN AGND
26
FB1
25
LSWO/
LSWI
EN1
24
23
1
22
OUT2
PWRON 2
21
FB2
VIN1
3
20
VIN2
SW1
4
19
SW2
GND1
5
18
GND2
SW3
6
17
SW4
VIN3
7
16
VIN4
FB3
8
15
FB4
RSTO
9
14
OUT5
10
SCL
11
12
13
SDA OUT4 VIN5
QFN-26 (3.5mmx4.5mm)
MP5424 Rev. 1.0
12/6/2021
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© 2021 MPS. All Rights Reserved.
4
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
PIN FUNCTIONS
Pin #
Name
1
FB1
2
PWRON
Start-up/shutdown input. The PWRON pin is a logic input pin that can start up or shut down
the device. PWRON has a weak internal pull-up current.
3
VIN1
Buck 1 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a
ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN1 path.
VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same bus voltage (VBUS).
4
SW1
Buck 1 switch output. Use a wide PCB trace for SW1 path.
5
GND1
6
SW3
Buck 3 switch output. Use a wide PCB trace for SW3 path.
7
VIN3
Buck 3 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a
ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN3 path.
VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same VBUS.
8
FB3
Feedback of buck3. Connect buck 3’s output directly to the FB3 pin.
9
RSTO
10
SCL
I2C clock signal input.
11
SDA
I2C data pin.
12
OUT4
LDO4 output. The LDO4 pin is powered by VIN5.
13
VIN5
LDO4 and LDO5 power input pin. This VIN5 pin operates from a 2.7V to 5.5V input voltage
(VIN). Connect the VIN5 and VIN1 pins if LDO4 and LDO5 are not used.
15
FB4
Buck 4 feedback. Connect buck ’s output directly to the FB4 pin.
16
VIN4
Buck 4 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a
ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN4 path.
VIN1, VIN2, VIN3, VIN4, and AVIN should be connected to the same VBUS.
17
SW4
Buck 4 switch output. Use a wide PCB trace for SW4 path
18
GND2
19
SW2
Buck 2 switch output. Use a wide PCB trace for SW2 path
20
VIN2
Buck 2 supply voltage input. The MP5424 operates from a 2.7V to 5.5V input rail. Use a
ceramic decoupling capacitor to decouple the input rail. Use a wide PCB trace for VIN2 path.
VIN1, VIN2, VIN3, VIN4, and AVIN must be connected to the same bus voltage.
21
FB2
Buck 2 feedback. Connect buck 2’s output directly to the FB2 pin.
22
OUT2
LDO 2 output. LDO 2 is powered by VIN2. If the OUT2 pin is configured as EN1, then OUT2
acts as an input pin. Pull EN1 high to turn on the PMIC; pull EN1 low to turn it off.
23
LSWI
Load switch input.
24
LSWO/
EN1
Load switch output or EN1. If the LSWO/EN1 pin is configured as EN1, then LSWO/EN1
acts as an input pin.
25
AGND
Analog ground. Connect the AGND pin to the GND1 and GND2 pins.
26
AVIN
MP5424 Rev. 1.0
12/6/2021
Description
Buck 1 feedback. Connect buck 1’s output directly to the FB1 pin.
Buck 1 and buck 3 power ground. The GND1 pin requires special consideration during PCB
layout. Connect GND1 to ground using copper traces and vias.
Reset output from the PMIC to CPU. The RSTO pin is an open-drain output. RSTO requires
an external pull-up resistor.
Buck 2 and buck 4 power ground. The GND2 pin requires special consideration during PCB
layout. Connect GND2 to ground using copper traces and vias.
Power supply input for logic circuitry. Use a 0.1µF ceramic capacitor to bypass the AVIN
pin to AGND. Connect AVIN to the system input via a . Ω resistor. VIN1, VIN2, VIN3, VIN4,
and AVIN should be connected to the same VBUS.
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5
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (3)
Thermal Resistance
VIN1, VIN2, VIN3, VIN4, VIN5, VAVIN ...............................
………………….-0.3V to +6.5V (6.8V for 300ms)
VSWx ...................................................................
-0.6V (-5V for VIN1
UVLO threshold. RSTO goes low if VIN1 < VIN1 UVLO threshold. RSTO goes high after
tRSTO. RSTO goes low with no delay. If VIN1 > VIN1 UVLO threshold and PWRON is
active, then RSTO monitors VIN1 while the PMIC is on
11: Monitors all enabled buck and LDO power rails. If the enabled bucks’ PG and
LDOs’ PG are good, then RSTO goes high after tRSTO. If any PG goes low, RSTO
goes low without a delay.
Sets tRSTO before RSTO goes high. tRSTO is not related to the default fSW.
RSTO_DELAY
D[5:4]
01
00: 100ms
01: 50ms
10: 10ms
11: 1ms
Sets the VIN1 UVLO rising threshold when RSTO_MODE is set to 10.
RSTO_PFI_
THLD
D[3:2]
10
00: 2.7V
01: 2.9V
10: 4V
11: 4.4V
Sets the start-up/shutdown sequence time slot intervals. The start-up/shutdown
sequences share the same time slot value. The time slot value is not related to the
default fSW.
TIME_SLOT
MP5424 Rev. 1.0
12/6/2021
D[3:2]
00
00: 0.5ms
01: 2ms
10: 8ms
11: 16ms
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27
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
Name
Bits
Default
Description
Selects the start-up sequence time slot mode.
0: The time slot is a fixed number set by TIME_SLOT
1: The time slot increases linearly, as shown below:
•
•
•
•
Time slot 0 to slot 3 has a TIME_SLOT x 1 interval
Time slot 3 to slot 7 has a TIME_SLOT x 2 interval
Time slot 7 to slot 11 has a TIME_SLOT x 4 interval
Time slot 11 to slot 15 has a TIME_SLOT x 8 interval
Time Slot Number
1
0
PWR_ON_
TIME_SLOT_
MODE
D[1]
2
3
4
5
6
7
9
8
10
11
12
13
14
15
0
VOUT
TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_ TIME_
SLOTx1 SLOTx1 SLOTx1 SLOTx2 SLOTx2 SLOTx2 SLOTx2 SLOTx4 SLOTx4 SLOTx4 SLOTx4 SLOTx8 SLOTx8 SLOTx8 SLOTx8
Example:
0.5ms
0.5ms
0.5ms
1ms
1ms
1ms
1ms
2ms
2ms
2ms
4ms
2ms
4ms
4ms
4ms
In a standard application, the start-up sequence ends at the maximum time slot of
enabled channels. For example, if time slot 7 is the maximum slot number of the
enabled channels (i.e. slot numbers above 7 are not used) during the start-up
sequence, then the counter only works until time slot 7. The start-up sequence is
complete, and the higher time slots are not executed.
Selects the shutdown sequence time slot mode.
0: The time slot is a fixed number set by TIME_SLOT
1: The time slot increases linearly, as shown below:
•
•
•
•
Time slot 0 to slot 3 has a TIME_SLOT x 1 interval
Time slot 3 to slot 7 has a TIME_SLOT x 2 interval
Time slot 7 to slot 11 has a TIME_SLOT x 4 interval
Time slot 11 to slot 15 has a TIME_SLOT x 8 interval
Time Slot Number
15
PWR_OFF_
TIME_SLOT_
MODE
D[0]
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
VOUT
Example:
TIME_ TIME_
TIME_
TIME_ TIME_
TIME_ TIME_ TIME_ TIME_ TIME_
TIME_ TIME_ TIME_ TIME_ TIME_
SLOTx8 SLOTx8 SLOTx8 SLOTx8 SLOTx4 SLOTx4 SLOTx4 SLOTx4 SLOTx2 SLOTx2 SLOTx2 SLOTx2 SLOTx1 SLOTx1 SLOTx1
4ms
4ms
4ms
4ms
2ms
2ms
2ms
2ms
1ms
1ms
1ms
1ms
0.5ms 0.5ms 0.5ms
If the EN_OFF_DELAY is disabled, then the shutdown sequence begins at the
maximum time slot of the enabled channels. For example, if time slot 7 is the
maximum slot number of the enabled channels (i.e. slot numbers above 7 are not
used) during the shutdown sequence, then the counter only works from time slot
7 to time slot 0. The shutdown sequence is complete, and the higher time slots are
not executed.
If the EN_OFF_DELAY is enabled, then the shutdown sequence starts from the
60th time interval, and the power rail turns off once the time interval decreases to
the power rail’s time slot. The shutdown delay of each power rail is determined by
the TIME_SLOT, PWR_OFF_TIME_SLOT_MODE and the time slot number.
MP5424 Rev. 1.0
12/6/2021
MonolithicPower.com
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28
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
Name
BUCK1_VREF,
BUCK2_VREF,
BUCK3_VREF,
BUCK4_VREF,
LDO2_VREF,
LDO4_VREF,
LDO5_VREF
Bits
D[7:0]
Default
00110100,
00110011,
00110100,
01001100,
01110000,
11101000,
11101000
Description
Sets the internal reference voltage (VREF). Buck outputs are between 400mV and
3587.5mV with 12.5mV per step. LDO outputs are from 650mV to 3587.5mV with
12.5mV per step. See Table 1 on page 32 for more details.
0000 0000: 400mV
0000 0001: 412.5mV
...
1111 1111: 3587.5mV
If the Buck1_VID, Buck2_VID, and Buck3_VID bits are set to 1, then the buck 1,
buck 2, and buck 3 VOUT range is between 400mV and 2.2V with a 7.4mV per step.
OVPEN1,
OVPEN2,
OVPEN3,
OVPEN4
D[6]
1
DISCHGEN1,
DISCHGEN2,
DISCHGEN3,
DISCHGEN4
D[5]
1
MODEBUCK1,
MODEBUCK2,
MODEBUCK3,
MODEBUCK4
D[4]
1
Enable bit for buck 1, buck 2, buck 3, and buck 4 output over-voltage protection
(OVP).
0: OVP disabled
1: OVP enabled
Enable bit for buck 1, buck 2, buck 3, and buck 4 output discharge function.
0: Discharge function disabled
1: Discharge function enabled
Selects auto-PFM/PWM mode or forced pulse-width modulation (FPWM) mode.
0: Auto-PFM/PWM mode
1: Forced PWM mode (FPWM)
Configures the high-side MOSFET (HS-FET) peak current limit (ILIMIT_PEAK) for
buck 1 and buck 3.
ILIM1, ILIM3
D[7:6]
10
00: 4.6A typical HS-FET ILIMIT_PEAK
01: 6.6A typical HS-FET ILIMIT_PEAK
10: 7.6A typical HS-FET ILIMIT_PEAK
11: 9.3A typical HS-FET ILIMIT_PEAK
Configures the HS-FET ILIMIT_PEAK for buck 2 and buck 4.
ILIM2, ILIM4
PHASE_
DELAY1,
PHASE_
DELAY2,
PHASE_
DELAY3,
PHASE_
DELAY4
SOFTSTART1,
SOFTSTART2,
SOFTSTART3,
SOFTSTART4
MP5424 Rev. 1.0
12/6/2021
D[7:6]
01
00: 2.7A typical HS-FET ILIMIT_PEAK
01: 3.9A typical HS-FET ILIMIT_PEAK
10: 5.1A typical HS-FET ILIMIT_PEAK
11: 6.1A typical HS-FET ILIMIT_PEAK
Sets the phase delay for buck 1, buck 2, buck 3, and buck 4.
D[5:4]
00, 01, 01,
00
00: 0° delay
01: 90° delay
10: 180° delay
11: 270° delay
Soft-start time (tSS) setting bit for buck 1, buck 2, buck 3, and buck 4. tSS is
between 10% and 90% of the target VOUT.
D[3:2]
01
00 :150μs
01: 300μs
10: 610μs
11: 920μs
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29
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
Name
POWER_OFF_
SLOT_NO_B1,
POWER_OFF_
SLOT_NO_B2,
POWER_OFF_
SLOT_NO_B3,
POWER_OFF_
SLOT_NO_B4,
POWER_OFF_
SLOT_NO_
LDO2,
POWER_OFF_
SLOT_NO_
LDSW,
POWER_OFF_
SLOT_NO_
LDO4,
POWER_OFF_
SLOT_NO_
LDO5
Bits
Default
This bit sets each power rail’s time slot number during the shutdown sequence. See
the TIME_SLOT register on page 28 and the PWR_OFF_TIME_SLOT_MODE
register on page 29 for more details. The delay times between neighboring slots are
not related to default fSW.
D[7:4]
0011,
0010,
0011,
0001,
0000,
0100
1010
1011
0000: Time slot 0
0001: Time slot 1
0010: Time slot 2
0011: Time slot 3
0100: Time slot 4
0101: Time slot 5
0110: Time slot 6
0111: Time slot 7
1000: Time slot 8
1001: Time slot 9
1010: Time slot 10
1011: Time slot 11
1100: Time slot 12
1101: Time slot 13
1110: Time slot 14
1111: Time slot 15
This bit sets each power rail’s time slot number during the start-up sequence (see the
TIME_SLOT register on page 28 and the PWR_ON_TIME_SLOT_MODE register on
page 29 for more details). The delay times between neighboring slots are not related
to the default fSW.
POWER_ON_
SLOT_NO_B1,
POWER_ON_
SLOT_NO_B2,
POWER_ON_
SLOT_NO_B3,
POWER_ON_
SLOT_NO_B4,
POWER_ON_
SLOT_NO_
LDO2,
POWER_ON_
SLOT_NO_
LDSW,
POWER_ON_
SLOT_NO_
LDO4,
POWER_ON_
SLOT_NO_
LDO5
D[3:0]
DISCHGEN_
LDO2,
DISCHGEN_
LDO4,
DISCHGEN_
LDO5
D[5]
1
BUCK1_VID,
BUCK2_VID,
BUCK3_VID
D[2:0]
000
EN1_SELECT
Description
0011,
0010,
0011,
0001,
0000,
0100101
0
1011
0000: Time slot 0
0001: Time slot 1
0010: Time slot 2
0011: Time slot 3
0100: Time slot 4
0101: Time slot 5
0110: Time slot 6
0111: Time slot 7
1000: Time slot 8
1001: Time slot 9
1010: Time slot 10
1011: Time slot 11
1100: Time slot 12
1101: Time slot 13
1110: Time slot 14
1111: Time slot 15
Enable bit for the LDO2, LDO4 and LDO5 output discharge function.
0: Discharge function disabled
1: Discharge function enabled
Sets the buck 1, buck 2, and buck 3 VOUT range and resolution.
D[5]
0
0: VOUT is 400mV to 3.5875V with 12.5mV per step
1: VOUT range is 400mV to 2.2V with 7.4mV per step
Selects LSWO or LDO 2 as the EN1 pin. If the EN1 function is enabled, then the
corresponding load switch or LDO 2 channel and its discharge function should be
turned off.
0: Selects LSWO as EN1 pin
1: Selects LDO2 as EN1 pin
MP5424 Rev. 1.0
12/6/2021
MonolithicPower.com
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© 2021 MPS. All Rights Reserved.
30
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
Name
Bits
Default
Description
Enables the shutdown delay. This bit is only active if EN_OFF_MODE = 0.
EN_OFF_
DELAY
D[4]
0
EN_OFF_
MODE
D[3]
0
DISCHGEN_
LDSW
D[5]
1
I2C_SLAVE_
ADDRESS
D[4:0]
01001
ILIM_LDO4,
ILIM_LDO5
PARALLEL_1
0: Shutdown delay disabled. The shutdown sequence begins at the largest time slot
of the enabled channel
1: Enable shutdown delay. The shutdown sequence begins at the 60th time interval,
the power rail turns off once the time interval decreases to the power rail’s time
interval. The time interval of each power rail is determined by TIME_SLOT,
PWR_OFF_TIME_SLOT_MODE, and the time slot number
Sets the shutdown sequence behavior controlled by the PWRON pin. There is always
a shutdown sequence while controlled by EN1.
0: Shutdown sequence
1: No shutdown sequence. All power rails turn off at the same time
Enable bit for the load switch output discharge function.
0: Discharge function disabled
1: Discharge function enabled
Sets the A5 to A1 bit of the slave I2C address. See the I2C Bus Slave Address section
on page 34 for more details.
Selects the LDO 4 and LDO 5 current limit (ILIMIT).
D[6]
D[7]
0
0
0: Lower ILIMIT supports 300mA IOUT
1: Higher ILIMIT supports 550mA IOUT
Sets whether buck 1 and buck 3 operate in parallel. Use FB1 as the feedback pin.
After the buck converters enter parallel mode, buck 3’s I2C/MTP register is invalid.
Parallel mode takes effect during a start-up through VIN. After start-up, the PMIC does
not respond to changes on this bit. ILIMIT is doubled based on buck 1’s register setting.
0: Buck 1 and buck 3 do not operate in parallel
1: Buck 1 and buck 3 operate in parallel
PARALLEL_2
D[6]
0
Sets whether buck 2 and buck 4 operate in parallel mode. Use FB2 as the feedback
pin. After the buck converters enter parallel mode, buck ’s I2C/MTP register is
invalid. Parallel mode takes effect during a start-up through VIN. After start-up, the
PMIC does not respond to changes on this bit. ILIMIT is doubled based on buck 2’s
register setting.
0: Buck 2 and buck 4 do not operate in parallel
1: Buck 2 and buck 4 operate in parallel
This bit defines the PWRON pin’s behavior (level trigger or falling-edge trigger).
PWRON_
MODE
EN_EN1_PIN
D[5]
D[4]
0
0
0: Level trigger. This functions as an EN pin. If the PWRON pin’s VIN exceeds the
rising threshold, then the PMIC begins the start-up sequence
1: Falling-edge trigger. If the PWRON pin detects a high to low transition and the PMIC
is off, then the PMIC begins the start-up sequence after a delay. If the PMIC is on,
then the PMIC begins the shutdown sequence after a delay. The delay time is set by
PWRON_DEBOUNCE_TIMER
Enable bit of EN1 function. EN1_POWER_RAILS_CONTROL defines which power
rails are controlled by the EN1 pin. EN1_INV defines EN1 active low or active high.
EN_SELECT defines LSWO or LDO 2 as EN1.
0: EN1 function disabled
1: EN1 function enabled
Sets EN1 to active low or active high.
EN1_INV
MP5424 Rev. 1.0
12/6/2021
D[7]
1
0: A low-level input to EN1 turns on the corresponding power rails
1: A high-level input to EN1 turns on the corresponding power rails
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MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
Name
Bits
Default
Description
This bit sets which power rails are controlled by EN1. Each bit controls 1 power rail
from D[6] to D[0].
EN1_POWER_
RAILS_
CONTROL
D[6:0]
0000111
EN_BUCK1,
EN_BUCK2,
EN_BUCK3,
EN_BUCK4,
EN_LDO2,
EN_LDSW,
EN_LDO4,
EN_LDO5
D[7:0]
0xFF
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Buck 1
Buck 2
Buck 3
Buck 4
LDSW
LDO 4
LDO 5
0: EN1 does not control the power rail’s start-up/shutdown sequence
1: EN1 controls this power rail’s start-up/shutdown sequence
If the EN1 function is enabled, the corresponding load switch or LDO 2 channel and
its discharge function should be turned off. Note that EN1 cannot control LDO 2. LDO
2 can only be controlled by PWRON
Enable control bit for each power rail.
0: Disabled
1: Enabled
Table 1: Output Reference Voltage Chart (BUCK1_VID = 0, Buck2_VID = 0, Buck3_VID = 0)
D[7:0]
VREF (mV)
D[7:0]
VREF (mV)
D[7:0]
VREF (mV)
00000000
400
01010110
1475
10101100
2550
00000001
412.5
01010111
1487.5
10101101
2562.5
00000010
425
01011000
1500
10101110
2575
00000011
437.5
01011001
1512.5
10101111
2587.5
00000100
450
01011010
1525
10110000
2600
00000101
462.5
01011011
1537.5
10110001
2612.5
00000110
475
01011100
1550
10110010
2625
00000111
487.5
01011101
1562.5
10110011
2637.5
00001000
500
01011110
1575
10110100
2650
00001001
512.5
01011111
1587.5
10110101
2662.5
00001010
525
01100000
1600
10110110
2675
00001011
537.5
01100001
1612.5
10110111
2687.5
00001100
550
01100010
1625
10111000
2700
00001101
562.5
01100011
1637.5
10111001
2712.5
00001110
575
01100100
1650
10111010
2725
00001111
587.5
01100101
1662.5
10111011
2737.5
00010000
600
01100110
1675
10111100
2750
00010001
612.5
01100111
1687.5
10111101
2762.5
00010010
625
01101000
1700
10111110
2775
00010011
637.5
01101001
1712.5
10111111
2787.5
00010100
650
01101010
1725
11000000
2800
00010101
662.5
01101011
1737.5
11000001
2812.5
00010110
675
01101100
1750
11000010
2825
00010111
687.5
01101101
1762.5
11000011
2837.5
MP5424 Rev. 1.0
12/6/2021
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MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
D[7:0]
VREF (mV)
D[7:0]
VREF (mV)
D[7:0]
VREF (mV)
00011000
700
01101110
1775
11000100
2850
00011001
712.5
01101111
1787.5
11000101
2862.5
00011010
725
01110000
1800
11000110
2875
00011011
737.5
01110001
1812.5
11000111
2887.5
00011100
750
01110010
1825
11001000
2900
00011101
762.5
01110011
1837.5
11001001
2912.5
00011110
775
01110100
1850
11001010
2925
00011111
787.5
01110101
1862.5
11001011
2937.5
00100000
800
01110110
1875
11001100
2950
00100001
812.5
01110111
1887.5
11001101
2962.5
00100010
825
01111000
1900
11001110
2975
00100011
837.5
01111001
1912.5
11001111
2987.5
00100100
850
01111010
1925
11010000
3000
00100101
862.5
01111011
1937.5
11010001
3012.5
00100110
875
01111100
1950
11010010
3025
00100111
887.5
01111101
1962.5
11010011
3037.5
00101000
900
01111110
1975
11010100
3050
00101001
912.5
01111111
1987.5
11010101
3062.5
00101010
925
10000000
2000
11010110
3075
00101011
937.5
10000001
2012.5
11010111
3087.5
00101100
950
10000010
2025
11011000
3100
00101101
962.5
10000011
2037.5
11011001
3112.5
00101110
975
10000100
2050
11011010
3125
00101111
987.5
10000101
2062.5
11011011
3137.5
00110000
1000
10000110
2075
11011100
3150
00110001
1012.5
10000111
2087.5
11011101
3162.5
00110010
1025
10001000
2100
11011110
3175
00110011
1037.5
10001001
2112.5
11011111
3187.5
00110100
1050
10001010
2125
11100000
3200
00110101
1062.5
10001011
2137.5
11100001
3212.5
00110110
1075
10001100
2150
11100010
3225
00110111
1087.5
10001101
2162.5
11100011
3237.5
00111000
1100
10001110
2175
11100100
3250
00111001
1112.5
10001111
2187.5
11100101
3262.5
00111010
1125
10010000
2200
11100110
3275
00111011
1137.5
10010001
2212.5
11100111
3287.5
00111100
1150
10010010
2225
11101000
3300
00111101
1162.5
10010011
2237.5
11101001
3312.5
00111110
1175
10010100
2250
11101010
3325
MP5424 Rev. 1.0
12/6/2021
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MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
D[7:0]
VREF (mV)
D[7:0]
VREF (mV)
D[7:0]
VREF (mV)
00111111
1187.5
10010101
2262.5
11101011
3337.5
01000000
1200
10010110
2275
11101100
3350
01000001
1212.5
10010111
2287.5
11101101
3362.5
01000010
1225
10011000
2300
11101110
3375
01000011
1237.5
10011001
2312.5
11101111
3387.5
01000100
1250
10011010
2325
11110000
3400
01000101
1262.5
10011011
2337.5
11110001
3412.5
01000110
1275
10011100
2350
11110010
3425
01000111
1287.5
10011101
2362.5
11110011
3437.5
01001000
1300
10011110
2375
11110100
3450
01001001
1312.5
10011111
2387.5
11110101
3462.5
01001010
1325
10100000
2400
11110110
3475
01001011
1337.5
10100001
2412.5
11110111
3487.5
01001100
1350
10100010
2425
11111000
3500
01001101
1362.5
10100011
2437.5
11111001
3512.5
01001110
1375
10100100
2450
11111010
3525
01001111
1387.5
10100101
2462.5
11111011
3537.5
01010000
1400
10100110
2475
11111100
3550
01010001
1412.5
10100111
2487.5
11111101
3562.5
01010010
1425
10101000
2500
11111110
3575
01010011
1437.5
10101001
2512.5
11111111
3587.5
01010100
1450
10101010
2525
01010101
1462.5
10101011
2537.5
I2C Bus Slave Address
The slave address is a 7-bit address followed by an 8th read or write (R/W) data direction bit. The A5,
A4, A3, A2, and A1 bits can be configured via the MTP e-fuse.
Setting Value
A7
A6
A5
A4
A3
A2
A1
1
1
0 (15)
1 (15)
0 (15)
0 (15)
1 (15)
Notes:
15) This bit is configurable via the MTP e-fuse.
16) The slave address is 0x69 (A[7:1] = 1101 001) by default.
MP5424 Rev. 1.0
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MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
I2C REGISTER MAP
Add
(hex)
NAME
R/W
D7
00
CTL0
R/W
DVS SLEW RATE
FREQUENCY
01
CTL1
R/W
RSTO_MODE
RSTO_DELAY
02
03
04
05
CTL2
R/W
Buck 1
R/W
R/W
R/W
06
R/W
07
08
R/W
R/W
09
Buck 2
R/W
0B
0C
0D
R/W
R/W
R/W
0E
R/W
0F
R/W
10
R/W
11
Buck 4
12
13
14
15
R/W
LDO 2
16
17
18
R/W
R/W
LOAD_
SW
19
1A
1B
LDO 4
LDO 5
21
22
EN
23
24
28
29
ILIM2
R/W
R/W
R/W
MTP_CTL
R/W
Status 2
Reserved
ID2
D1
D0
PWRON_DEBOUNCE_
TIMER
RSTO_PFI_THLD
Reserved
Reserved
SOFTSTART2
Reserved
POWER_ON_SLOT_NO_B2
BUCK3_VREF: 0.4V to 3.5875V/12.5mV step or 0.4V to 2.2V/7.4mV step
OVPEN3
DISCHGEN3 MODEBUCK3
Reserved
ILIM3
PHASE_DELAY3
SOFTSTART3
POWER_OFF_SLOT_NO_B3
Reserved
POWER_ON_SLOT_NO_B3
BUCK4_VREF: 0.4V to 3.5875V/12.5mV step
RESERVED
OVPEN4
DISCHGEN4
ILIM4
MODEBUCK4
PHASE_DELAY4
Reserved
SOFTSTART4
POWER_OFF_SLOT_NO_B4
RESERVED
POWER_ON_SLOT_NO_B4
EN_OFF_
EN_OFF_ BUCK3_
BUCK2_
BUCK1_VID
DELAY
MODE
VID
VID
LDO2_VREF: 0.65V to 3.5875V/12.5mV step
DISCHGEN_
Reserved
Reserved
I2C_SLAVE_ADDRESS
LDO2
POWER_OFF_SLOT_NO_LDO2
POWER_ON_SLOT_NO_LDO2
Reserved
DISCHGEN_
Reserved
Reserved
Reserved
Reserved
LDSW
POWER_OFF_SLOT_NO_LDSW
POWER_ON_SLOT_NO_LDSW
LDO4_VREF: 0.65V to 3.5875V/12.5mV step
DISCHGEN_
Reserved
ILIM_LDO4
Reserved
Reserved
LDO4
POWER_OFF_SLOT_NO_LDO4
POWER_ON_SLOT_NO_LDO4
LDO5_VREF: 0.65V to 3.5875V/12.5mV step
DISCHGEN_
Reserved
ILIM_LDO5
Reserved
RESERVED
LDO5
POWER_OFF_SLOT_NO_LDO5
POWER_ON_SLOT_NO_LDO5
PARALLEL_1 PARALLEL_2
PWRON_
EN_EN1_
RESERVED
(17)
(17)
MODE (17)
PIN (17)
EN1_INV (17)
EN1_POWER_RAILS_CONTROL(17)
EN_
EN_BUCK1
EN_BUCK2
EN_BUCK3
EN_BUCK4
EN_LDO2
EN_LDO4
EN_LDO5
LDSW
RESERVED
EN1_SELECT
MTP configure code ("0x00" for standard MP5424-0000, "0x01" for MP5424-0001)
MTP revision number (MTP revision number is stored here, in case the user must update the MTP)
ENTER_MTP_
MODE
PROGRAM_
MTP (18)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MTP Program Password
R
R
(18)
D2
POWER_ON_SLOT_NO_B1
PHASE_DELAY2
W
Status 1
Reserved
POWER_OFF_SLOT_NO_B2
R/W
R/W
26
27
R/W
R/W
Parallel
Mode
Standby 1
25
R/W
R/W
R/W
1F
20
R/W
R/W
R/W
1C
1D
1E
R/W
D3
BUCK2_VREF: 0.4V to 3.5875V/12.5mV step or 0.4V to 2.2V/7.4mV step
OVPEN2
DISCHGEN2 MODEBUCK2
RESERVED
Reserved
R/W
R/W
D4
POWER_OFF_SLOT_NO_B1
R/W
CTL3
D5
PWR_ON_ PWR_OFF_
Reserved
Reserved
TIME_SLOT
TIME_SLOT TIME_SLOT
_MODE
_MODE
BUCK1_VREF: 0.4V to 3.5875V/12.5mV step or 0.4V to 2.2V/7.4mV step
Reserved
OVPEN1
DISCHGEN1 MODEBUCK1
Reserved
ILIM1
PHASE_DELAY1
SOFTSTART1
Reserved
R/W
0A
Buck 3
D6
PGLDO4
OTWARNING
R
Reserved "1"
OTEMPP
PGLDO2
Reserved "1"
PGBUCK4
PG
BUCK3
PGBUCK2
PGBUCK1
Reserved
CHECKSUM
FLAG
Reserved
Reserved
Reserved
Reserved
PGLDO5
CURRENT MTP PAGE
INDEX
VENDOR ID
Reserved
Notes:
17) The I2C bits do not control the real circuitry. Only the MTP bits control those functions. The MTP value only reloads the circuitry when the
PWRON pin turns off, the MTP is configured, or AVIN > UVLO threshold.
18) Reserved bits must be written to 0.
Register Description
MP5424 Rev. 1.0
12/6/2021
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MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
Most of the register bits share the same
description as the MTP e-fuse configuration
table on page 26. Table 2 shows the descriptions
of the I2C register bits that are different from the
MTP register bits.
2
The I C register's default values are determined
by the MTP table.
The I2C register can be reset to the hard-coded
default values under two conditions:
1. There is a CRC error while loading the MTP.
2. The MTP page is set to 0.
Thermal shutdown does not reset the I2C register.
Table 2: I2C Register Descriptions
Name
Bits
Default
Description
ENTER_MTP_
MODE
D[7]
0
Set ENTER_MTP_MODE to 1 to enter pre-MTP configure mode. After MTP
configuration is complete, ENTER_MTP_MODE resets automatically to 0.
PROGRAM_
MTP
D[6]
0
If PROGRAM_MTP is set 1, then the PMIC executes an MTP configure action .
After MTP configuration is complete, PROGRAM_MTP resets automatically to 0.
PG indicator for the buck converters and LDOs. If VOUT exceeds 90% of the VREF,
then PGx = 1. If VOUT drops below 80% of VREF, then PGx = 0.
PGx
D[X]
0
OTWARNING
D[7]
0
Die temperature early warning bit. If OTWARNING is high, this indicates that the
die temperature has exceeded 120°C. OTWARNING latches once it is triggered.
Write 1 to OTWARNING to clear it.
OTEMPP
D[6]
0
Over-temperature (OT) indicator. If OTEMPP is high, this indicates that thermal
shutdown has been triggered. OTEMPP latches once it is triggered. Write 1 to
OTEMPP to clear it.
D[7:4]
1000
D[4]
0
VENDOR ID
CHECKSUM
FLAG
CURRENT
MTP PAGE
INDEX
During I2C-controlled dynamic voltage scaling, the PG deglitch timer blanks the
possible PG glitch. These PG bits change dynamically to indicate the power good
of each buck’s and each LDO’s status.
Vendor identification.
1: The current MTP page has a CRC or checksum error
0: The current MTP data passes the CRC test
CURRENT MTP PAGE INDEX stores the current MTP page index information. The
IC cannot access the MTP while D[1:0] = 10b. The MP5424 MTP can only be
configured two times.
D[1:0]
00
00: Default page; two other pages can be used
01: First page
10: Second page
11: Reserved
MP5424 Rev. 0.81
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Preliminary Specifications Subject to Change ©
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36
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
APPLICATION INFORMATION
Selecting the Inductor
Optimized Performance with
MPS Inductor MPL-AL6050 Series
For most applications, use a 0.47µH to 2.2µH
inductor with a DC current rating at least 25%
greater than the maximum load current
(ILOAD_MAX). For improved efficiency, use an
inductor with a DC resistance below 15mΩ. For
most designs, the inductance (L1) can be
calculated with Equation (1):
L1 =
VOUT (VIN − VOUT )
VIN IL fOSC
(1)
with X5R or X7R dielectrics are recommended
due to their low ESR and small temperature
coefficients. For most applications, a 22µF
capacitor is sufficient.
Since the input capacitor (C1) absorbs the input
switching current, it requires an adequate ripple
current rating. The RMS current in C1 (IC1) can
be estimated with Equation (3):
IC1 = ILOAD
VOUT VOUT
1−
VIN
VIN
The worst-case condition occurs at VIN = 2 x VOUT,
which can be estimated with Equation (4):
Where ∆IL is the inductor ripple current.
Choose the inductor ripple current to be
approximately 30% of ILOAD_MAX. The maximum
inductor peak current (IL(MAX)) can be estimated
with Equation (2):
IL(MAX ) = ILOAD +
IL
2
(2)
Choose an inductor with a higher inductance to
improve efficiency under light-load conditions
(
Inductors for more information.
Selecting the Step-Down Converter Input
Capacitor (C1)
The step-down converter has a discontinuous
input current (IIN), and requires a capacitor to
supply the AC current to the converter while
maintaining the DC VIN. Use low-ESR capacitors
for the best performance. Ceramic capacitors
MP5424 Rev. 1.0
12/6/2021
(3)
IC1 =
ILOAD
2
(4)
For simplification, choose C1 to have an RMS
current rating greater than half of ILOAD_MAX.
C1 can be electrolytic, tantalum, or ceramic. If
using electrolytic or tantalum capacitors, add a
small, high-quality ceramic capacitor (0.1μF)
placed as close to the IC as possible. If using
ceramic capacitors, ensure that they have
enough capacitance to provide sufficient charge
to prevent excessive voltage ripple at the input.
The input voltage ripple (∆VIN) caused by the
capacitance can be calculated with Equation (5):
VIN =
V
ILOAD
V
OUT 1 − OUT
fSW C1 VIN
VIN
(5)
Selecting the Step-Down Converter Output
Capacitor (C2)
The output capacitor (C2) for the step-down
converter maintains the DC VOUT. C2 can be
ceramic, tantalum, or electrolytic. For the best
results, use low-ESR capacitors to keep the
output voltage ripple (∆VOUT) low. For most
applications, two 22µF ceramic capacitors are
sufficient .
∆VOUT can be estimated with Equation (6):
VOUT =
VOUT
V
1 − OUT
fSW L1
VIN
1
RESR +
8
f
C2
SW
(6)
Where RESR is the equivalent series resistance
(ESR) value of C2.
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MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
For ceramic capacitors, the capacitance
dominates the impedance at fSW, and causes the
majority of ∆VOUT. For simplification, ∆VOUT can
be calculated with Equation (7):
ΔVOUT =
VOUT
V
1 − OUT
2
8 fSW L1 C2
VIN
(7)
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at fSW.
For simplification, ∆VOUT be estimated with
Equation (8):
ΔVOUT =
VOUT
V
1 − OUT RESR
fSW L1
VIN
(8)
The characteristics of C2 also affect the system
stability.
Table 4 lists the recommended components for
MP5424.
Table 4: Recommended External Components for DC/DC Converters and LDOs
MP5424 Rev. 1.0
12/6/2021
Component
Value
Notes
VIN1 input
capacitor (CIN)
22μF
0805 size/10V ceramic capacitor
VIN2 CIN
22μF
0805 size/10V ceramic capacitor
VIN3 CIN
22μF
0805 size/10V ceramic capacitor
VIN4 CIN
22μF
0805 size/10V ceramic capacitor
VIN5 CIN
10μF
0805 size/10V ceramic capacitor
AVIN CIN
0.1μF
0603 size/10V ceramic capacitor
Buck 1 output
capacitor (COUT)
22μF x 2
0805 size/10V ceramic capacitor
Buck 1 inductor
1μH
ISAT > current limit
Buck 2 COUT
22μF x 2
0805 size/10V ceramic capacitor
Buck 2 inductor
1.5μH
ISAT > current limit
Buck 3 COUT
22μF x 2
0805 size/10V ceramic capacitor
Buck 3 inductor
1μH
ISAT > current limit
Buck 4 COUT
22μF x 2
0805 size/10V ceramic capacitor
Buck 4 inductor
1.5μH
ISAT > current limit
LSWI CIN
10μF
0603 size/6.3V ceramic capacitor
LDO 2 COUT
2.2μF
0603 size/6.3V ceramic capacitor
LSWO COUT
10μF
0603 size/6.3V ceramic capacitor
LDO 4 COUT
2.2μF
0603 size/6.3V ceramic capacitor
LDO 5 COUT
2.2μF
0603 size/6.3V ceramic capacitor
RSTO pull-up
resistor
100kΩ
0603 or 0402 size film resistor
AVIN series resistor
to VIN1 RSTO pullup resistor
4.7Ω
0603 or 0402 size film resistor
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38
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
PCB Layout Guidelines (19)
Efficient PCB layout is critical for stable
operation. It is recommended to use a 4-layer
board for improved performance. For the best
results, refer to Figure 17 and follow the
guidelines below:
2. Connect the input capacitor to the VINx pin
using short and wide traces.
1. Connect the input ground to the GNDx pin
using short and wide traces.
4. Route SW away from sensitive analog areas,
such as FB1, FB2, FB3, and FB4.
Buck 1
3. Ensure FB1, FB2, FB3, and FB4 are Kelvinconnected to the buck 1, buck 2, buck 3, and
buck 4 output capacitors. Do not connect FB
directly to the inductor’s output node.
VIN1
PGND
SW1
VIN2
SW2
AGND
FB1
AVIN
26
Buck 2
AGND
25
LSWO/
LSW1
EN1
24
OUT2
23
1
22
2
21
3
20
SW1
4
19
SW2
GND1
5
18
GND2
SW3
6
17
7
16
VIN4
15
FB4
FB2
PWRON
VIN1
PGND
VIN3
8
FB3
9
VIN2
PGND
SW4
14
RSTO
10
11
12
13
SCL
SDA
OUT4
VIN5
R1
OUT5
C14
SW3
SW4
VIN5
Buck 3
VIN3
PGND
VIN4
Buck 4
Top Layer
Mid-Layer 1
Bottom Layer
Figure 17: Recommended PCB Layout (20)
Notes:
19) The recommended PCB layout is based on Figure 18 on page 40.
20) It is recommended to separate buck 1’s PGND and buck 3’s PGND from buck 2’s PGND and buck ’s PGND on the top layer.
MP5424 Rev. 1.0
12/6/2021
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39
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
TYPICAL APPLICATION CIRCUITS
R1
100k
3.3V
VIN1 = 2.7V
to 5.5V
3
C1
22µF
5
20
C2
22µF
VIN5 = 5V
3.3V
3.3V
C14
C15
C13
2.2µF
2.2µF
10µF
13
9
2
12
14
L1
1µH
RSTO PWRON OUT4
OUT5
VIN5
4
SW1
VIN1
1
FB1
GND1
SW2
VIN2
FB2
18
7
GND2
MP5424
SW3
VIN3
C3
22µF
FB3
16
SW4
VIN4
C4
22µF
R2
. Ω
FB4
SCL
26
C5
0.1µF
AVIN
LSWO
/EN1
LSWI
AGND
23
24
25
C10
10µF
VOUT
3.3V/
5V
SDA
OUT2
22
C12
C11
2.2µF
10µF
L2
19 1.5µH
L3
1µH
VOUT2 =
1.0375V
VOUT3 =
1.05V
C8
22µF x 2
8
17
C6
22µF x 2
C7
22µF x 2
21
6
VOUT1 =
1.05V
L4
1.5µH
15
VOUT4 =
1.35V
C9
22µF x 2
10
11
1.8V
Figure 18: Typical Application Circuit (21) (22)
MP5424 Rev. 1.0
12/6/2021
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40
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
TYPICAL APPLICATION CIRCUITS (continued)
VIN5: 5V
R1
100k
3.3V
3.3V
9
2
RSTO PWRON
VIN1 = 2.7V
to 5.5V
3
10µF
C15
13
VIN5
SW1
VIN1
4
L1
1µH
VOUT1 =
1.05V
C6
22µF x 4
6
SW3
C1
22µF
5
20
C2
22µF
3.3V
2.2µF
2.2µF
C14
C13
12
14
OUT4
OUT5
18
7
GND1
FB1
VIN2
FB3
GND2
VIN3
C3
22µF
MP5424
SW2
FB2
16
VIN4
C4
22µF
SW4
FB4
SCL
R2
. Ω
26
C5
0.1µF
SDA
AVIN
1
8
L2
1.5µH
19
VOUT2 =
1.0375V
C7
22µF x 2
21
17
L4
1.5µH
15
VOUT4 =
1.35V
C9
22µF x 2
10
11
LSWO
OUT2
LSWI
AGND
/EN1
24
22
23
25
C12
C10
C11
2.2µF
10µF
10µF
VOUT
1.8V
3.3V/
5V
Figure 19: Typical Application Circuit (with Buck 1 and Buck 3 in Parallel) (21) (22)
Notes:
21) VIN5’s minimum VIN is equal to the maximum nominal VOUT of LDO 4 and LDO 5. Connect the VIN5 and VIN1 pins if LDO 4 and LDO 5 are
not used.
22) If operating at a 2.2MHz fSW and with a small duty cycle, ensure that the buck’s on time is >100ns for increased system stability.
MP5424 Rev. 1.0
12/6/2021
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41
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
PACKAGE OUTLINE DRAWING FOR 26L FCQFN (3.5X4.5MM)-2
MF-PO-D-0426 revision 0.0
PACKAGE INFORMATION
QFN-26 (3.5mmx4.5mm)
PIN 1 ID
0.15X45º TYP
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
0.15X45º
1) LAND PATTERNS OF PIN1,9,14,22 HAVE THE SAME
LENGTH AND WIDTH.
2)ALL DIMENSIONS ARE IN MILLIMETERS.
3) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP5424 Rev. 1.0
12/6/2021
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42
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
CARRIER INFORMATION
1
Pin1
1
ABCD
1
1
ABCD
ABCD
ABCD
Feed Direction
Part Number
MP5424GRM0000-Z
MP5424 Rev. 1.0
12/6/2021
Package
Description
QFN-26
(3.5mmx4.5mm)
Quantity/ Quantity/ Quantity/
Reel
Carrier
Reel
Tube
Tray
Diameter Tape Width
5000
N/A
N/A
13in
12mm
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Carrier
Tape Pitch
8mm
43
MP5424 – 5V POWER MANAGEMENT IC WITH I2C AND MTP
REVISION HISTORY
Revision #
Revision Date
1.0
12/06/2021
Description
Pages Updated
Initial Release
-
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP5424 Rev. 1.0
12/6/2021
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