MP6004
Primary-Side Regulated Flyback/Buck
80V DCDC Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP6004 is a monolithic flyback dc-dc
converter with a 180 V power switch that
targets isolated or non-isolated 13 W PoE
applications. It supports both primary-side
regulated flyback and high-voltage buck
applications.
•
MP6004 uses fixed peak current and variable
frequency discontinuous conduction mode
(DCM) to regulate constant output voltage. The
primary-side regulation without opto-coupler
feedback in flyback mode simplifies the design
and saves BOM cost while buck mode
minimizes the solution size for non-isolated
applications. A 180 V integrated power
MOSFET optimizes the device for various wide
voltage applications.
The MP6004 protection features include overload protection, over-voltage protection, opencircuit protection, and thermal shutdown.
The MP6004 is available
3mm x 3mm package.
in
a
QFN-14
•
•
•
•
•
•
•
•
•
Supports Primary-Side Regulated Flyback
without Opto-Coupler Feedback
Supports Buck from Up to 80 V Input
Integrated 180 V Switching Power MOSFET
Internal 80 V Start-Up Circuit
Up to 3 A Programmable Current Limit
Discontinuous Conduction Mode
OLP, OVP, Open-Circuit, and Thermal
Protection
Flexible Self-Power or External VCC Power
Minimal External Component Count
Available in a QFN-14 3mm x 3mm
Package
APPLICATIONS
•
•
•
•
Security Cameras
VoIP Phones
WLAN Access Points
General Flyback and Buck Converters
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
ORDERING INFORMATION
Part Number*
MP6004GQ
Package
QFN-14 (3mm x 3mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP6004GQ–Z)
TOP MARKING
AMN: Product code of MP6004GQ
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
2
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
VIN ............................................-0.3 V to +100 V
SW ............................................-0.7 V to +180 V
FB1 .........................................-0.7 V to +6.5 V(2)
FB2 to VIN .................................-6.5 V to +0.3 V
All other pins ...........................-0.3 V to +6.5 V(3)
VCC sinking current ............................. 1.5 mA(4)
FB1 sinking current ............................... ±1 mA(2)
EN sinking current .................................. 1 mA(5)
Continuous power dissipation (TA = +25°C) (6)
................................................................ 2.5 W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +150°C
Recommended Operating Conditions
(7)
Supply voltage (VIN) ........................14 V to 80 V
Switching voltage (VSW) ............-0.5 V to +150 V
Maximum VCC sinking current ............ 1.2 mA(4)
Maximum FB1 sinking current ........... ±0.5 mA(2)
Maximum EN sinking current ............... 0.5 mA(5)
Maximum switching frequency.............. 200 kHz
Maximum current limit................................... 3 A
Switching junction temp. (TJ). .. -40°C to +125°C
MP6004 Rev. 1.0
4/14/2015
Thermal Resistance
(8)
θJA
θJC
QFN-14 (3mm x 3mm)........... 50....... 12 °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) Refer to the “Output Voltage Setting” section on page 18.
3) VCC and EN voltage can be pulled higher than this rating, but
the external pull-up current should be limited. Refer to “VCC
sinking current” and “EN sinking current” ratings to the left.
4) Refer to the “VCC Power Supply Setting” section on page 17..
5) Refer to the “EN Control Setting” section on page 17.
6) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
7) The device is not guaranteed to function outside of its
operating conditions.
8) Measured on JESD51-7, 4-layer PCB.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
3
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 48 V, VEN = 5 V, VOUT = 12 V, TJ = -40°C to 125°C, typical value is tested at 25°C, unless
otherwise noted.
Parameter
Symbol Condition
Power supply and UVLO
VIN UVLO rising threshold
VIN UVLO falling threshold
VCC regulation(9)
VCC UVLO rising
threshold(9)
VCC UVLO falling
threshold(9)
Quiescent current
EN high-level voltage
EN low-level voltage
EN input current
Voltage feedback
FB1 reference voltage
FB1 leakage current
Flyback mode DCM detect
threshold on FB1
FB1 open-circuit threshold
FB1 OVP threshold
Minimum diode conduction
time for FB1 sample
FB2 reference voltage
FB2 leakage current
Buck mode DCM detect
threshold on SW
Switching power device
On resistance
Current sense
Current limit
Current leading-edge
Blanking time
MP6004 Rev. 1.0
4/14/2015
Min
Typ
Max
Units
10.5
7.4
4.8
11.6
8.2
5.4
12.8
9
5.9
V
V
V
4.3
4.7
5.1
V
4
4.5
4.8
V
5.5
1.3
7.5
μA
V
V
μA
1.94
1.99
2.04
V
1.93
1.99
2.05
V
10
50
nA
25
50
75
mV
VFB1OPEN
VFB1OVP
-90
120%
-60
125%
-20
130%
mV
VREF1
TSAMPLE
1.4
2.2
3
μs
-1.955
-1.88
-1.805
V
-1.96
-1.88
-1.8
V
10
50
nA
0.14
V
VIN-R
VIN-F
VCC
VCC-R
VCC-F
IQ
VIN rising
VIN falling
Load = 0 mA to 10 mA
VIN is higher than UVLO, Vcc
rising
VIN is higher than UVLO, Vcc
falling
VFB1 = 2.2 V, VFB2 = VIN
380
3.9
VREF1
IFB1
VDCM1
VREF2
IFB2
Respect to GND, TJ = 25°C
Respect to GND, TJ = -40°C to
+125°C
Respect to GND, VFB1 = 2 V
Respect to GND
Respect to VIN, TJ = 25°C
Respect to VIN, TJ = -40°C to
+125°C
Respect to VIN, VFB2 = -2 V
VDCM2
Respect to VIN
RON-SW
VCC = 5.4 V
ILIMIT
TLEB
RILIM = 53.6 kΩ, L = 47 μH
0
0.8
1.85
2.05
450
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
Ω
2.25
A
ns
4
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 48 V, VEN = 5 V, VOUT = 12 V, TJ = -40°C to 125°C, typical value is tested at 25°C, unless
otherwise noted.
Parameter
Symbol Condition
DCDC converter thermal shutdown
Min
Typ
Max
Units
Thermal shutdown
temperature(10)
TSD
150
ºC
Thermal shutdown
hysteresis(10)
THYS
20
ºC
NOTES:
9) The maximum VCC UVLO rising threshold is higher than the minimum VCC regulation in the EC table due to production distribution.
However, for one unit, VCC regulation is higher than the VCC UVLO rising threshold. The VCC UVLO rising threshold is about 87 percent
of the VCC regulation voltage, and the VCC UVLO falling threshold is about 83 percent of the VCC regulation voltage in one unit.
10) Guaranteed by characterization, not tested in production.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
5
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 48 V, VOUT = 12 V, IOUT = 1 A, TA = 25°C, unless otherwise noted.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
6
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48 V, VOUT = 12 V, IOUT = 1 A, TA = 25°C, unless otherwise noted.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
7
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48 V, VOUT = 12 V, IOUT = 1 A, Flyback mode, TA = 25°C, unless otherwise noted.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
8
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48 V, VOUT = 12 V, IOUT = 1 A, Flyback mode, TA = 25°C, unless otherwise noted.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
9
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48 V, VOUT = 12 V, IOUT = 1 A, Flyback mode, TA = 25°C, unless otherwise noted.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
10
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48 V, VOUT = 12 V, IOUT = 1 A, Flyback mode, TA = 25°C, unless otherwise noted.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
11
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
PIN FUNCTIONS
PIN#
Name
Description
1, 2
GND
Switching converter power return.
3
EN
Regulator on/off control input. EN can program VIN UVLO start-up through a Zener
diode and a resistor divider.
4,12
NC
No connection. NC is not connected internally. Float NC or connect to GND in layout.
5
VIN
Positive power supply terminal.
6
FB2
Feedback for non-isolated buck solution. Connect FB2 to VIN in flyback application.
7
MODE
8
FB1
Feedback for flyback solution. Connect FB1 to GND in buck application.
9
ILIM
IC switching current limit program pin. Connect ILIM to GND through a resistor to
program the peak current limit.
10
AGND
11
VCC
Supply bias voltage pin, powered through internal LDO from VIN. It is recommended
to connect a capacitor (no less than 1 µF) between VCC and GND.
13,14
SW
Drain of converter switching MOSFET.
MP6004 Rev. 1.0
4/14/2015
Buck mode or flyback mode select pin. MODE is pulled up internally to VCC through a
1.5 µA current source. Float MODE for buck application mode; connect MODE to GND for
flyback application mode.
Analog power return for switching converter control circuit.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
12
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
FUNCTION DIAGRAM
VIN
VIN
VAUX
VCC
High-Voltage
LDO
VIN/VCC UVLO
EN
VIN
FB1
VOUT
DCM Detection
SW
Feedback
Sampling
Control & Driver
Management
VAUX
VIN
FB2
Protection
Current Sense
ILIMIT Program
AGND
MODE
GND
ILIM
Figure 1—Functional block diagram
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
13
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
OPERATION
Start-Up and Power Supply
MP6004 features an 80 V start-up circuit. When
VIN is higher than 4.3 V, the capacitor at VCC is
charged through the internal LDO. Normally VCC
is regulated at 5.4 V (if VIN is high enough),
and the VCC UVLO is 4.7 V, typically. With the
exception of VCC UVLO, the MP6004 has an
additional 11.6 V VIN UVLO. When VIN is higher
than the 11.6 V UVLO, VCC is charged higher
than the 4.7 V UVLO, and EN pin is high,
MP6004 starts switching.
VCC can be powered from the transformer
auxiliary winding to save IC power loss. Refer
to the “Vcc Power Supply Setting” section on
page 18 for more details.
Figure 2—Primary-side current waveform
The primary-side inductance (LM) stores energy
in each cycle as a function of Equation (2):
E=
1 2
LMIPK
2
Calculate the power transferred from the input
to the output with Equation (3):
P=
Flyback and Buck Mode
MP6004 supports both flyback and buck
topology applications. Connect MODE to GND
to set the MP6004 in flyback mode, and float
MODE to set the MP6004 in buck mode. MODE
is pulled up internally to VCC through a 1.5 µA
current source. Do not connect MODE to VIN in
buck mode, and do not place a resistor
between MODE and GND in flyback mode.
1 2
LMIPKFS
2
(3)
Where FS is the switching frequency. When IPK
is constant, the output power depends on FS
and LM.
Use Equation (4) to calculate the rate at which
the current rises linearly in buck mode:
dIp(t )
dt
Switching Work Principle
(2)
=
VIN − VOUT
LM
(4)
After start-up, MP6004 works in discontinuous
conduction mode (DCM). The second switching
cycle will not start until the inductor current
drops to 0 A. In each cycle, the internal
MOSFET is turned on, and the current-sense
circuit senses the current IP(t) internally.
The internal MOSFET turns off when IP(t) rises
to IPK (see Figure 3). The output current is
calculated with Equation (5):
Use Equation (1) to calculate the rate at which
the current rises linearly in flyback mode:
Where, D is the inductor current conducting
duty cycle.
dIp(t )
dt
=
VIN
LM
IOUT =
1
DIPK
2
(5)
(1)
When IP(t) rises up to IPK, the internal MOSFET
turns off (see Figure 2). The energy stored in
the primary-side inductance transfers to the
secondary-side through the transformer.
Figure 3—Inductor current waveform
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
14
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
Light-Load Control
In flyback mode (if the load decreases),
MP6004 stretches down the frequency
automatically to reduce the power transferring
while keeping the same IPK in each cycle. An
approximate 10 kHz minimum frequency is
applied to detect the output voltage even at a
very light load. During this condition, the
switching IPK jumps between 20 percent of the
normal IPK and 100 percent of the normal IPK to
reduce the power transferring. The MP6004 still
transfers some energy to the output even if
there is no load on the output due to the 10 kHz
minimum frequency. This means that some
load is required to maintain the output voltage,
or else VOUT will rise and trigger an OVP.
In buck mode, the MP6004 has no minimum
frequency limit, so it stretches down to a very
low frequency and regulates the output
automatically even there is no load on the
output.
Frequency Control
By monitoring the auxiliary winding voltage in
flyback mode or monitoring the SW voltage in
buck mode, the MP6004 detects and regulates
the inductor current in DCM. The frequency is
controlled by the peak current, the current ramp
slew rate, and the load current. The maximum
frequency occurs when the MP6004 runs in
critical conduction mode, providing the
maximum load power. The MP6004 switching
frequency should be lower than 200 kHz in the
design.
Voltage Control
In flyback application, the MP6004 detects the
auxiliary winding voltage from FB1 during the
secondary-side diode conduction period.
Assume the secondary winding is the master,
and the auxiliary winding is the slave. When the
secondary-side diode conducts, the FB1
voltage is calculated with Equation (6):
VFB1 =
NA
R2
× (VOUT + VD1F ) ×
NS
R1 + R2
Where:
VD1F is the output diode forward-drop voltage.
(6)
NA and NS are the turns of the auxiliary winding
and the secondary-side winding, respectively.
R1 and R2 are the resistor dividers for sampling.
The output voltage differs from the secondarywinding voltage due to the current-dependant
diode forward voltage drop. If the secondarywinding voltage is always detected at a fixed
secondary current, the difference between the
output voltage and the secondary-winding
voltage is a fixed VD1F. MP6004 starts sampling
the auxiliary-winding voltage after the internal
power MOSFET turns off for 0.7 μs and finishes
the sampling after the secondary-side diode
conducts for 3 μs. This provides good
regulation when the load changes. However,
the secondary diode conducting period must be
longer than 3 μs in each cycle, and the FB1
signal must be smooth 0.7 μs after the switch
turns off.
With a buck solution, there is one FB2 pin
referenced to VIN. It can be used as the
reference voltage for the buck application. The
output voltage is referenced to VIN and does
not have the same GND as the input power.
Programming the Current Limit
The MP6004 current limit is set by an external
resistor (R3) from ILIM to ground. The value of
R3 can be estimated with Equation (7):
ILIM =
100 VL × 0.18
+
R3
L
(7)
Where ILIM is the current limit in A, VL is the
voltage applied on the inductor when the
MOSFET turns on, R3 is the setting resistor in
kΩ, and L is the inductor in μH.
The current limit cannot be programmed higher
than 3 A.
Leading-Edge Blanking
Transformer parasitic capacitance induces a
current spike on the sense resistor when the
power switch turns on. The MP6004 includes a
450 ns leading-edge blanking period to avoid
falsely terminating the switching pulse. During
this blanking period, the current sense
comparator is disabled, and the gate driver
cannot switch off.
VOUT is the output voltage.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
15
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
DCM Detection
Over-Load Protection
The
MP6004
regulator
operates
in
discontinuous conduction mode in both flyback
and buck modes.
MP6004 will always work in DCM mode for any
condition.
In flyback mode, the MP6004 detects the falling
edge of the FB1 voltage in each cycle. The
second cycle switching will not start unless the
chip detects a 50 mV falling edge on FB1.
In buck mode, the MP6004 detects the falling
edge of the SW voltage in each cycle. The
second cycle switching will not start unless the
chip detects 0.14 V falling edge between
VSW-VIN.
Over-Voltage & Open-Circuit Protection
In flyback mode, the MP6004 includes overvoltage protection (OVP) and open-circuit
protection. If the voltage at FB1 exceeds 125
percent of VREF1 (or FB1’s -60 mV falling edge
cannot be detected because the feedback
resistor is removed), immediately the MP6004
shuts off the driving signal and enters hiccup
mode by re-charging the internal capacitor. The
MP6004 resumes normal operation when the
fault is removed.
In flyback mode, the secondary-side diode
conduction duty cycle is limited to about 80
percent. In an over-load condition, the output
energy is limited by IPK and FS. With a heavier
load, the output drops and the diode conduction
period becomes longer. This causes the
switching frequency to drop so that the output
energy can be limited. The MP6004 has same
protection logic for an over-load/output-short
condition.
In buck mode, the duty cycle limitation does not
apply, but the output current is limited to half of
IPK.
Thermal Shutdown
When the junction temperature exceeds 150°C,
the MP6004 shuts down. Once the temperature
drops below 130°C, the part
re-starts
automatically.
In buck mode, if the voltage at FB2 is higher
than the reference voltage, the MP6004 stops
switching immediately.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
16
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
APPLICATION INFORMATION
EN Control Setting
MP6004 turns on when EN goes high, and it
turns off when EN goes low. EN is pulled low
internally by an approximate 0.9 MΩ resistor.
In flyback mode, the maximum on time is
limited at about 8 μs. The secondary-side
rectifier diode conduction time should be longer
than 3 μs for FB1 feedback sampling. If VIN
decreases and the inductor current cannot
ramp the IPK to setting value within the
maximum on time, the diode conduction time
decreases to less than 3 μs, causing FB1
feedback sample failure. The MP6004 treats
this failure as a VOUT drop and generates more
pulses, causing VOUT to overshoot. In this
condition, EN can be used to program VIN
UVLO and shuts down the part before VIN drops
(triggering the maximum on time). Since the EN
high-level voltage is 3.9 V and the low-level
voltage is 1.3 V, it is hard to program the VIN
UVLO with a small hysteresis. In this condition,
one resistor divider and one Zener diode is
recommended (see Figure 4).
Zener diode and resistor divider are
recommended to set the appropriate VIN UVLO.
There is an internal Zener diode on EN, which
clamps the EN voltage to prevent runaway. The
maximum pull-up current for the internal Zener
clamp (assuming 6.5 V) should be less than 0.5
mA. If EN is driven with an external signal, use
a signal voltage less than 6.5 V or connect EN
to the signal through a pull-up resistor that
ensures the maximum pull-up current is less
than 0.5 mA. If using a resistor divider (see
Figure 4) and VIN-VZENER is higher than 6.5 V,
the minimum resistance for the pull-up resistor
R5 should be calculated with Equation (10):
VIN − VZENER − 6.5V 6.5V
−
< 0.5mA
R5
R6
(10)
VCC Power Supply Setting
The VCC voltage is charged through the internal
LDO by VIN. Normally, VCC is regulated at 5.4 V,
typically. A capacitor no less than 1 µF is
recommended for decoupling between VCC and
GND.
In flyback mode, VCC can be powered from the
transformer auxiliary winding to save the highvoltage LDO power loss.
Figure 4—VIN UVLO setting with EN control
For example, the MP6004 should be turned on
before VIN rises to 36 V and shut down before
VIN drops to 20 V. One 20 V Zener diode (D4)
and a resistor divider (R5 = 100 kΩ/R6 = 49.9
kΩ) can be selected to program the VIN UVLO.
The programmed VIN rising threshold can be
calculated with Equation (8):
VIN_R < 20V +
100kΩ + 49.9kΩ
× 3.9V = 31.7V
49.9kΩ
(8)
The programmed VIN falling threshold is
calculated with Equation (9):
VIN_F > 20V +
100kΩ + 49.9kΩ
× 1.3V = 23.9V
49.9kΩ
(9)
In buck mode, FB2 feedback is not affected by
the rectifier diode conduction time, but the
MP6004 Rev. 1.0
4/14/2015
Figure 5—Supply VCC from auxiliary winding
The auxiliary winding supply voltage can be
calculated with Equation (11):
VCC =
NA
× (VOUT + VD1F ) − VD3F
NS
(11)
Where NA and NS are the turns of the auxiliary
winding and the output winding, VD1F is the
output rectifier diode voltage drop, and VD3F is
the D3 voltage drop in Figure 5.
VCC voltage is clamped at about 6.2 V by one
internal Zener diode. The clamp current
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
17
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
capability is about 1.2 mA. If the auxiliary
winding power voltage is higher than 6.2 V
(especially in a heavy-load condition), a series
resistor (R8) is necessary to limit the current to
VCC. For simple application, supply the VCC
power through the internal LDO directly.
Output Voltage Setting
Generally, select R2 with a 10 kΩ to 50 kΩ
resistor to limit noise and provide an
appropriate R1 for the -0.5 mA negative current
limit.
In buck application, the feedback pin is FB2.
The output voltage can be estimated with
Equation (13):
In MP6004, there are two feedback pins for
different application modes.
In flyback mode, the converter detects the
auxiliary winding voltage from FB1. R1 and R2
are the resistor dividers for the feedback
sampling (see Figure 6).
Na
FB1
R1
Figure 6—Feedback in isolation application
When the primary-side power MOSFET turns
off, the auxiliary-winding voltage is sampled.
The output voltage is estimated with Equation
(12):
VOUT
V
× (R1 + R 2 ) NS
= REF1
×
− VD1F
R2
NA
(12)
Where,
NS is the transformer secondary-side winding
turns.
NA is the transformer auxiliary winding turns.
VD1F is the rectifier diode forward drop.
VREF1 is the reference voltage of FB1 (1.99 V,
typically).
When the primary-side power MOSFET turns
on, the auxiliary winding forces a negative
voltage to FB1. The FB1 voltage is clamped to
less than -0.7 V internally, but the clamp current
should be limited to less than -0.5 mA by R1.
For example, if the auxiliary winding forces
-11 V to R1 (to make the current flowing from
FB1 to R1 lower than -0.5 mA), R1 resistance
must be higher than 22 kΩ (if ignoring R2
current).
MP6004 Rev. 1.0
4/14/2015
R1 + R2
× VREF2
R2
(13)
Where, VREF2 is the reference voltage of FB2
-1.88 V, typically.
Maximum Switching Frequency
When MP6004 works in DCM, the frequency
reaches its maximum value during a full-load
condition. The maximum frequency is affected
by the peak current limit, the inductance, and
the input/output voltage. Generally, design the
maximum frequency lower than 200 kHz.
GND
R2
VOUT = −
In buck mode, the maximum frequency occurs
when the buck runs in critical conduction mode.
The frequency can be calculated with Equation
(14):
FSW _ MAX =
(VIN − VOUT ) × VOUT
ILIM × L × VIN
(14)
Where, ILIM is the IPK set by the current limit
resistor.
With a lighter load, the frequency is lower than
the maximum frequency above.
In flyback mode, design the maximum
frequency with the minimum input voltage and
the maximum load condition. Calculate the
frequency with Equation (15):
FSW ≤
1
TON + TCON + TDELAY
(15)
Where:
TON is the MOSFET one pulse turn-on time
determined with Equation (16):
ILIM × LM
VIN
(16)
transformer
primary-winding
TON =
LM is the
inductance.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
18
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TCON is the rectifier diode current conducting
time and can be calculated with Equation (17):
TCON
NS × ILIM × LM
=
NP × (VOUT + VD1F )
(17)
Where, NS is the transformer secondary-side
winding turns.NP is the transformer primary-side
winding turns.
TDELAY is the resonant delay time from the
rectifier diode current drop to 0 A to the
auxiliary-winding voltage drop to 0 V. The
resonant time can be tested on the board
(estimate around 0.5 μs).
Output Capacitor Selection
The output capacitor maintains the DC output
voltage. For best results, use ceramic
capacitors or low ESR capacitors to minimize
the output voltage ripple. For ceramic
capacitors, the capacitance dominates the
impedance at the switching frequency.
In flyback application, the worst output ripple
occurs under a light-load condition; the worst
output ripple can be estimated by Equation (21):
VOUTP _ P =
0.5 × NP × ILIM × TCON
NS × C2
(21)
In flyback mode, the MP6004 samples the
feedback signal within 3 μs after the primaryside MOSFET turns off. The secondary-side
diode conduction time in Equation (17) should
be higher than 3 μs. This time period, combined
with the duty cycle, determines the maximum
frequency.
Where,
C2 is the output capacitor value.
VOUTP-P is the output ripple.
Input Capacitor Selection
An input capacitor is required to supply the AC
ripple current to the inductor while limiting noise
at the input source. A low ESR capacitor is
required to keep the noise to the IC at a
minimum. Ceramic capacitors are preferred, but
tantalum or low ESR electrolytic capacitors will
suffice. For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The ripple will be the worst at light
load. The required input capacitance can be
estimated with Equation (18):
0.5 × ILIM × TON
(18)
C =
In buck application, the worst Vout ripple can be
estimated with Equation (22):
1
VINP _ P
Where C1 is the input capacitor value, VINP-P is
the expected input ripple, and TON is the
MOSFET turn-on time.
In an isolated application, TON is calculated with
Equation (19):
I ×L
(19)
T = LIM M
ON
VIN
Normally, a 44 μF or higher ceramic capacitor is
recommended as the output capacitor. This
allows a small Vo ripple and stable operation.
VOUTP _ P =
0.5 × ILIM2 × L × (VIN + VD1F )
C2 × (VIN − VOUT ) × (VOUT + VD1F )
(22)
Leakage Inductance
The
transformer’s
leakage
inductance
decreases system efficiency and affects the
output current and voltage precision. Optimize
the transformer structure to minimize the
leakage inductance. Aim for a leakage
inductance less than 3 percent of the primarywinding inductance.
RCD Snubber for Flyback
The transformer leakage inductance causes
spikes and excessive ringing on the MOSFET
drain voltage waveform, affecting the output
voltage sampling 0.7 µs after the MOSFET
turns off. The RCD snubber circuit limits the SW
voltage spike (see Figure 7).
In a non-isolation application, TON is calculated
with Equation (20):
I ×L
(20)
T = LIM
ON
VIN − VOUT
Where L is the buck`s inductor value.
Figure 7—RCD snubber
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
19
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
The power dissipation in the snubber circuit is
estimated with Equation (23):
PSN =
1
× LK × ILIM2 × FS
2
(23)
Where, LK is the leakage inductance.
Since R4 consumes the majority of the power,
R4 is estimated with Equation (24):
VD1 = VOUT +
VIN × NS
+ VPD1
NP
(27)
VPD1 can be selected at 40 percent ~100
percent of VOUT + VIN x NS/NP. An RC or RCD
snubber circuit for the output diode D1 is
recommended.
(24)
In buck mode, the diode reverse voltage
equates to the input voltage. A 20 percent ~ 40
percent margin is recommended.
Where, VSN is the expected snubber voltage on
C4.
In both applications, the current rating should
be higher than the maximum output current.
The snubber capacitor C4 can be designed to
get appropriate voltage ripple on the snubber
using Equation (25):
Dummy Load
V 2
R4 = SN
PSN
ΔVSN =
VSN
R4 × C4 × FS
(25)
Generally, a 15 percent ripple is acceptable.
Buck Inductor Selection
The inductor is required to transfer the energy
between the input source and the output
capacitors. Unlike normal application where
inductors determine the inductor ripple, the
MP6004 always works in DCM while VIN, VOUT,
and ILIM are constant. The inductor only
determines the speed of the current rising and
falling, which determines the switching period.
The expected maximum frequency can
determine the inductor value using Equation
(26):
(V − V OUT ) × (VOUT + VD1F )
1
L ≈ IN
×
(VIN + VD1F ) × IPEAK
FSW
(26)
FSW is the expected maximum switching
frequency, which should be lower than 200 kHz
in general setting.
Output Diode Selection
The output rectifier diode supplies current to the
output capacitor when the internal MOSFET is
off. Use a Schottky diode to reduce loss due to
the diode forward voltage and recovery time.
In isolation application, the diode should be
rated for a reverse voltage greater than
Equation (27):
MP6004 Rev. 1.0
4/14/2015
When the system operates without a load in
flyback mode, the output voltage rises above
the normal operation voltage because of the
minimum switching frequency limitation. Use a
dummy load for good load regulation. A large
dummy load decreases efficiency, so the
dummy load is a tradeoff between efficiency
and load regulation. For applications using
Figure 10, a minimum load of around 10 mA is
recommended.
PCB Layout Guidelines
Efficient PCB layout for high-frequency
switching power supplies is critical. Poor layout
may result in reduced performance, excessive
EMI, resistive loss, and system instability. For
best results, refer to Figure 8 and Figure 9 and
follow the guidelines below:
For flyback application:
1. Keep the input loop as short as possible
between the input capacitor, transformer,
SW, and GND plane for minimal noise and
ringing.
2. Keep the output loop between the rectifier
diode, the output capacitor, and the
transformer as short as possible.
3. Keep the clamp loop circuit between D2, C4,
and the transformer as small as possible.
4. Place the VCC capacitor close to VCC for
the best decoupling. The current setting
resistor R3 should be placed as close to
ILIM and AGND as possible.
5. Keep the feedback trace far away from
noise sources (such as SW). The trace
connecting FB1 should be short.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
20
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
6. Use a single point connection between
power GND and signal GND. Vias around
GND
and
the
thermal
pad
are
recommended to lower the die temperature.
Top Layer
Bottom Layer
Via
2
1
VOUTGND
Figure 8—Recommended flyback layout
For buck application:
1. Keep the input loop as short as possible
between the input capacitor, rectifier diode,
SW, and GND plane for minimal noise and
ringing.
2. Keep the output loop between the rectifier
diode, the output capacitor, and the inductor
as short as possible.
3. Place the VCC capacitor close to VCC for
the best decoupling. The current setting
resistor R3 should be placed as close to
ILIM and AGND as possible.
4. Connect the output voltage sense and VIN
power supply from the output capacitor with
parallel traces. The feedback trace should
be far away from noise sources (such as
SW). The trace connected to FB2 should be
short.
5. Use a single point connection between
power GND and signal GND. Vias around
GND
and
the
thermal
pad
are
recommended to lower the die temperature.
VOUT
1
2
2
1
VIN
VINGND
Figure 9—Recommended buck layout
Design Example
Table 1 shows a design example following the
application guidelines for the following
specifications in flyback applications:
Table 1—Flyback design example
36 V-72 V
VIN
12 V
VOUT
0 A-1 A
IOUT
The typical application circuit for VOUT = 12 V in
Figure 10 shows the detailed application
schematic and is the basis for the typical
performance waveforms. For more detailed
device applications, please refer to the related
evaluation board datasheet.
Table 2 shows a design example following the
application guidelines for the following
specifications in buck applications:
Table 2—Buck design example
VIN
VOUT
IOUT
36 V-72 V
12 V
0 A-1 A
The typical application circuit is shown in Figure
11. For more detailed device applications,
please refer to the related evaluation board
datasheet.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
21
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
TYPICAL APPLICATION CIRCUITS
VIN
36 V-72 V
T1
D4
20 V
C1B
47 µF
R4
10 k
C1A
2.2 µF
C4
10 nF
SBR8U60P5
C5
R7
Ns
PGND
EN
U1
VCC
C2A
22 µF
C3
1 µF
R3
52.3 k
PGND
ILIM
FB1
R1
56.2 k
MODE
AGND
C2B
22 µF
AGND
MP6004
PGND
20Ω
AGND
R6
VINGND
1 nF
Np2
SW
VCC
49.9 k
PGND
D2
200 V
FB2
VIN
R5
100 k
12 V@1 A
VOUT
D1
Np1
R2
20 k
GND
R8
1k
C6
VCC
1 nF/2000 V
PGND
PGND
VOUTGND
D3
PGND
PGND
C2C
220 µF
AGND
FB2
VIN
Figure 10—Flyback application circuit, VIN = 36 V-72 V, VOUT = 12 V, IOUT =1 A
Figure 11—Buck application circuit, VIN = 36 V-72 V, VOUT = 12 V, IOUT = 1 A
20 k
47 µF
2.2 µF
20 V
22 µF
100 k
100 µF
33 k
GND
L1 10 µH
SW
EN
VCC
FB1
MP6004
49.9 k
1 µF
ILIM
43.2 k
GND
AGND
GND
MODE
GND
GND
GND
GND
Figure 12—Buck application circuit, VIN = 36 V-72 V, VOUT = 5 V, IOUT = 1 A
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
22
MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER
PACKAGE INFORMATION
QFN-14 (3mm X 3mm)
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
PIN 1 ID OPTION A
0.30x45° TYP.
SIDE VIEW
PIN 1 ID OPTION B
R0.20 TYP.
DETAIL A
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-229.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP6004 Rev. 1.0
4/14/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
23
工商网监
湘ICP备2023018690号
