HR1200
High-Performance
Digital PFC+LLC Combo Controller
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
DESCRIPTION
FEATURES
The HR1200 is a high-performance controller
that integrates an advanced digital PFC
controller and a half-bridge LLC resonant
controller. It requires quite low input power at
no load or ultra-light load, making it compliant
with Energy using Product Directive (EuP) Lot 6
and Code of Conduct Version 5 Tier 2
specifications.
General System Features
The PFC of the HR1200 employs a patented
average current control scheme, which can
operate both in continuous conduction mode
(CCM) and discontinuous conduction mode
(DCM) according to the instantaneous condition
of the input voltage and output load. The IC
exhibits excellent efficiency and high power
factor (PF) at light load. In CCM, the HR1200
can be used in applications up to 500W with
minimal board size limitations. The performance
of the PFC can be optimized by programming
multiple parameters through an I2C GUI.
Programming can be completed either by the
factory or by the customer referring to a
detailed user guide.
The half-bridge LLC resonant converter
achieves high efficiency with zero-voltage
switching (ZVS). The HR1200 implements an
adaptive dead-time adjustment (ADTA) function
to guarantee ZVS in different load conditions.
Additionally, the HR1200 can prevent the LLC
converter from operating in capacitive mode,
making it more robust and easier to design.
The HR1200 integrates a high-voltage (HV)
current source internally for start-up. When the
AC input is removed, the HV current source
also functions as an X-cap discharger. Such
features are helpful to reduce related devices,
thus reduce power consumption at no load.
The HR1200 has multiple protection features
including thermal shutdown (TSD), open-loop
protection (OLP), over-current protection (OCP),
over-voltage protection (OVP), and brownin/brown-out protection.
Meets EuP Lot 6 and COC Version 5 Tier 2
Specifications
HV Current Source for Start-Up
Smart X-Cap Discharger
Standard I2C Interface
1k EEPROM to Store Parameters
User-Friendly GUI for Digital PFC
PFC Controller
High Efficiency from Light Load to Full Load
by CCM/DCM Multi-Mode Control
High PF Due to Patented Input Capacitor
Current Compensation
Programmable Frequency Jittering
Programmable Brown-In and Brown-Out
Programmable Soft Start
Cycle-by-Cycle Current Limit
Open-Loop Protection
LLC Controller
600V High-Side Gate Driver with Integrated
Bootstrap Diode and High dv/dt Immunity
Adaptive Dead-Time Adjustment of HB LLC
with Minimum and Maximum Limit
Burst Mode Switching
Safe Start-Up in Case of System Fault
Two-Level Over-Current Protection (OCP)
Latch Shutdown Protection
Over-Temperature Protection (OTP)
Capacitive Mode Protection
APPLICATIONS
Notebook Adapters
All-in-One or Gaming Power Supply
Desktop PC and ATX Power
General AC/DC Power Supply up to 600W
LCD TV and Plasma TV Power Supply
MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under quality assurance. “MPS”
and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
Analog digital adaptive modulation (ADAM) and advanced asynchronous
mode (AAM) are trademarks of Monolithic Power Systems, Inc.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
1
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
Q5
Rfmax
GNDP
C8
C4
SO
TIMER
SDA
SCL
R6
HV
SS
CSS
RSS
BURST
FSET
CT
GNDS
VCC
HR1200
RES
GNDD
R5
V3.3
C3
ACIN
CSP
R4
V3.3
RHV
Rin1
90-264VAC
47-63Hz
CX1
LCM1
D1
D2
CX2
Rin2
B1
C1
Rsp
LPFC
Q1
R9
R8
D3
R1
R2
R3
U*
CSHB
CHBVS
GATEP
LSG
SW
HBVS
HSG
C2
Vreg BST
FBP
Cbst
C5
Cbus
+
Vbus=400V
D4
Rfmin
CT
C9
R10
Q3
Q2
Rf
Cf D5
+
Lr
C7
D6
R7
C6
Cr
T2
Q4
MP6922
Feedback
Network
C10
Vout-
Vout+
TYPICAL APPLICATION
Figure 1: Typical Application
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
2
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
ORDERING INFORMATION
Part Number*
Package
Top Marking
HR1200GM−XXXX*
HR1200GY−XXXX*
TSSOP-28
SOIC-28
See Below
*−XXXX: internal code version control.
For customer-specific projects, MPS will assign a special 4-digit number.
For Tape & Reel, add suffix −Z (e.g. HR1200GM−XXXX−Z)
For Tape & Reel, add suffix −Z (e.g. HR1200GY−XXXX−Z)
TOP MARKING
MPS: MPS prefix
YY: year code
WW: week code
HR1200: first six digits of the part number
LLLLLLLLL: lot number
PACKAGE REFERENCE
SDA
1
28
SCL
SDA
1
28
SCL
ACIN
2
27
FBP
ACIN
2
27
FBP
RES
3
26
V3.3
RES
3
26
V3.3
CSP
4
25
SS
CSP
4
25
SS
GNDD
5
24
CT
GNDD
5
24
CT
GNDP
6
23
FSET
GNDP
6
23
FSET
GATEP
7
22
BURST
GATEP
7
22
BURST
VREG
8
21
CSHB
VREG
8
21
CSHB
LSG
9
20
GNDS
LSG
9
20
GNDS
TIMER
10
19
HBVS
TIMER
10
19
HBVS
SO
11
SO
11
18
NC
VCC
12
17
SW
HV
HR1200
14
TSSOP-28
HR1200 Rev 1.1
3/25/2020
HR1200
17
SW
VCC
12
16
HSG
NC
13
16
HSG
15
BST
HV
14
15
BST
SOIC-28
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
3
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
θJA
θJC
Recommended Operating Conditions(1)
Thermal Resistance(4)
HVpk ......................................................... ≤500V
Supply voltage (VCC) ......................... 14V to 30V
Operating junction temp. .......... -40°C to +125°C
TSSOP-28 .............................. 82 ....... 20 ... °C/W
SOIC-28 ................................. 60 ....... 30 ... °C/W
ABSOLUTE MAXIMUM RATINGS(2)
Parameter
General
Total power dissipation(3)
Storage temperature
Junction temperature
Lead temperature
Voltage
Voltage on HV
Floating supply voltage
Floating ground voltage
Voltage on high-side gate driver
Floating ground max. slew rate
Voltage on VCC
Voltage on VREG
VREG Supply Current
V3.3 Supply Current
Voltage on low-side gate driver
Voltage on PFC gate driver
Voltage on CS
Voltage on HBVS
Other analog pins
Other digital pins
Analog ground to digital ground
Current
Current on HBVS
Source current of FSET
ESD(4)
Symbol
Ptotal
Tstg
TJ
TLEAD
VHV
VBST
VSW
VHSG
dVSW/dt
VCC
Vreg
Ireg
I3V3
VLSG
VPFCG
VCS
VHBVS
Condition
Min
Max
Units
W
-55
-40
1.56
+150
+150
260
C
C
C
-0.5
-0.5
-6.5
-0.3
-0.5
-0.5
+700
+618
+618
+618
50
+38
+14
50
20
+14
+14
+6.5
Self-limited
6.5
2
V
V
V
V
V/ns
V
V
mA
mA
V
V
V
V
V
V
-0.3
+0.3
V
-65
+65
2
mA
mA
Tamb = 125°C
Continuous
-0.5
-1
-3
-0.5
-0.5
GNDP/GNDS
to GNDD
IHBVS
IFSET
All pins
Human body model
2000
V
All pins
Machine model
200
V
All pins
Charged device model
500
V
NOTES:
1) The device is not guaranteed to function outside of its operating conditions.
2) Exceeding these ratings may damage the device.
3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-to-ambient thermal
resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is
calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature,
causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage.
4) Measured on JESD51-7, 4-layer PCB.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
4
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
ELECTRICAL CHARACTERISTICS
VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed
by characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
High-Voltage Start-Up Current Source (HV)
Breakdown voltage
VHVBR
700
V
Normal charge current
IHVNOR
VHV = 100V, VCC = 15V,
TJ = 25°C
Normal charge current
IHVNOR
VHV = 100V, VCC = 15V
4.5
7
8.9
mA
Supply current when fault occurs
IHVLimit
VHV = 100V, VCC = 0V
0.8
1.4
2.1
mA
Leakage current when turned off
IHVoff
VHV = 400V, VCC = 24V
7
10
µA
20
21.5
23.1
V
10.5
13.9
11.3
15
12.1
16.2
V
V
8.4
9
9.9
V
5.5
7
8.5
mA
IC Power Supply (VCC)
IC turn-on threshold voltage when HV is
detected
UV protection threshold 1
UV protection threshold 2(5)
VCCON(HV)
VCCUVP1
VCCUVP2
VHV > VHVON
LLC operation
LLC disabled
IC release threshold
VCCRST
Operation current at normal
ICC(nor)
RRES =20kΩ
fPFC = 120kHz
fLLC = 200kHz
Start-up current
ICC-start1
VCC = 20V
14
0.55
mA
0.7
mA
Current at fault (LLC fault, PFC operation)(5)
ICC-Disable1
TIMER = 4V
PFC burst
2
mA
Current at fault (LLC fault, PFC fault)(5)
ICC-Disable2
TIMER = 4V
0.5
mA
Vreg
Ireg = 0mA
Ireg = 30mA
Regulated Power Supply (VREG)
Regulated output voltage
11.3
10.8
12
11.8
12.8
12.6
V
V
IC enable threshold
VregON
10.2
10.8
11.5
V
UVP
VregUVP
7.7
8.2
8.8
V
2.95
2.85
3.15
3.1
3.45
3.35
V
V
Power Supply for Digital Core (V3.3)
Voltage regulation range
V3V3
I3V3 = 0mA
I3V3 = 15mA
X-Cap Discharger (HV)
X-cap discharger current(5)
IX-d
X-cap discharger clock time
TX-d
5.5
0.9
1.5
mA
2.4
ms
PFC Gate Driver
Sourcing capacity(5)
Igate_sr
CGate = 1nF
750
mA
Sinking capacity
Igate_sk
CGate = 1nF
Gate-on resistor
Ron(H)
Ron(L)
Voltage fall time
Voltage rise time
(5)
HR1200 Rev 1.1
3/25/2020
-800
mA
Sourcing 20mA
Sinking 20mA
4.5
2.5
Ω
Ω
Tf
CGate = 1nF
10
ns
Tr
CGate = 1nF
15
ns
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
5
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
ELECTRICAL CHARACTERISTICS
(continued)
VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed
by characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
1.245
1.25
1.255
V
Reference Current (RES)
Voltage regulation range
VRT
TJ = 25°C
fosc_nor
At normal
19
MHz
At fault or burst off
1
MHz
System Clock
Clock frequency
fosc_nopwm
AC Input Sensing (ACIN)
Voltage range
KACIN = 0.0032
0
1.6
V
KACIN = 0.0032
0
1.6
V
KACIN = 0.0032
0
1.6
V
RRES = 20kΩ
61
64
µA
PFC Feedback (FBP)
Voltage range
Current Sense (CSP)
Voltage range
Bias current in CSP
Icsp-bias
62.5
ADC for ACIN, FB, and CSP
ADC voltage reference
ADC
TJ = 25°C
resolution(6)
1.593 1.600 1.607
V
10
bits
Acquisition time(6)
350
ns
Integral non-linearity (INL)(6)
±7.0
LSB
Differential non-linearity (DNL)(6)
±4.5
LSB
Offset error(6)
±0.5
LSB
±1.5
LSB
1.593 1.600 1.607
V
7
bits
Integral non-linearity (INL)(6)
±1.5
LSB
Differential non-linearity (DNL)(6)
±0.3
LSB
±0.2
LSB
±1.5
LSB
5
µs
1.593 1.600 1.607
V
10
bits
±4.5
LSB
Differential non-linearity (DNL)(6)
±2.0
LSB
Offset error(6)
±0.5
LSB
±1.5
LSB
Gain
error(6)
DAC for OVP and OCL
Reference voltage
TJ = 25°C
Resolution(6)
Offset
Gain
error(6)
error(6)
Output setting time
(5)
DAC for Set Comparator
Reference voltage
TJ = 25°C
Resolution(6)
Integral non-linearity
Gain
error(6)
HR1200 Rev 1.1
3/25/2020
(INL)(6)
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
6
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
ELECTRICAL CHARACTERISTICS
(continued)
VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed
by characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
60
360
mV
Comparator for Set Signal, OVP, and OCL
Offset voltage
I2C Characteristics (SCL/SDA)(5)
Input high voltage (VIH)
2.1
V
Input low voltage (VIL)
Output low voltage (VOL)
2
I C Timing Characteristics
0.8
V
0.4
V
400
kHz
(5)
Operating frequency range
100
4.7
μs
Holding time
4.0
μs
Repeated start condition setup time
4.7
μs
Stop condition setup time
4.0
μs
Data hold time
0
ns
Data setup time
250
ns
Clock low time out
25
Clock low period
4.7
Clock high period
4.0
Bus free time
Between stop and start
35
ms
μs
50
μs
Clock/Data fall time
300
ns
Clock/Data rise time
1000
ns
High-Side Floating Gate Driver Supply (BST, SW)
BST leakage current
ILKBST
VBST = 600V
10
µA
SW leakage current
ILKSW
VSW = 582V
10
µA
Current Sensing of the Half-Bridge (CSHB)
Frequency shift threshold
VCS-OCR
OCR
0.7
0.77
0.83
V
OCP threshold
VCS-OCP
OCP
1.41
1.48
1.55
V
Current polarity comparator reference
when HSG is on
VCSPR
80
mV
Current polarity comparator reference
when LSG is on
VCSNR
-80
mV
Output Voltage Sense (SO)
Latch protection on SO
VSO-Latch
3.22
3.42
3.6
V
Start-up failure protection on SO
VSO-SFP
1.85
1.96
2.08
V
Pull-up current on SO
ISO-PU
100
nA
Oscillator (FSET, CT)
Output duty cycle
HR1200 Rev 1.1
3/25/2020
D
TJ = 25°C
48
50
52
%
TJ = -40°C to 125°C
47
50
53
%
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
7
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
ELECTRICAL CHARACTERISTICS
(continued)
VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed
by characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Oscillation frequency
Symbol
Condition
Min
Typ
fosc
Max
Units
600
kHz
CT peak value
VCTP
3.54
3.74
3.94
V
CT valley value
VCTV
0.79
0.87
0.95
V
Voltage reference at FSET
VREF
1.88
1.97
2.06
V
tDMIN
Dead time
CHBVS = 5pF
tDMAX
tD_float
Timer for CMP
HBVS floating
240
ns
0.82
1.1
1.38
µs
230
300
390
ns
tD_CMP
50
µs
Voltage clamp
VHBVS-C
7.5
V
Minimum voltage for the change rate to be
detected
dvmin/dt
Half-Bridge Voltage Sensing (HBVS)
Turn-on delay
CHBVS = 5pF, typically
190
V/µs
Td
Slope finish to turn-on
delay
130
ns
Rd
VCS > VCS-OCR
120
Ω
VSS-OCP
VCS > VCS-OCP
Soft-Start Function (SS)
Discharge resistance
Threshold for OCP
1.61
1.72
1.82
V
1.18
1.23
1.28
V
Standby Function (BURST)
Disable threshold
Vth
Hysteresis
Vhys
40
mV
Delayed Shutdown (TIMER)
Charge current
ICHARGE
Charge current for SFP
VTIMER = 1V,
VCS = 0.85V,
SO = 3V
90
ICHARGE_SFP SO < 2.5V
140
180
25
µA
µA
Threshold for forced operation at maximum
frequency
Vth1
1.87
1.97
2.07
V
Shutdown threshold
Vth2
3.25
3.45
3.65
V
Restart threshold
Vth3
0.23
0.29
0.35
V
Low-Side Gate Driver (LSG)
Peak source current(5)
Isourcepk
0.75
A
Peak sink current(5)
Isinkpk
0.87
A
Sourcing resistor
Rsource
4
Ω
Rsink
2
Ω
Fall time
tf
20
ns
Rise time
tr
20
ns
Sinking resistor
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
8
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
ELECTRICAL CHARACTERISTICS
(continued)
VCC = 25V, TJ = -40°C to 125°C, currents entering the IC are positive, min and max are guaranteed
by characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
High-Side Gate Driver (HSG, Referenced to SW)
Peak source current(5)
Isourcepk
0.74
A
Isinkpk
0.87
A
Rsource
4
Ω
Rsink
2
Ω
Fall time
tf
20
ns
Rise time
tr
20
ns
Thermal shutdown threshold
145
°C
Thermal shutdown recovery threshold
100
°C
Peak sink current
(5)
Sourcing resistor
Sinking resistor
Thermal Shutdown
NOTE:
5) Guaranteed by design.
6) Guaranteed by characterization.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
9
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TYPICAL CHARACTERISTICS
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
10
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TYPICAL CHARACTERISTICS (continued)
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
11
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 85V to 265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
12
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 85V to 265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
13
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 85V to 265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
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© 2020 MPS. All Rights Reserved.
14
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
PIN FUNCTIONS
Package
Pin #
Name
1
SDA
I2C data bus. Connect a suitable pull-up resistor from SDA to V3.3.
2
ACIN
Input voltage sensing. ACIN is connected to ADC internally. The voltage is used
for on-time calculation and brown-in/brown-out protection. The ratio of the external
resistor divider should be 0.0032. It is recommended to connect a 680pF capacitor
from ACIN to GNDD.
3
RES
Reference current for producing system clock and bias voltage on CSP. RES
connects to a precise reference voltage of 1.25V internally. The reference current is
produced by connecting a 20kΩ, 0.5% resistor externally from RES to GNDD.
4
CSP
Sensing of the PFC inductor current. Connect a 20kΩ, 0.5% resistor to CS to
produce a bias voltage of 1.25V.
5
GNDD
Ground reference for the digital core of the PFC.
6
GNDP
Ground reference of the PFC gate driver and the LLC low-side gate driver.
7
GATEP
Gate driver output of the PFC MOSFET.
8
VREG
Regulated power supply. VREG provides a regulated power supply for the PFC
and LLC gate drivers or external circuits.
9
LSG
Low-side gate driver of HB. The driver is capable of a minimum 0.7A sourcing
current and a minimum 0.8A peak sinking current to drive the lower MOSFET of the
half-bridge leg. LSG is actively tied to GND during UVLO.
10
TIMER
Setting of protection and recovery time. Connect a capacitor and a resistor from
TIMER to GNDS to set both over-current protection delay and recovery delay.
11
SO
Latch function for OVP and OTP. If the SO voltage exceeds VSO-Latch, the IC stops
switching immediately and remains latched off until VCC drops below VCCRST. When
the LLC is enabled during start-up, if the SO voltage is still below VSO-SFP after the
TIMER voltage reaches Vth2, the IC stops operating. Connect SO and GNDS with a
noise-decoupling capacitor more than 100nF placed as close to the IC as possible.
12
VCC
IC supply power. When the power is on, VCC is charged up by HVCS internally at
first and then by the auxiliary power supply.
13, 18
NC
Not connected. NC is not connected in SOIC28 package and removed in TSSOP28
package to increase creepage distance.
14
HV
High-voltage current source for the IC start-up. HV also acts as an X-cap
discharger when the input voltage drops out.
15
BST
Voltage bootstrap. BST is connected externally to a capacitor to build a power
supply to drive the high-side MOSFET of the HB LLC.
16
HSG
High-side gate driver of HB. HSG is the gate driver output for the high-side
MOSFET of the HB LLC.
17
SW
Reference of the high-side gate driver and bootstrap capacitor.
Description
19
HBVS
Slope sensing to achieve adaptive dead-time adjustment. Detect the dv/dt of the
half-bridge mid-point. A 5pF high-voltage capacitor is recommended between SW
and HBVS. LLC works with fixed dead-time (about 300ns) when HBVS is floating.
Connecting HBVS to GNDS disables the LLC switching.
20
GNDS
Ground reference of LLC and power management circuits.
HR1200 Rev 1.1
3/25/2020
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15
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
PIN FUNCTIONS (continued)
Package
Pin #
Name
Description
Current sense of half-bridge. The LLC current can be sensed by a sense resistor
or a capacitive divider.
CSHB has the following functions:
1. Over-current regulation: As the voltage exceeds the VCS-OCR threshold, the
soft-start capacitor on SS discharges internally. The frequency increases, limiting
the output power. An output short circuit results in a nearly constant peak primary
current. A timer set on ACIN limits the duration of this condition.
21
CSHB
2. Over-current protection: If the current continues to build up (despite the
frequency increase) when the CSHB voltage reaches VCS-OCP, CSS is discharged
continuously, and OCP is not triggered immediately until VSS < VSS-OCP. If the
condition for VCS > VCS-OCP remains once VSS drops below VSS-OCP, the IC shuts
down. CTIMER continues to be charged by an internal 140µA current source until
the TIMER voltage reaches Vth2. The IC resumes operation when the TIMER
voltage falls below Vth3.
3. Capacitive mode protection: The moment LSG is turned off, the CSHB
voltage level is compared with a -80mV CMP threshold. If CSHB > -80mV, it
blocks the HSG gate output until the slope comes down or the CMP timer runs
out. Once HSG is turned off, CSHB is compared with a +80mV CMP threshold. If
CSHB < +80mV, it blocks the LSG gate output until the slope comes up or the
CMP timer runs out. As soon as capacitive mode is detected, the soft-start
capacitor on SS discharges internally and the frequency increases.
All functions are disabled when CSHB is connected to GND.
BURST
Burst mode control. If the voltage on BURST is lower than Vth (1.23V), the IC is
disabled and resumes when the voltage exceeds 1.23V with a hysteresis of about
40mV. During burst mode, soft-start is not activated. This function helps reduce
power loss at a lighter load.
23
FSET
Switching frequency set. Provide a precise and stable VREF (1.97V) reference
voltage. Current flowing out of FSET regulates the LLC switching frequency and
output voltage. The minimum frequency is set via a resistor connected to GND. The
resistor connecting the optocoupler and FSET sets the maximum frequency. An RC
series connected from FSET to GND determines the specific operating frequency.
24
CT
Time set. Current flowing out of FSET is mirrored to charge and discharge the
capacitor connected from CT to GNDS, which determines LLC switching frequency.
25
SS
Soft-start for LLC. Connect an external capacitor from SS to GND and a resistor to
FSET to set both the maximum oscillator frequency and the time constant for the
frequency shift during start-up. An internal switch discharges the capacitor when the
chip is turned off to guarantee soft-start (all protections are listed except CMP).
26
V3.3
A stable 3.3V voltage for digital PFC core or external circuit. A 10µF decoupling
ceramic capacitor is recommended to connect V3.3 and GNDS.
27
FBP
Voltage sensing of PFC output. The voltage of FBP is sampled by ADC. FBP is
also used in on-time calculation, OVP, OLP, and digital PI. A 3.3MΩ pull-down
resistor is connected internally. It is recommended to connect a 680pF capacitor
from FBP to GNDD.
28
SCL
I2C serial clock input. Connect a suitable pull-up resistor from SCL to V3.3.
22
HR1200 Rev 1.1
3/25/2020
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© 2020 MPS. All Rights Reserved.
16
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
BLOCK DIAGRAM
HV
VCC
VREG
BST
IHVNOR=7mA
Vreg
Vcc
Vreg
LDO
Level
Shifter
SW
Vcc
Power Supply Management
Slope
Detection
X-Cap Discharger
GATEP
VULO_3.3V
GNDP
HG
HBVS
Vreg
LDO
GNDS
GNDP
V3.3
LG
V3.3
PWM(3.3V)
LDO
OCP
GNDP
Set/OCL
CCM Off-Time/OCL
V1.8V
100pF
OCR
VCS-OCR
Ibias
DAC
CSP
ACIN
MUX
PFC
Control
Logic
LLC
Control
Logic
ADC
CSHB
OCP
VCS-OCP
100µA
Current Direction
+/-80mV
FBP
LLC_BO/BI (3.3V)
DAC
LLC_Sych (3.3V)
Latch
VSO-Latch
SO
SFP
VSO-SFP
OVP_PFC
SS
OLP_PFC
EEPROM
OSC
RES
Ifmin
SS_Ctrl
VREF
I2C
Ibias
K*Ibias
1.25V
FSET
Pgood
BURST
CCO
Vth
SCL SDA GNDD
GNDS
TIMER
Figure 2: Functional Block Diagram
HR1200 Rev 1.1
3/25/2020
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17
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
FUNCTION DESCRIPTION
Power Supply Management
The HR1200 is a high-performance combo
controller that integrates digital PFC and HB
LLC controllers.
This section describes how the HR1200
produces and optimizes the power supply for
circuits inside the IC. Optimized power source
can reduce no-load consumption and provide
robust operation with sufficient fault protection.
A high-voltage current source is also integrated
in the IC for start-up and X-cap discharge when
the AC input drops out.
EEPROM
The HR1200 applies EEPROM as the NVM. It
has 1k bytes of data memory and 16 bytes of
security memory.
There are only two commands used to operate
the EEPROM:
1.
Read all the data from EEPROM to the
memory map. This process operates
automatically before the controller runs or
receives a RESTORE_USER_ALL command
(51h) from the I2C.
2.
Write all the data from the memory map to
EEPROM. This process operates when it
receives a STORE_USER_ALL command
(50h) from the I2C.
I2C Communication and GUI
The HR1200 has a standard I2C interface. It is
recommended to select an I2C tool with 100kHz
clock frequency. The I2C can read and write the
memory map. It can also send a command to
load the data from EEPROM to memory map or
reload the data from memory map to EEPROM
with the graphic user interface (GUI) (see
Figure 3). For details, please refer to the “User
Guideline_HR1200 I2C Kit and GUI” and “User
Guideline_HR1200 Layout” files available on
the MPS website.
System Functions
This section describes functions that HR1200
integrates to improve system performance,
including X-cap discharge, IC on/off control, a
power good signal, and an interface between
the PFC stage and LLC stage for synchronous
operation.
Digital PFC Controller
The HR1200 uses a digital PFC controller
integrating digital logic, ADC, DAC, and
comparators to achieve PFC functionality. To
acquire programmable design parameters, I2C
communication functions and EEPROM are
also included.
HB LLC Controller
The HB LLC converter can generate an isolated
and regulated output voltage from the high
voltage DC bus. With an adaptive dead-time
control method, the HB LLC controller helps the
converter operate in ZVS in a wider load range,
improving the efficiency of the converter at light
load. The IC implements anti-capacitive mode
operation protection, allowing for robust product
design.
Figure 3: HR1200 I2C GUI
HR1200 Rev 1.1
3/25/2020
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18
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
Part 1: Power Supply Management
The power supply management function is
implemented via four output pins: HV, VCC,
VREG, and V3.3. Figure 4 and Figure 5 show
the block diagram and operation waveforms of
the power management circuit.
LDO
VCC
HV
IHVLimit=1.4mA
IHVNOR=7mA
IHVoff=7uA
X-cap
discharger
Bias
REGULATOR
Ich_max=30mA
Ich_UV=5.0mA
HV Start up
Control
Short
Protection
UVLO(in)
If the start-up current comes from HV when
VCC reaches VCCON(HV), the internal LDO is
powered on. VREG begins building up, and the
IC starts operating if no fault condition occurs.
Then VCC is powered by the auxiliary winding
of the HBC transformer. Once VCC drops
below VCCUVP1, following actions occur:
The IC stops operating, and the PFC
controller stops switching immediately. But
the HB LLC controller continues to operate
until the low-side MOSFET becomes active.
The VREG LDO is disabled.
VREG
CONTROL
1.2V
UVLO
Logic
OFF/ON
VCCON/VCCUVP
Reset
VCCRST
VregON/VregUVP
UVLO(in)
Level
shift
UVLO(3.3V)
Figure 4: Block Diagram of Power Supply
VHV
IHV
40V
Vcc
1.4mA
7mA
7μA
7mA
7μA
7mA
IC Supply Input (VCC)
VCC provides operational power for most of the
internal circuits. Then the IC can start up with
the HV start-up current source.
V3.3
Reset
level VCCON(HV) (21.5V typically). The HV current
source turns on again when VCC drops below
VCCUVP1 (11.3V typically). Once the HV current
source is turned off, the leakage current into HV
should be below IHVoff (7µA typically).
t
7μA
VCCON(HV)
21.5V
VCCUVP1
11.3V
VCCRST
9.5V
9V
The HV current source charges VCC until VCC
reaches VCCON(HV), then VREG LDO is turned on
again. If the IC enters latch mode, the latch
status will remain until VCC falls below VCCRST.
1.2V
t
Vreg
Vreg
11.8V
10.8V
8.2V
VregON
VregUVP
If VCC supplied by an external DC power
source instead of HV current source, please
refer to the HR1201 as an alternative.
t
VUVLO
t
V3.3
t0
t1 t2
t3 t4
t5 t6 t7
t8 t9 t10 t11t12t13
t14
t15
t
Figure 5: Operation Waveforms of Power Supply
High-Voltage Start-Up Input (HV)
A 7mA current source charges VCC internally
when a voltage larger than 40V is applied to HV.
If VCC is lower than 1.2V, the charge current
from HV is limited to IHVLimit (1.4mA typically), to
prevent excessive power loss caused by VCC
short circuit during start-up.
During normal operation, the voltage on VCC
rises quickly after start-up, and the HV current
source switches to the nominal current IHVNOR
(7mA typically). IHVNOR charges the capacitor
connected to VCC externally, and VCC voltage
ramps up. The HV current source is switched
off when VCC voltage exceeds the start-up
HR1200 Rev 1.1
3/25/2020
Regulated Output (VREG)
An internal LDO is added to stabilize voltage in
order to:
Supply the internal PFC driver.
Supply the internal low-side driver of HB LLC.
Supply the internal high-side driver of HB LLC
via a bootstrap diode.
Supply a reference voltage.
The LDO is enabled only when VCC is higher
than VCCON(HV). This ensures that any optional
external circuitry connected to VREG does not
dissipate any of the start-up current.
The IC starts switching only when VREG is
higher than VregON (10.8V typically). If VREG
falls below VregUVP (8.2V typically), the IC and
the PFC controller stop switching immediately.
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19
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
The HB LLC controller continues operating until
the low-side MOSFET becomes active.
V3.3 for Digital Logic
V3.3 is a stabilized power supply for the internal
digital logic. It is the output of an LDO with its
input connected to VCC internally. The output
of V3.3 is connected to a digital section with an
internal bonding wire. When VCC is larger than
VCCRST plus a hysteresis of about 0.5V, the V3.3
LDO is enabled. It can be disabled only when
VCC is lower than VCCRST.
The capacitor on V3.3 should be in the range of
4.7µF to 10µF to guarantee that V3.3 is stable.
Out from the 3.3V LDO, there is another LDO
with 1.8V output downstream for powering the
internal digital circuits.
consumption is reduced significantly. Once the
AC voltage is disconnected, after a detection
time window (Timer 1, 96ms typically), the IC
controls the internal 7mA current source
automatically to discharge energy from the Xcap to VCC within the Timer 3 period (48ms
typically). The IC stops for an additional Timer 3
period to detect the AC. If no AC is re-applied
during this last time period, the IC continues
discharging during the Timer 2 period (144ms
typically) until VHV is below 35V. Once VHV drops
below 35V, VCC is discharged quickly by the
internal current source, which speeds up
recovery when the IC is in latch mode.
AC remove
VHV
Detect whether input re-plug to AC line
Unplug
Detection
The UVLO (3.3V signal) is an enable signal for
both the digital PFC and LLC controller. When
VCC is larger than VCCUVP1, and VREG is larger
than VregON, UVLO (3.3V signal) goes high.
Discharge
Discharge
UVLO (3.3V signal)
Discharge
35V
IHV
Timer 1
Timer3Timer3 Timer2
t
Timer3 Timer2
t
Disch_en
Part 2: System Functions
X-Cap Discharger
X-caps are critical components placed at the
input terminals of the power supply to filter out
differential mode EMI noise. If the AC line
voltage is removed, the redundant voltage on
X-caps may cause harm to the user. Safety
standards require the voltage to be discharged
to a safe level within a certain time frame.
Commonly, resistors are placed in parallel with
X-caps across the AC line to provide a
discharge path. However, extra resistors bring
continuous power consumption as long as the
AC input is connected, which is the significant
contributor to power consumption at no-load or
standby conditions.
The HV current source in the HR1200 acts as a
smart X-cap discharger when the AC input is
removed. So, traditional discharge resistors can
be eliminated. Operating waveforms are shown
in Figure 6.
In a normal stage, the HV current source is off.
The leakage current in HV is small, so power
HR1200 Rev 1.1
3/25/2020
VCC
VCCON
VCCXCD
21.5V
VCCRST
t
9V
Vreg
t
Driving
Signal
t
t0 t'0
t1
t2
t3
t4 t5 t6
t7
t8 t9 t10
t
Figure 6: Operating Waveforms of X-Cap
Discharger when AC Removed
If the AC recovers in HV again during the Timer
3 period, a new start-up procedure begins (see
Figure 7).
If the X-cap discharge function is enabled, VCC
should be regulated between VCCON and VCCXCD
to avoid over-stressing VCC.
The X-cap discharge function is very flexible,
and allows users to choose an X-cap value to
optimize differential mode EMI filtering without
worrying about the effect of the required bleed
resistors on the standby power budget and
system no-load.
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20
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
The IC can be disabled by programming the
EEPROM through the I2C GUI (see Table 1).
AC remove
VHV
Unplug
Detection
Table 1: IC Disabled through I2C and MPS’ GUI
Discharge
IHV
Timer1
Timer3
t
Timer3
t
Disch_en
VCC
t
VCCON
VCCXCD
21.5V
t
Vreg
t
t0 t'0
t1
t
t4 t5
t2 t3
Figure 7: Operating Waveform of X-Cap
Discharger when AC Recovered
Over-Temperature Protection (OTP)
Once the internal thermal sensor senses the IC
temperature is over 145°C, the IC stops
switching immediately. Both the LDO for VREG
and V3.3 are disabled. If the IC temperature
rises above 100°C, the high-voltage current
source is disabled. The IC is enabled again
when VCC drops below VCCRST. If the IC
temperature drops below 100°C, the IC starts
up again.
IC On/Off Control
The IC is turned off by pulling FBP down to
GND with an external MOSFET (see Figure 8).
If the FB voltage is less than 0.2V, both the
PFC and LLC disable the PWM switching
during startup or operation. When the FBP
voltage is higher than 0.3V, the IC is turned on
again. Besides, the IC can be turned off from
the secondary side through an optocoupler.
ad_channel
ACIN
2
adc_rdy
12
There are two signals between the PFC and the
LLC part:
1. D2D brown-in/out signal (see Figure 9)
Driving
Signal
ad_result
PFC and LLC Interface
MUX
ADC
A0
Filter
A1
Filter
A2
Filter
FBP
ad_clk
adc_soc
Vout
CSP
If the output voltage is higher than VD2D_BI, the
D2D_BI/BO signal is set high, enabling the LLC
stage. The LLC stage is disabled when the
output voltage drops below VD2D_BO. This
function guarantees the LLC operates within a
proper input voltage range, preventing the LLC
from running in capacitive mode.
VD2D_BI and VD2D_BO are programmable through
I2C. The register address for VD2D_BI is one word
(16h, 17h). The register address for VD2D_BO is
one word (18h, 19h). The value in the register
can be calculated with Equation (1):
1023
DEC2HEX VD2D_BI/BO 0.0032
1.6
(1)
2. LLC burst synchronize signal
When the LLC operates in burst mode, the PFC
burst mode can be synchronized with the LLC
burst mode. This is achieved by setting bit 7 of
register 56h high. When bit 7 is low, the LLC
and PFC burst independently.
Part 3: PFC Controller
The state-of-the-art CCM/DCM control scheme
can reduce the RMS current drawn from the AC
mains by ensuring good shape of the input
current both in CCM and DCM. The control
scheme reduces the switching frequency when
the load is reduced, therefore achieving higher
efficiency and higher power factor at light load.
On/Off
Digital PFC Timing
Figure 8: IC On/Off Control
HR1200 Rev 1.1
3/25/2020
Figure 9 shows the timing of the digital PFC
block.
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21
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
Vrec
Vout_target
VD2D_BI
VD2D_BO
Vout
t
VACIN
mirrored and flows out of CSP. If CSP is also
connected externally to a 20kΩ resistor, a bias
voltage of 1.25V on CSP is produced, which
keeps the CSP voltage positive (see Figure 11).
VIN_BI
VIN_BO
Clock
t
V3.3
Iosc=K*Iref
OSC
t
V1.8
Iref=62.5μA
t
1.25V
Vosc
Ibias=Iref
t
rst
CSP
Enable
RCSP
t
IL
AC_BI/BO
t
Figure 10: Reference Current
GATEP
t
D2D_BI/BO
t0
t1
t2 t3
t4
RRES=20kΩ
Rbias=20kΩ
OCP
t
20μs
UVLO(3.3V)
RES
t5
t6
t
Figure 9: Power Supply Sequence of Digital
Controller
Moreover, the reference current is mirrored to
produce a system clock (see Figure 11).
Iref=62.5μA
1.25V
Ich=K*Iref
Timing of the Power Supply
Once VCC rises above VCCRST plus a hysteresis
of about 0.5V, the V3.3 LDO is enabled and an
internal LDO downstream produces a stable
1.8V power supply for the internal digital logic
and system clocks. The rst signal is set high
when both 3.3V and 1.8V are stable. When
UVLO (3.3V signal) is validated, the IC enables
OSC, ADC, DAC, and relative comparators.
The enable signal is set high after a delay of
20µs, which indicates the digital core is ready to
begin operation.
Timing of the Digital Core
If the enable signal is high, ADC begins
sampling VACIN and VFBP. If the AC input meets
the brown-in condition and no open-loop fault is
found on FBP, the AC_BI/BO signal is set high.
The PFC soft starts until the output reaches the
target value. While the PFC output voltage
ramps up above VD2D-BI, D2D_BI/BO is set high.
the downstream LLC starts operating.
Reference Current (RES)
RES is connected internally to a precise
reference voltage of 1.25V (see Figure 10).
RES should be connected to a 20kΩ, 0.5%
resistor externally. Reference current about
62.5µA is then generated. The current is
HR1200 Rev 1.1
3/25/2020
RES
Vref
S
Q
Clock
Cch2
R
Cch1
RRES=20kΩ
Delay
Clock_Select:
‘1’: Clock=20MHz
‘0’: Clock=1MHz
Figure 11: System Clock Generator
The system clock switches from 20MHz to
1MHz when PWM is disabled (i.e. burst off,
OVP, OCP, etc.) in order to reduce IC power
consumption.
Input Voltage Sensing
The input voltage is rectified and attenuated by
a resistor divider with a fixed ratio (0.0032)
before provided to the ACIN input. Then, the
ADC samples the voltage on ACIN including the
instantaneous value, the peak value, and the
frequency of the input voltage. The data are
used for on-time calculation, AC brown-in/out
protection, capacitor current compensation and
X-cap discharge.
Figure 12 shows the input voltage level defined
for different functions. All parameters can be
programmed through the I2C Kit and MPS’ GUI.
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22
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VACIN
1.6V
256
DEC2HEX VIN_High/Low 0.0032
1 .6
VINMAX=500V
Output Voltage Sensing
VIN_Level1 [Reg: 4Fh]
Normal
operation
range
Similar to input voltage sensing, the output
voltage is attenuated by a resistor divider
before connected to FBP. Then the voltage on
FBP is sampled by ADC. The results are used
for on-time calculation and a series of
protections.
VIN_High/Low [Reg: 05h]
VIN_Level2
[Reg: 50h]
VIN_BI [Reg: 39h 38h]
VIN_BO [Reg: 3Bh 3Ah]
Figure 12: Input Voltage Level for Different
Functions
Input Brown-In/Brown-Out
If VACIN is larger than the brown-in threshold
(VIN_BI), it means the IC is ready to switch. If
VACIN is less than the brown-out threshold
(VIN_BO) for the length of one timer period, the IC
stops switching. VIN_BI and VIN_BO are 10-bit
values that are stored in the registers from 38h
to 3Bh. The values can be calculated with
Equation (2):
1023
DEC2HEX VIN_BI/BO 0.0032
1 .6
(2)
The brown-in and brown-out timer is set in
register 3Ch (see Table 2).
The internal pull down resistor of 3.3MΩ should
be considered when designing the external
resistors. Make the total divided ratio to 0.0032
according to Equation (4):
RFBL L // 3.3M
0.0032
RFBL H ( RFBL L // 3.3M )
Item
VIN_BI_TIME
VIN_BO_TIME
Description
Brown-in time
Brown-out time
Figure 13 shows the output voltage level that is
defined for different functions. All parameters
can be programmed through the I2C GUI.
VFB
1.6V
VIN_Level1, VIN_High/Low and VIN_Level2 separate the
input voltage into four ranges to achieve
different compensation values to improve PF at
different input voltage ranges.
The thresholds are 8-bit data. The value can be
set according to Equation (3):
HR1200 Rev 1.1
3/25/2020
VOUTMAX=500V
VOUT_Highline_OVP [Reg: 48h]
VOUT_Lowline_OVP [Reg: 49h]
Normal
operation
range
High/Low Line
The low line is determined when the input
voltage is lower than VIN_High/Low. The high line is
determined when the input voltage is larger
than VIN_High/Low plus a hysteresis of about 10V.
The high/low-line signal sets the soft-start time
and the resonant time for valley turn-on. It also
regulates the output voltage at different levels
to optimize the efficiency of the PFC stage.
(4)
Where RFBL-H is the divider resistor connected
on high-side and RFBL-L is the divider resistor
connect on low-side.
Table 2: Brown-In/Out Timer in Register 3Ch
Bit
7:4
3:0
(3)
VOUT_Highline_nor
VOUT_Lowline_nor
VOUT_Highline_set1
VOUT_Lowline_set1
VOUT_Highline_set2
VOUT_Lowline_set2
VOUT_Highline_set3
VOUT_Lowline_set3
[Reg: 02h 01h]
[Reg: 04h 03h]
[Reg: 11h 0Eh]
[Reg: 15h 12h]
[Reg: 11h 0Fh]
[Reg: 15h 13h]
[Reg: 11h 10h]
[Reg: 15h 14h]
VOUT_FastLoop
VOUT_OLP_Recovery=90V
VOUT_OLP=60V
Figure 13: Output Voltage Level for Different
Functions
Output Regulation
To optimize efficiency, the output voltage can
be auto-regulated according to the input voltage
and output power. The output voltage is divided
into two ranges by VIN_High/Low and is divided into
four ranges according to the output power level,
which can be programmed by registers from
06h to 0Bh. Therefore, the IC can auto-regulate
eight output voltages accordingly.
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
open loop is achieved by software and the
value is fixed.
Output Fast OVP
VOUT_Highline_OVP and VOUT_Lowline_OVP are 7-bit
values stored in register 48h and 49h. They are
programmable through the I2C GUI (430V
typically). A 7-bit DAC converts VOUT_OVP to an
analog signal and compares the result with FBP
voltage. If output voltage is larger than VOUT_OVP,
the PFC stops switching. Once output voltage
decreases to regulation voltage, the PFC
resumes switching. Figure 14 shows the OVP
circuit.
VOUT_OVP(n)
DAC
Peak Current Sensing
The PFC inductor current is sensed by RCSP
and produces a negative voltage. A precise
current source (Ibias) exits CSP and produces a
positive bias voltage on Rbias (see Figure 16).
The CSP voltage is calculated with Equation (5):
VCSP ( t) VCSP_Bias ( t) VCS ( t)
COMP
VFBP(t)
Blanking
Time
PWM(3.3V)
VCS
IL
VOUT_OVP(t)
Rcsp
OVP_enable
VCSP_Bias
Rbias
CSP
PWM
OCP
OC2
OCP_disable
S
OC1
Ibias
R
OCP_disable
Q
Latch
Figure 14: OVP Circuit
A blanking time is inserted in OVP, keeping the
IC immune to switching noise interference (see
Figure 15). Both of TOVP_T and TOVP_R are
programmable in register 60h.
(5)
Q
OCP_trig
OCP_release
OCL_trig
A
path
DAC
IOCL(n)
IOCL(t)
OCL
Digital
Core
SET
DAC
Iref_off(n)
VFBP
Iref_off(t)
430V
400V
OVP trigger
2pF
OVP recovery
TOVP_T
OVP_enable
TOVP_R
10pF
10MΩ
ACIN
OVP Effective time
32kΩ
4kΩ
50pF
MUX
Figure 15: Output Fast OVP
10MΩ
Fast Loop
FBP
32kΩ
In a dynamic load event, the PFC output
voltage decreases due to the low bandwidth of
the voltage control loop, which may cause the
output voltage to fall out of the regulated range.
Fast loop is activated when the output voltage
is lower than VOUT_FastLoop. Then Ki and Kp of the
digital PI are changed with X times the normal
value, depending on the GUI setting. In this way,
the output voltage of the PFC is regulated faster
in the dynamic load event.
B path
ADC
4kΩ
50pF
Figure 16: Current Sense Circuit in CSP
Overall, the CSP voltage is positive (see Figure
17). The ADC samples VCSP_Bias (1.25V typically)
regularly.
Open Loop or IC Disable Condition
If the FBP voltage is less then VOUT_OLP (60V
typically), it is considered to be an open-loop or
IC disable condition. The IC does not work and
PWM switching is disabled during operation.
The IC restarts only when the FBP voltage is
larger than VOUT_OLP_Recovery (90V typically). The
HR1200 Rev 1.1
3/25/2020
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VCSP
Sampling
PWM
VCSP_Bias
1.25V
VCSP
0V
VI-OCP =0V
VI-OCL
t
IL
OC1
OCP_blanking
TOCP_blanking
OCP_disable
OC2
Q
IL_max
IL_limit
Q
OCP_release
t
Figure 17: Voltage Waveform in CSP
Over-Current Protection (OCP)
If the CSP voltage is less than zero, overcurrent protection is enabled. The PFC stops
switching immediately, and OCP_trig is set high
simultaneously. The digital core detects this
status and disables the PWM. OCP can be
released by the OCP_release signal.
The OCP function is disabled by setting bit 3 of
register 45h to logic low. The OCP behavior
mode can be programmed by setting bit 2 to bit
0 of register 45h. It can be hiccup, latch or autorestart with a delay time. The default setting is
hiccup. The delay time is set in register 46h.
A programmable LEB1 (TOCP_blanking) of about
200ns is implemented to avoid error sensing
due to switching noise.
Figure 18: OCP Operation Waveform
Over-Current Limit (OCL)
The inductor current exists a cycle-by-cycle limit
by setting the appropriate RCSP and VI-OCL. VI-OCL
can be programmed in register 44h, and it can
be converted to an analog signal by a 7-bit DAC.
A programmable LEB1 (TOCL_blanking) of about
200ns is inserted to avoid switching noise if the
digital core is turned on (similar to TOCP_blanking).
Digital PFC Control Scheme
Figure 19 shows the flowchart of the digital PFC
control scheme.
Digital Current Reference
The digital PI compensates for the voltage loop.
Its output Vcomp(n) is sent to the multiplier for
current reference calculation (see Figure 20).
The OCP function can avoid over-stressing
when the inductor is shorted, or when the
current is too large.
Figure 18 shows the operating waveforms of
the OCP function.
HR1200 Rev 1.1
3/25/2020
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
where TS is the switching period, programmable
in registers from 1Eh to 22h.
Start
ADC
On-Time
Calculation
Mode Decision
The HR1200 has three operation modes:
continuous conduction mode (CCM), variable
frequency discontinuous conduction mode (VFDCM), and constant frequency discontinuous
conduction mode (CF-DCM).
Sensing Ipk
The peak value of the inductor current in CCM
should satisfy Inequality (8):
Sensing Vin, Vo
Digital
Voltage Loop
Current Reference
Iref Calculation
Ipk (n) 2 Iref (n)
Mode
Determination
The peak value of the inductor current in VFDCM should satisfy Inequality (9):
CF_DCM
VF_DCM
CCM
2 Iref (n) Ipk (n) 2 Iref (n)
DAC Input:
Off_cur_ref(n)=0
DAC Input:
Off_cur_ref(n)=0
DAC Input:
Off_cur_ref(n)
(8)
Reduce On-Time
Calculation
VF_DCM
Off-Time
Ipk (n) 2 Iref (n)
Ts_max
(10)
Ts
where Ts_max is the maximum switching period,
programmable in registers from 23h to 27h.
Valley Turn On
1. CCM Operation
End
IL
Ipk
Iref
Figure 19: Flowchart of PFC Control Scheme
Vin(n)
Vo(n)
Vo_ref(n)
off_cur_ref
Vin_avg(n)
SET
-
Kp s Ki
+
Vcomp(n)
Vin
s
Digital PI
Vcomp
Vin_avg
2
Iref(n)
Vcomp (n)
(0.5 Vin_pk (n))2
(6)
On-Time Calculation
The on-time can be calculated with Equation (7):
HR1200 Rev 1.1
3/25/2020
n
n+1
Vo_ref Vin (n)
Vo_ref
Ts
(7)
t
t
PWM
ton
Ts
The digital current reference can be calculated
with Equation (6):
Ton (n)
n-1
Digital Multiplier
Figure 20: Current Reference
Iref (n) Vin (n)
(9)
Ts
The peak value of the inductor current in CFDCM should satisfy Inequality (10):
CF_DCM
Off Time
CCM Off Time
Ts_max
t
Figure 21: CCM Control Signals
When the converter operates in CCM, the
off_cur_ref(n) is calculated and sent to DAC.
The output of the DAC is an analog signal
off_cur_ref(t) and is compared with VCS(t). If
VCS(t) is lower than off_cur_ref(t), the signal will
be set high. The PWM signal is set high
accordingly (see Figure 21).
The off current reference at CCM can be
calculated with Equation (11):
off_cur_re f(n) 2 Iref (n) Ipk (n)
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(11)
26
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
2. VF-DCM Operation
When the converter operates in VF-DCM, the
off current reference is set to zero. In this case,
the set signal represents the boundary of DCM
(see Figure 22).
IL
Iref
PWM
n-1
n
Ipk (n) Ipk (n)
(15)
The new turn-on time can be calculated with
Equation (16):
Ipk
SET
As ton changes minimally, the peak value of
inductor current can be seen as unchanged.
See Equation (15):
off_cur_ref
t
n+1
t
V
Vin (n)
t on (n) o_ref
Ts (n)
Vo_ref
(16)
The delay time is calculated with Equation (17):
ton
Ts
t
td
2 I (n)
Ts_max
t d (n) Ts_max Ts (n) 1 ref
Ipk (n)
Ts_new
(17)
Figure 22: VF-DCM Control Signals
The new switching period is calculated with
Equation (12):
Ts_new (n)
Ipk (n)
2 Iref (n)
Ts
(12)
Soft Start (SS)
Once the AC input voltage is larger than VIN_BI,
the Vin_ok signal pulls high, and the HR1200
initiates a soft-start sequence (see Figure 24).
Vo_target
The delay time is calculated with Equation (13):
I (n)
t d (n) Ts_new (n) Ts pk
1 Ts
2 Iref (n)
Vo_start
Vout
(13)
Vin
3. CF-DCM Operation
When the converter operates in CF-DCM, the
off current reference is set to zero. In this mode,
the switching frequency is limited to the
minimum switching frequency (see Figure 23).
IL
Iref
PWM
td'
ton'
T s'
n-1
n
ton
Ts
off_cur_ref
t
n+1
t
td
t
Ts_max
The PWM duty is modulated to achieve
average current control. The new switching
period is calculated with Equation (14):
HR1200 Rev 1.1
3/25/2020
Tss
The output voltage rises from the rectified
output voltage to the target value. When
softstart_flag is set high, the soft-start sequence
is completed.
The soft-start time can be calculated with
Equation (18):
Tss ( Vo_target Vo_start )
Figure 23: CF-DCM Control Signals
2 I (n)
Ts (n) ref
Ts_max
Ipk (n)
PWM
softstart_flag
Figure 24: Soft-Start Sequence
Ipk
SET
Vin_ok
(14)
2bit_num 1
slewrate
Vadc_ref
(18)
where Vo_target is the target value of the output
voltage, Vo_start is the soft-start value of the
output voltage, bit_num is the ADC data bit (12
typically), Vadc_ref is the reference voltage of
ADC (1.6V typically).
The slew rate is different at high line and low
line. The slew rate at high line is programmable
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
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in register 1Ch; the slew rate at the low line is
programmable in register 1Dh.
Burst-Mode Operation
At light load, the IC is always designed to run in
burst mode for better efficiency or less no-load
power consumption. Once the output load is
lower than the threshold (e.g. 3% rated load),
the PFC enters burst mode. The threshold can
be programmed in register 2Dh for high line and
register 2Fh for low line. In burst mode, the
switching duty is calculated based on the 3%
rated load. The output is regulated to Vo_target
with a 5V hysteresis. The PFC keeps switching
when the output voltage is below Vo_target-5V.
The PFC stops switching when the output
voltage ramps up to Vo_target.
Burst-mode operation is synchronized with the
LLC_sync signal. If the LLC_sync signal is high,
the PFC PWM switching is turned off. Once the
output voltage is lower than Vo_target-5V, the
PFC is turned on again even if the LLC_sync
signal is high. This status continues until the
output voltage ramps up to Vo_target.
When the PFC recovers from burst mode, it
operates in critical conduction mode (CRM) for
the first five switching cycles.
Capacitor Current Compensation
Traditional PFC control schemes only regulate
the inductor current to match the shape of the
input voltage. However, the input capacitor
current is not controlled which may cause PF
deterioration and undesired delay. With a larger
capacitor or a higher input voltage, the PF even
worsens.
To improve the PF, the HR1200 implements a
patented method to compensate for PF
deterioration. Relevant data are stored in
registers from 4Bh to 4Eh, corresponding to
different input voltage levels. With this function,
the PF is improved at all input voltage levels.
frequency.
Vin
Vinpk
20V
t
fsw
fsw_max
fsw_nor
fsw_min
Tm(fm)
t
Figure 25: Frequency Jittering
The parameters of fsw_max, fsw_min, and fm can be
programmed by the I2C GUI for the best EMI
performance.
Part 4: LLC Controller
Oscillator (FSET)
Figure 26 shows the block diagram of the
oscillator. A modulated current charges and
discharges the capacitor on CT. The voltage on
the capacitor swings between the peak
threshold and the valley threshold to determine
the oscillator frequency.
The source current of FSET controls the current
source IS-1 to charge the CT capacitor. Here,
the current mirror ratio inside the HR1200 is
1A/A. When an oscillating cycle starts, IS-1
charges the CT capacitor until the voltage
triggers the peak threshold voltage. The
discharge current source IS-2 which is twice the
source current of FSET is then turned on.
Therefore, the CT capacitor is discharged with
the source current of FSET. When the voltage
on the CT capacitor drops to the valley
threshold voltage, the IS-2 is turned off, and a
new oscillating cycle repeats.
SS
VREF
Frequency Jittering
In order to reduce the EMI noise, the switching
frequency is designed to be modulated by a
triangular waveform with the frequency of fm.
The switching frequency is modulated to the
maximum value at the peak of the triangle and
to the minimum value at its valley. Figure 25
shows the algorithm modulating the switching
HR1200 Rev 1.1
3/25/2020
FSET
Rfmin
Rss
Rfmax
Is-1
Iset
VCTV
Css
Iset
S
Q
GNDS
VCTP
CT
2Iset
Is-2
R
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
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Figure 26: Oscillator Block Diagram
When VCC reaches the turn-on threshold,
VREG starts to ramp up. As soon as VREG
exceeds VregON, CT begins to be charged and
LSG switches on first. When CT ramps up to
VCTP, LSG switches off and CT holds for a
period of dead time. Once the dead time
expires, CT drops down and HSG switches on.
HSG keeps working until CT drops down below
VCTV, HSG is turned off. A full switching cycle
repeats unless VCC is lower than VCCUVP.
Figure 27 shows the detailed CT waveform
from start-up to steady state.
fs
1
3 CT RFSET
(19)
where RFSET represents the total equivalent
resistor on FSET.
The minimum and maximum frequency can be
calculated with Equation (20) and Equation (21):
1
3 CT Rfmin
(20)
1
3 CT (Rfmin || Rfmax )
(21)
fmin
fmax
The values of Rfmin and Rfmax can be extracted:
Vcc
VCCON
VCCUVP
t
Vreg
VregON
VregUVP
CT
VCTP
t
1
3 CT fmin
(22)
Rfmax
Rfmin
fmax
1
fmin
(23)
ADTA
VCTV
t
HSG
t
LSG
Ts
t
Figure 27: CT Waveform from Start-Up to
Steady State
The RC network connected externally to FSET
determines the switching frequency and the
soft-start switching frequency.
Rfmin connected from FSET to GND contributes
to the maximum resistance of the external RC
network when the phototransistor is blocked.
Therefore, it sets the minimum source current
from FSET, which determines the minimum
switching frequency.
Under normal operation, the phototransistor
controls the current through Rfmax to modulate
the frequency for output voltage regulation.
When the phototransistor is saturated, the
current through Rfmax is at its maximum, thus
setting the maximum switching frequency.
An RC tank connected in series between FSET
and GND is used to shift the frequency during
start-up (see the “Soft Start” section for details).
The operation period can be expressed with
Equation (19):
HR1200 Rev 1.1
3/25/2020
Rfmin
Soft Start (SS)
For the resonant half-bridge converter, the
power delivered is inversely proportional to the
switching frequency. To ensure the converter
starts or restarts safely, the soft-start function
sets the switching frequency at a high value
until the value is controlled by the closed loop.
The soft-start can be easily achieved using an
external RC series circuit.
At the beginning of the start-up sequence, the
SS voltage is 0V. The soft-start resistor RSS is in
parallel with Rfmin. So Rfmin and RSS determine
the initial frequency:
fstart
1
3 CT (Rfmin || Rss )
(24)
During start-up, CSS is charged until its voltage
reaches the reference VREF, and the current
flowing through RSS drops to zero. This period
takes about 5RSSCSS. During this period, the
switching frequency changes following an
exponential curve. Initially, the CSS charging
process decays relatively quickly, but the rate
slows progressively. After this period, the output
voltage is still not close to the setting value, so
the feedback loop takes over after start-up.
With a soft-start function, the input current
increases gradually until the output voltage
reaches the setting point with little overshoot.
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
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The parameters of the soft-start RC network
can be chosen according to Equation (25) and
Equation (26):
the differential current elapses accordingly.
HBVS starts to ramp up. LSG switches on after
a minimum dead-time.
Rfmin
The duration from the time HSG switches off to
the time LSG switches on is defined as the
dead time. It relies on the completion of SW’s
transition.
R ss
Css
fstart
1
fmin
3 10-3
Rss
(25)
(26)
Select the initial frequency fstart at least four
times the minimum value fmin. When selecting
CSS, there is a trade-off between the desired
soft-start operation and the OCP speed.
Adaptive Dead-Time Adjustment (HBVS)
The dead-time period between HSG and LSG
drivers is always needed in half-bridge
topologies in order to prevent any crossconduction through the power stage MOSFETs,
which may result in excessive current, high EMI
noise and destructions in practical applications.
Traditional fixed dead-time control scheme is
often used in resonant converters as it is simple
to implement. However, this method can cause
hard switching in light load or large Lm design
condition which eventually leads to thermal and
reliability issues.
The HR1200 incorporates an intelligent ADTA
logic circuit, which is capable of detecting the
dv/dt of SW and automatically inserting a
proper dead-time with respect to the actual
operating conditions of the converter. To
achieve this, a 5pF high-voltage capacitor is
recommended between SW and HBVS. With
ADTA, the MOSFET body diode conduction
time can be minimized which enables the LLC
converter to achieve high efficiency from light
load to full load due to ZVS. Moreover, the
design of thermal management and Lm of the
transformer can be easier. Figure 28 shows the
simplified block diagram of ADTA.
When LSG switches off, SW swings from zero
to high, creating a positive differential current
via CHBVS. The dead time adjusts automatically
to current information.
To avoid damaging HBVS, the differential
current should not be higher than 65mA.
Otherwise, a smaller value for CHBVS must be
selected to meet Inequality (27):
id CHBVS
dV
65mA
dt
(27)
However, if the value for CHBVS is too small to
detect dv/dt, the minimum voltage change rate
dvmin/dt is taken into account to choose an
appropriate CHBVS.
First, calculate the peak magnetizing current Im
according to Equation (28):
Im
Vin
8 Lm fmax
(28)
Then CHBVS can be designed:
CHBVS
950 μA Coss
Im
2
(29)
where Coss is the output capacitance of the
power stage MOSFET when Vds equals zero.
For a typical design, Lm=870µH, Vin=450Vdc,
and fmax=140kHz. Based on calculation results,
CHBVS should be larger than 4.5pF. So 5pF is
selected, typically fit for most MOSFETs.
Once HSG switches off, SW begins swinging
from a high voltage to a low voltage due to the
resonant tank current Ir. A negative dv/dt draws
a current from HBVS via CHBVS. HBVS is pulled
down depending on dv/dt and CHBVS. If the
differential current is higher than the internal
comparator current, HBVS will be pulled down
to zero and clamped. When SW stops slewing,
HR1200 Rev 1.1
3/25/2020
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
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Vbus
HSG Driver
HG
HSG
CBOOT
SW
Lr
LG
ADTA
Logic
LG
CLK
tDMAX
t
t
Vgate
LSG
CHBVS
LSG
HSG
LSG
HSG
t
VSW
Cr
GNDP
HG
tDMIN
VCLK
Vreg
LSG Driver
tDMIN
Vosc
BST
id
HBVS
t
VDT
CLKN
t0 t1 t2
t3 t4 t5
t6
t
t7
Figure 28: Block Diagram of ADTA
Figure 30: Dead Time in ADTA
Figure 29 shows the operation waveform of
ADTA. Figure 30 illustrates the possible dead
time with ADTA logic. There are three kinds of
possible dead time: minimum dead time tDMIN
(240ns typically), maximum dead time tDMAX
(1.1µs typically), and adjusted dead time
(between tDMIN and tDMAX). When the transition
time of SW is smaller than tDMIN, the logic
prevents the gate from providing output until
tDMIN is reached. This can avoid any shootthrough of the high-side and low-side MOSFET.
If the dead time is too long, it may lead to duty
cycle loss and loss of soft switching. So a
maximum dead time tDMAX is set forcing the gate
to switch on.
If HBVS is shorted to GND, LLC stops switching.
If HBVS is floating, the internal circuit cannot
detect the differential current in HBVS, and the
fixed dead time (300ns) takes effect.
Capacitive Mode Protection (CMP, CSHB)
In fault conditions such as over-load or shortcircuit condition, the converter may run into the
capacitive region. In capacitive mode, the
voltage applied to the resonant tank is lagging
off the current. The body diode of one of the
MOSFETs switches on. So, to avoid device
damage, the switching of the other MOSFET
should be blocked. The functional block
diagram of CMP is shown in Figure 31.
Vbus
BST
Dead time adaptively
adjusted
HSG Driver
VREF
LSG
HSG
HSG
HG
FSET
Iset
t
LSG Driver
LG
Discharge:
SW
Lr
LSG
OCR/OCP, CMP, Restart
GNDP
t
Q
VSW
Capacitive
Detected
Maximum
Frequency
140μA
TIMER
t
Shut Down
Vth2
Q
CMP
Control
Logic
SET
D
Cr
-80mV
CLK
CLR
CSHB
Q
Vth1
Protection
Timer
VHBVS
CBOOT
VREG
SS
im
HSG
Q
SET
CLR
D
80mV
CLK
OCR
VCS-OCR
Restart
Vth3
OCP
VCS-OCP
tDMIN
Figure 31: CMP and OCP Block Diagram
t
IHBVS
id
t
CLK
Figure 32 shows the operating principle of
capacitive mode protection. CSPOS and
CSNEG stand for the current polarity, which is
generated by comparing the voltage of CS with
internal +80mV and -80mV voltage reference.
t
Figure 29: Operation Waveform of ADTA
HR1200 Rev 1.1
3/25/2020
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31
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
tDMIN
Vosc
Timer out
tDMIN
tDMAX
t
VCLK
t
Vgate
LSG
HSG
LSG
VSW
HSG
HSG
t
Slope Missing
t
VCSHB
80mV
-80mV
t
CSNEG
t
CSPOS
50μs
t0
t1
t2
t3
t4
t5
The HR1200 provides two levels of over-current
protection (see Figure 33).
1. Over-Current Regulation
t
The first level of protection occurs when the
voltage on CSHB exceeds VCS-OCR (0.77V).
Following actions will take place:
t
Figure 32: Operating Principle of CMP
At t0, the low-side gate driver switches off for
the first time. CSNEG is high, which means the
current is at the right polarity, so the converter
is operating in inductive mode. The capacitive
mode protection circuit is not active.
At t1, the high-side gate driver switches off for
the first time. CSPOS is high, so the current is
at the right polarity, and the converter operates
in inductive mode. The capacitive mode
protection circuit is still not active.
At t2, the low-side gate driver turns off for a
second time. CSNEG is zero and CSPOS is
high, which means the converter is operating in
capacitive mode. The body diode of the lowside MOSFET takes over the current after the
low-side MOSFET is turned off. SW does not
turn high, so HBVS cannot catch the dv/dt until
the current returns to the correct polarity. The
dead time remains high, and VCO is held.
Another MOSFET does not switch on. So,
capacitive switching is effectively avoided.
At t3, the current returns to the correct polarity,
then another MOSFET is turned on due to dv/dt
being captured.
If the correct current polarity cannot be detected
from t2 to t4, or the current is very small and is
not capable of pulling SW up or down,
eventually another MOSFET will be forced to
switch on when the timer for CMP (50µs)
expires (as shown in Figure 32 in dashed lines).
The VSS control signal controls the soft start.
When capacitive mode operation is detected,
HR1200 Rev 1.1
3/25/2020
Over-Current Regulation and Over-Current
Protection (CSHB, TIMER)
t
Vss
VDT
VSS is high. An internal MOSFET is turned on to
pull the voltage of CSS low. Therefore, the
switching frequency increases quickly to limit
the power delivered to the output. VSS is reset
when the first gate driver is turned off (after
CMP). The switching frequency decreases
smoothly until the control loop takes over.
a. The transistor connected internally between
SS and GND is turned on for at least 10µs,
which causes the CSS voltage dropping
down, resulting in a sharp increase in the
oscillator frequency. Hence, the energy
transferred to the output is reduced.
b. An internal 140µA current source is turned
on to charge CTIMER and raises the voltage
of TIMER pin. If the CSHB voltage drops
below VCS-OCR (10mV hysteresis) before the
TIMER voltage reaches Vth1 (1.97V), the
discharging of CSS and the charging of
CTIMER stop. Then the converter resumes
normal operation.
tOC represents the time for the CTIMER voltage to
rise from 0V to Vth1. It is actually a delay time for
over-current regulation. There is no simple
relationship between tOC and CTIMER. CTIMER is
selected based on experimental results.
If the CSHB voltage remains larger than VCS-OCR
after the TIMER voltage reaches Vth1, CSS is
discharged completely. Simultaneously, internal
140µA current source continues charging CTIMER
until the TIMER voltage reaches Vth2 (3.45V). At
this time, the IC turns off all gate driver outputs.
The period for the TIMER voltage to rise from
Vth1 to Vth2 can be calculated approximately by
using Equation (30):
t OP 10 4 CTIMER
(30)
The above status remains until VTIMER drops to
Vth3 (0.29V) as CTIMER is slowly discharged by
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32
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
RTIMER. The IC then restarts. The time period
can be calculated using Equation (31):
t OFF ln
Vth2
RTIMERCTIMER 2.5 RTIMERCTIMER
Vth3
(31)
The OCR limits the energy transferred from the
primary to the secondary winding during overload or short-circuit period. However, excessive
power consumption due to high continuous
currents can damage the secondary-side
windings and rectifiers. By incorporating the
TIMER function, the IC provides additional
protection to reduce the average power
consumption. When OCR is triggered, the
converter enters a hiccup-like protection mode
that operates intermittently. Figure 33 shows
the timing procedure.
VCC
tOC
tOFF
tOP
The HR1200 uses two methods for sensing
current: lossless current sensing and sense
resistor current sensing. Generally, lossless
current sensing is used in high-power
applications (see Figure 34).
Lr
R1
CSHB
C1
RS
CS
Cr
Figure 34: Current Sensing with Lossless
Network
tSS
t
VSS
VREF
VSS-OCP
To design a lossless current sensing network,
Inequality (32) should be satisfied:
t
ICr
CS
t
Cr
100
(32)
VCS-OCP
VCS-OCR
VCS
t
TIMER
Vth2
Vth1
Vth3
t
Vout
Normal
Operation
t
Over Load Pmin
Shutdown
Soft Start
OCP( restart mode)
Figure 33: OCR Timing Sequence
RS should meet Inequality (33):
C
1 r
(33)
CS
where ICrpk is the peak current of the resonant
tank at low input voltage and full load. ICrpk can
be expressed in Equation (34):
RS
2. Over-Current Protection
The second level of protection triggers when
VCS > VCS-OCP (1.48V). Normally, this condition
occurs when the CSHB voltage continues rising
during short–circuit period. Once VCS rises to
VCS-OCP, the IC does not stop switching
immediately until VSS < VSS-OCP, and CSS is
discharged
by
an
internal
transistor
continuously. If VCS remains above VCS-OCP until
VSS drops below VSS-OCP, the IC shuts down.
CTIMER is charged by an internal 140µA current
source until the TIMER voltage reaches Vth2.
The IC resumes operation if the TIMER voltage
falls below Vth3.
The OCP provides a high-speed over-current
limitation. The IC works in auto-recovery mode
when OCP triggers.
Current Sensing
HR1200 Rev 1.1
3/25/2020
VCS-OCR
ICrpk
2
ICrpk
NVo Ioπ
4L m fs 2N
2
(34)
where N is the turn ratio of the transformer, lo
and Vo are the output current and voltage
respectively, fs is the switching frequency, and
Lm is the magnetizing inductance.
For capacitive mode detection in no load or tiny
load condition, RS should meet Inequality (35)
as well:
RS
80 mV
C
1 r
Im
CS
(35)
In some conditions especially when large Lm is
used, it’s difficult to meet Inequality (33) and
Inequality (35) simultaneously. The system will
operate without CMP function at light load if
Inequality (35) is not satisfied.
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33
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
The R1 and C1 network is used to attenuate the
switching noise on CSHB. The time constant
should be no larger than 100ns.
An alternative solution is to use a sense resistor
in series with the resonant tank (see Figure 35).
This method is quite simple, but may cause
undesired power consumption on the sense
resistor.
SS
CT
CT
VCO
Css
Iset
Rss
VREF
FSET
BURST
Burst control
Vth
Rfmax
Rfmin
RBURST
CBURST
Lr
Figure 36: Burst-Mode Operation Set-Up
CSHB
R1
C1
Cr
RS
Figure 35: Current Sensing with A Sense
Resistor
The sense resistor can be designed using
Inequality (36):
RS
VCS-OCR
ICrpk
(36)
LLC Brown-In/Brown-Out (D2D_BI/BO)
The LLC controller stops when the D2D_BI/BO
signal is low and recovers once the D2D_BI/BO
signal goes high.
Burst-Mode Operation (BURST)
Under light-load or no-load condition, the
resonant half-bridge switching frequency is
limited by the system maximum frequency. To
control the output voltage and limit the power
consumption, the HR1200 enables the
converter to operate in burst mode to reduce
the average switching frequency, thus reducing
the average residual magnetizing current and
related power losses.
HR1200 Rev 1.1
3/25/2020
Figure 36 shows a typical circuit connecting
BURST to the feedback signal. RBURST and
CBURST must be optimized to adjust the number
of switching cycles during burst-on period,
which can reduce no-load power consumption.
Rfmax can determine the maximum switching
frequency which is needed for the IC to operate
in burst mode. It also determines the level of
output load needed to run into burst mode.
Figure 37 illustrates the burst-mode operation
waveforms. When the output load decreases,
the BURST voltage also decreases. If the
BURST voltage drops below Vth (1.23V), the
HR1200 stops switching both the HSG and
LSG and connects CT to GNDS internally.
Meanwhile, the SYN signal is set high. It is
used to synchronize the burst of PFC and LLC.
Once the voltage on BURST exceeds Vth by a
hysteresis of 40mV, the HR1200 resumes
normal operation and the SYN signal is set low.
During burst-mode operation, VREG normally
holds above VregUVP, and the soft-start function
is not activated.
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34
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VO
t
LG/HG
t
BURST
Connect SO to the resistor divider from V3.3 if
the SO functions are not needed.
1.27V
40mV
1.23V
Vth+Vhys
Vth
with the TIMER capacitor, the TIMER voltage is
pulled down gradually. Until the TIMER voltage
falls below Vth3, the IC attempts another restart
sequence.
t
High-Side Gate Driver (HSG)
FBP
t
GATEP
t
SYN
For PFC
Burst off
Burst off
Burst off
t
Figure 37: Burst-Mode Operation
Latch Protection (SO)
If the SO voltage exceeds the threshold VSO-Latch
(3.42V), the IC latches off. This status can only
be released when VCC drops below VCCRST.
This function can be used for OVP or OTP.
The external BST capacitor provides energy to
the high-side gate driver. An integrated
bootstrap diode charges this capacitor through
VCC. This diode simplifies the external driving
circuit for the high-side switch, allowing the BST
capacitor to be charged when the low-side
MOSFET is on.
Considering the BST capacitor charging time, in
order to provide enough gate driver energy, a
BST capacitor of 100nF to 1μF is recommender
(see Figure 39).
VCC
Start-Up Failure Protection (SFP, SO)
BST
The HR1200 provides a one-shot start-up
failure protection by sampling the SO voltage.
Figure 38 shows the detailed SFP timing.
VSO
Transient
Unplug from
main input
High Side
Driver
Over Load
or Short
1.96V
VSO-SFP
t
LG/HG
Level
Shifter
HSG
CBST
SW
t
VSS Soft Start
t
TIMER
Vth2
Vth1
3.45V
1.97V
Vth3
0.29V
Low-Side Gate Driver (LSG)
t
SFP
t
Figure 38: SFP Timing
During start-up, the TIMER capacitor begins to
be charged up by an internal 25µA current
source. If the SO voltage is less than VSO-SFP
(1.96V) when the TIMER voltage rises up to Vth1,
then the IC treats it as a fault condition. The
HR1200 begins discharging the SS capacitor,
and TIMER continues ramping up irreversibly.
As soon as the TIMER voltage reaches Vth2, the
HR1200 stops charging TIMER, both PFC and
LLC stop switching. As a resistor is in parallel
HR1200 Rev 1.1
3/25/2020
Figure 39: High-Side Gate Driver
LSG provides the gate driver signal for the lowside MOSFET. The maximum absolute rating
table shows the maximum LSG voltage is 14V.
Under certain conditions (e.g. surge rating is
too high), a large voltage spike may occur on
LSG due to oscillations from the long gatedriver wire, the MOSFET parasitic capacitance,
and the small gate-driver resistor. The voltage
spike may cause damage to LSG. Although
there is suppression internally in the chip, it is
better to add a 13V Zener diode close to LSG
and GND to prevent damage to the chip pins
(see Figure 40).
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35
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
SW
Vreg
Cgd
Low Side
Driver
LSG
Cds
Rg
13V
Cgs
GNDP
Figure 40: Low-Side Gate Driver
HR1200 Rev 1.1
3/25/2020
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36
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
PROTECTION SUMMARY
Pin
Description
Affected
Action
VCC
Symbol
VCC_UVP
Under-voltage protection for VCC
System
Disable
VCC
VCC_SCP
Short-circuit protection for VCC
System
Disable and limit IHV
VREG
Vreg_UVP
Under-voltage protection for VREG
System
Disable and limit Ich (Vreg)
SO
VSO_Latch
Latch protection
System
Shutdown and latch
SO
VSO_SFP
Start-up failure protection
System
Restart with timer out
OTP
Over-temperature protection
System
Disable
ACIN
Brown-out
Line input under-voltage protection
System
CSP
OCP_PFC
Current limit of PFC
PFC
FBP
FBP
FBP
OVP_PFC
OLP_PFC
UVP_PFC
Over voltage of PFC
Open-loop protection
Under-voltage protection for PFC out
PFC
System
HBC
Suspend switching
Program with restart or
latch off
Suspend switching
Restart with recovery
Suspend switching
LLC brown-in/-out
LLC stage under-voltage protection
HBC
Suspend switching
CSHB
OCR_HBC
Over-current regulation of HBC
HBC
CSHB
OCP_HBC
Over-current protection HBC
HBC
CSHB
CMR
Capacitive mode regulation
HBC
CSHB
ADT
Adaptive dead time
HBC
Restart with timer out
Shutdown, restart with
timer out
Increasing switching
frequency
Prevent hard switching
HR1200 Rev 1.1
3/25/2020
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37
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TYPICAL APPLICATION CIRCUIT
Figure 41: Application Circuit
HR1200 Rev 1.1
3/25/2020
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38
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
PACKAGE OUTLINE DRAWING FOR 28-TSSOP
PACKAGE INFORMATION
MF-PO-D-0024
revision 1.0
TSSOP-28
9.60
9.80
0.40 TYP
28
15
1.60
TYP
4.30
4.50
PIN 1 ID
0.65 BSC
5.80
TYP
6.20
6.60
14
1
TOP VIEW
RECOMMENDED LAND PATTERN
0.80
1.05
1.20 MAX
SEATING PLANE
0.19
0.30
0.65 BSC
0.05
0.15
0.09
0.20
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
NOTE:
GAUGE PLANE
0.25 BSC
0o-8o
0.45
0.75
DETAIL “A”
HR1200 Rev 1.1
3/25/2020
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AE.
6) DRAWING IS NOT TO SCALE.
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39
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
PACKAGE OUTLINE DRAWING FOR 28-SOIC
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
MF-PO-D-0022 revision 2.0
PACKAGE INFORMATION (continued)
SOIC-28
0.024
(0.61)
0.697(17.70)
0.713(18.10)
28
15
0.050
(1.27)
0.079
(2.00)
0.291
(7.40)
0.299
(7.60)
0.394
(10.00)
0.418
(10.60)
0.370
(9.40)
PIN 1 ID
14
1
TOP VIEW
0.013(0.33)
0.020(0.51)
RECOMMENDED LAND PATTERN
0.050(1.27)
BSC
0.093(2.35)
0.104(2.65)
SEATING PLANE
0.004(0.10)
0.012(0.30)
FRONT VIEW
0.010(0.25)
x 45o
0.030(0.75)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
HR1200 Rev 1.1
3/25/2020
0.009(0.23)
0.013(0.33)
SEE DETAIL "A"
SIDE VIEW
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MS-013, VARIATION AE.
6) DRAWING IS NOT TO SCALE.
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40
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
APPENDIX A: I2C COMMANDS AND REGISTERS
VOUT_CMD_H (02/01h, 10bits)
Set the normal value of the output voltage target at high line. The default setting for the -0001 version is
1100011110.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
VOUT_CMD_H
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
VOUT_CMD_L (04/03h, 10bits)
Set the normal value of the output voltage target at low line. The default setting for the -0001 version is
1100011110.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r/w
VOUT_CMD_L
8
7
6
r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
VIN_HL_LINE (05h, 8bits)
Set the threshold of high line and low line. The default setting for the -0001 version is 01110001.
Command
Bit
Access
7
r/w
6
r/w
VIN_HL_LINE
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
AUTO_VOUT_VCOMP1 (07/06h, 14bits)
Set the Load Level1 of the auto-output voltage. The default setting for the -0001 version is
011111111100.
Command
Bit
Access
15
r
14
r
13
r/w
12
r/w
11
r/w
10
r/w
AUTO_VOUT_VCOMP1
9
8
7
6
5
r/w r/w r/w r/w r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
AUTO_VOUT_VCOMP2 (09/08h, 14bits)
Set the Load Level2 of the auto-output voltage. The default setting for the -0001 version is
001100110010.
Command
Bit
Access
15
r
14
r
13
r/w
12
r/w
11
r/w
10
r/w
AUTO_VOUT_VCOMP2
9
8
7
6
5
r/w r/w r/w r/w r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
AUTO_VOUT_VCOMP3 (0B/0Ah, 14bits)
Set the Load Level3 of the auto-output voltage. The default setting for the -0001 version is
000110011001.
Command
Bit
Access
15
r
14
r
13
r/w
12
r/w
11
r/w
10
r/w
AUTO_VOUT_VCOMP3
9
8
7
6
5
r/w r/w r/w r/w r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
AUTO_VOUT_CMPHYS (0D/0Ch, 14bits)
Set the load hysteresis of the auto-output voltage. The default setting for the -0001 version is
000011110101.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
15
r
14
r
13
r/w
12
r/w
11
r/w
10
r/w
AUTO_VOUT_CMPHYS
9
8
7
6
5
r/w r/w r/w r/w r/w
4
r/w
3
r/w
2
r/w
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1
r/w
0
r/w
41
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
AUTO_VOUTH_CMD1_L (0Eh, 8bits)
Set the low byte of the output voltage level one at high line. The default setting for the -0001 version is
00011110.
Command
Bit
Access
7
r/w
6
r/w
AUTO_VOUTH_CMD1_L
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
AUTO_VOUTH_CMD2_L (0Fh, 8bits)
Set the low byte of the output voltage level two at high line. The default setting for the -0001 version is
00011110.
Command
Bit
Access
7
r/w
6
r/w
AUTO_VOUTH_CMD2_L
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
AUTO_VOUTH_CMD3_L (10h, 8bits)
Set the low byte of the output voltage level three at high line. The default setting for the -0001 version is
00011110.
Command
Bit
Access
7
r/w
6
r/w
AUTO_VOUTH_CMD3_L
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
AUTO_VOUTH_CMD_H (11h, 6bits)
Set the high byte of the output voltage at high line. The default setting for the -0001 version is 111111.
Bit
5:4
3:2
1:0
Item
AUTO_VOUTH_CMD3_H
AUTO_VOUTH_CMD2_H
AUTO_VOUTH_CMD1_H
Command
Bit
Access
Description
High bits of output voltage level three at high line.
High bits of output voltage level two at high line.
High bits of output voltage level one at high line.
7
r
6
r
AUTO_VOUTH_CMD_H
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
AUTO_VOUTL_CMD1_L (12h, 8bits)
Set the low byte of the output voltage level one at low line. The default setting for the -0001 version is
00011110.
Command
Bit
Access
7
r/w
6
r/w
AUTO_VOUTL_CMD1_L
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
AUTO_VOUTL_CMD2_L (13h, 8bits)
Set the low byte of the output voltage level two at low line. The default setting for the -0001 version is
00011110.
Command
Bit
Access
7
r/w
6
r/w
AUTO_VOUTL_CMD2_L
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
AUTO_VOUTL_CMD3_L (14h, 8bits)
Set the low byte of the output voltage level three at low line. The default setting for the -0001 version is
00011110.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r/w
6
r/w
AUTO_VOUTL_CMD3_L
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
42
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
AUTO_VOUTL_CMD_H (15h, 6bits)
Set the high byte of the output voltage at low line. The default setting for the -0001 version is 111111.
Bit
5:4
3:2
1:0
Item
AUTO_VOUTL_CMD3_H
AUTO_VOUTL_CMD2_H
AUTO_VOUTL_CMD1_H
Command
Bit
Access
Description
High bits of output voltage level three at low line.
High bits of output voltage level two at low line.
High bits of output voltage level one at low line.
7
r
AUTO_VOUTL_CMD_H
6
5
4
3
2
1
r
r/w r/w r/w r/w r/w
0
r/w
LLC_ENABLE_HIGH (17/16h, 10bits)
Set the enable threshold voltage of the LLC. The default setting for the -0001 version is 1100101010.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
LLC_ENABLE_HIGH
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
LLC_ENABLE_LOW (19/18h, 10bits)
Set the disable threshold voltage of the LLC. The default setting for the -0001 version is 1001010001.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
LLC_ENABLE_LOW
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
ZCD_PERIOD_H (1Ah, 7bits)
Set the oscillation period of the turn-off current at high line. The default setting for the -0001 version is
0010100.
Command
Bit
Access
7
r
6
r/w
ZCD_PERIOD_H
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
ZCD_PERIOD_L (1Bh, 7bits)
Set the oscillation period of the turn-off current at low line. The default setting for the -0001 version is
0101000.
Command
Bit
Access
7
r
6
r/w
ZCD_PERIOD_L
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
SLEWRATE_HIGH (1Ch, 8bits)
Set the soft-start slew rate at high line. The default setting for -0001 version is 00000110.
Command
Bit
Access
7
r/w
6
r/w
SLEWRATE_HIGH
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
SLEWRATE_LOW (1Dh, 8bits)
Set the soft-start slew rate at low line. The default setting for the -0001 version is 00001101.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r/w
6
r/w
SLEWRATE_LOW
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
43
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TS1_L (1Eh, 8bits)
Set the low byte of the switching period at level one of the input voltage. The default setting for the
-0001 version is 11001000.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS1_L
4
3
r/w r/w
2
r/w
1
r/w
0
r/w
TS2_L (1Fh, 8bits)
Set the low byte of the switching period at level two of the input voltage. The default setting for the
-0001 version is 11001000.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS2_L
4
3
r/w r/w
2
r/w
1
r/w
0
r/w
TS3_L (20h, 8bits)
Set the low byte of the switching period at level three of the input voltage. The default setting for the
-0001 version is 11001000.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS3_L
4
3
r/w r/w
2
r/w
1
r/w
0
r/w
TS4_L (21h, 8bits)
Set the low byte of the switching period at level four of the input voltage. The default setting for the
-0001 version is 10100111.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS4_L
4
3
r/w r/w
2
r/w
1
r/w
0
r/w
TS_H (22h, 4bits)
Set the high byte of the switching period. The default setting for the -0001 version is 0000.
Bit
3
2
1
0
Item
TS4_H
TS3_H
TS2_H
TS1_H
Description
High bit of switching period at level four of the input voltage.
High bit of switching period at level three of the input voltage.
High bit of switching period at level two of the input voltage.
High bit of switching period at level one of the input voltage.
Command
Bit
Access
7
r
6
r
5
r
TS_H
4
3
r
r/w
2
r/w
1
r/w
0
r/w
TS_MIN1_L (23h, 8bits)
Set the low byte of the maximum switching period at level one of the input voltage. The default setting
for the -0001 version is 00100000.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS_MIN1_L
4
3
2
r/w r/w r/w
1
r/w
0
r/w
TS_MIN2_L (24h, 8bits)
Set the low byte of the maximum switching period at level two of the input voltage. The default setting
for the -0001 version is 00100000.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r/w
6
r/w
5
r/w
TS_MIN2_L
4
3
2
r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
44
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
TS_MIN3_L (25h, 8bits)
Set the low byte of the maximum switching period at level three of the input voltage. The default setting
for the -0001 version is 00100000.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS_MIN3_L
4
3
2
r/w r/w r/w
1
r/w
0
r/w
TS_MIN4_L (26h, 8bits)
Set the low byte of the maximum switching period at level four of the input voltage. The default setting
for the -0001 version is 11110100.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS_MIN4_L
4
3
2
r/w r/w r/w
1
r/w
0
r/w
TS_MIN_H (27h, 8bits)
Set the high byte of the maximum switching period. The default setting for the -0001 version is
01111111.
Bit
7:6
5:4
3:2
1:0
Item
TS_MIM4_H
TS_MIN3_H
TS_MIN2_H
TS_MIN1_H
Description
High bit of the maximum switching period at level four.
High bit of the maximum switching period at level three.
High bit of the maximum switching period at level two.
High bit of the maximum switching period at level one.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
TS_MIN_H
4
3
2
r/w r/w r/w
1
r/w
0
r/w
JITTER_AMPLITUDE (28h, 8bits)
Set the peak-to-peak amplitude of the switching frequency jitter. The default setting for the -0001
version is 00000010.
Command
Bit
Access
7
r/w
6
r/w
JITTER_AMPLITUDE
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
JITTER_FS (30/29h, 13bits)
Set the step value and the period of step of the switching frequency jitter. The default setting for -0001
version is 0100000011110.
Bit
12:11
10:0
Command
Bit
Access
Item
JITTER_STEP
STEP_PERIOD
15
r
14
r
13
r
Description
Step value.
Step period.
12
r/w
11
r/w
10
r/w
9
r/w
JITTER_FS
8
7
6
r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
TON_MIN (2Bh, 5bits)
Set the minimum turn-on time. The default setting for the -0001 version is 01100.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r
6
r
5
r
TON_MIN
4
3
2
r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
45
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
MIN_OFF_TIME (2Ch, 5bits)
Set the minimum turn-off time. The default setting for the -0001 version is 01100.
Command
Bit
Access
7
r
6
r
MIN_OFF_TIME
5
4
3
2
r
r/w r/w r/w
1
r/w
0
r/w
BURST_POINT_H (2E/2Dh, 13bits)
Set the PFC burst load at high line. The default setting for the -0001 version is 0000111101011.
Command
Bit
Access
15
r
14
r
13
r
12
r/w
11
r/w
10
r/w
BURST_POINT_H
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
BURST_POINT_L (30/2Fh, 13bits)
Set the PFC burst load at low line. The default setting for the -0001 version is 0000111101011.
Command
Bit
Access
15
r
14
r
13
r
12
r/w
11
r/w
10
r/w
BURST_POINT_L
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
NORMAL_KI (31h, 8bits)
Set the Ki value at normal operation mode. The default setting for the -0001 version is 00010010.
Command
Bit
Access
7
r/w
6
r/w
NORMAL_KI
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
NORMAL_KP (32h, 8bits)
Set the Kp value at normal operation mode. The default setting for the -0001 version is 01111000.
Command
Bit
Access
7
r/w
6
r/w
NORMAL_KP
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
FAST_KI (34/33h, 10bits)
Set the Ki value at fast-loop operation mode. The default setting for the -0001 version is 0001001000.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r/w
FAST_KI
8
7
r/w r/w
6
r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
FAST_KP (36/35h, 10bits)
Set the Kp value at fast-loop operation mode. The default setting for the -0001 version is 0100100000.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r/w
FAST_KP
8
7
r/w r/w
6
r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
FASTLOOP_VOLTAGE (37h, 7bits)
Set the fast-loop level below the output voltage target. The default setting for the -0001 version is
0011111.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r
6
r/w
FASTLOOP_VOLTAGE
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
46
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VIN_BI_LEVEL (39/38h, 10bits)
Set the brown-in voltage of the input voltage. The default setting for the -0001 version is 0011101101.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
VIN_BI_LEVEL
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
VIN_BO_LEVEL (3B/3Ah, 10bits)
Set the brown-out voltage of the input voltage. The default setting for the -0001 version is 0011011001.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
VIN_BO_LEVEL
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
VIN_BIBO_TIME (3Ch, 8bits)
Set the brown-in and brown-out time of the input voltage. The default setting for the -0001 version is
00000101.
Bit
7:4
3:0
Item
VIN_BI_TIME
VIN_BO_TIME
Description
Brown-in time.
Brown-out time.
Command
Bit
Access
7
r/w
6
r/w
VIN_BIBO_TIME
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
IREF_LEVEL1 (3E/3Dh, 9bits)
Level one of the input current reference. The default setting for the -0001 version is 010001001.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
IREF_LEVEL1
8
7
6
r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
IREF_LEVEL2 (40/3Fh, 9bits)
Level two of the input current reference. The default setting for the -0001 version is 001000101.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
IREF_LEVEL2
9
8
7
6
r
r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
IREF_HYS (41h, 8bits)
Set the hysteresis of the level of the input current reference. The default setting for the -0001 version is
00010111.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
IREF_HYS
4
3
2
r/w r/w r/w
1
r/w
0
r/w
VIN_BO_TRIM1 (42h, 6bits)
Set the trim value of the brown-out level of the input voltage at level one. The default setting for the
-0001 version is 000000.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r
6
r
VIN_BO_TRIM1
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
47
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VIN_BO_TRIM2 (43h, 6bits)
Set the trim value of the brown-out level of the input voltage at level two. The default setting for the
-0001 version is 000000.
Command
Bit
Access
7
r
6
r
VIN_BO_TRIM2
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
OCP_LIMIT (44h, 7bits)
Set the over-current limit of the inductor current. The default setting for the -0001 version is 0000100.
Command
Bit
Access
7
r
6
r/w
OCP_LIMIT
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
OCP_MODE (45h, 4bits)
Set the over-current protection mode. The default setting for the -0001 version is 0000.
Bit
3
2:0
Item
Description
OCP_MODE_EN
1: enable
0: disable
OCP_MODE
000: latch
111: hiccup
other: retry number
Command
Bit
Access
7
r
6
r
5
r
OCP_MODE
4
3
2
r
r/w r/w
1
r/w
0
r/w
OCP_RETRY_DELAY (47/46h, 10bits)
Set the delay time of the system recovery after the OCP event is cleared. The default setting for the
-0001 version is 0111110100.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
OCP_RETRY_DELAY
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
OVP_LIMIT_H (48h, 7bits)
Set the over-voltage limit of the output voltage at high line. The default setting for the -0001 version is
1101101.
Command
Bit
Access
7
r
6
r/w
OVP_LIMIT_H
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
OVP_LIMIT_L (49h, 7bits)
Set the over-voltage limit of the output voltage at low line. The default setting for the -0001 version is
1101101.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r
6
r/w
5
r/w
OVP_LIMIT_L
4
3
2
r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
48
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
CODE ID (4Ah, 8bits)
Store customer code ID. The default setting for the -0001 version is 00000001.
Bit
7:2
1:0
Item
CUSTOMER_ID
PROGRAMMED CODE_ID
Command
Bit
Access
Description
Customer number
Programmed code number
7
r/w
6
r/w
5
r/w
CODE ID
4
3
r/w r/w
2
r/w
1
r/w
0
r/w
IREF_COMP_VALUE1 (4Bh, 7bits)
Set the first compensation amplitude of the input current reference. The default setting for the -0001
version is 0000001.
Command
Bit
Access
7
r
6
r/w
IREF_COMP_VALUE1
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
IREF_COMP_VALUE2 (4Ch, 7bits)
Set the second compensation amplitude of the input current reference. The default setting for the -0001
version is 0000011.
Command
Bit
Access
7
r
6
r/w
IREF_COMP_VALUE2
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
IREF_COMP_VALUE3 (4Dh, 7bits)
Set the third compensation amplitude of the input current reference. The default setting for the -0001
version is 0001101.
Command
Bit
Access
7
r
6
r/w
IREF_COMP_VALUE3
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
IREF_COMP_VALUE4 (4Eh, 7bits)
Set the fourth compensation amplitude of the input current reference. The default setting for the -0001
version is 0001100.
Command
Bit
Access
7
r
6
r/w
IREF_COMP_VALUE4
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
VIN_LEVEL_SEL1 (4Fh, 8bits)
Set the first voltage level of the input voltage. The default setting for the -0001 version is 10011001.
Command
Bit
Access
7
r/w
6
r/w
VIN_LEVEL_SEL1
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
VIN_LEVEL_SEL2 (50h, 8bits)
Set the second voltage level of the input voltage. The default setting for the -0001 version is 01001000.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r/w
6
r/w
VIN_LEVEL_SEL2
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
49
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VCOMP_MAX_L (52/51h, 16bits)
Set the maximum load. The default setting for the -0001 version is 0110110011010010.
Command
Bit
Access
15
r/w
14
r/w
13
r/w
12
r/w
11
r/w
10
r/w
VCOMP_MAX_L
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
VCOMP_MAX_H (53h, 8bits)
Set the maximum load. The default setting for the -0001 version is 01011001.
Command
Bit
Access
7
r/w
6
r/w
VCOMP_MAX_H
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
IREF_MAX (55/54h, 9bits)
Set the maximum value of the input current reference. The default setting for the -0001 version is
111100100.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
IREF_MAX
8
7
6
r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
SYS_CONFIG (56h, 8bits)
Configure the system. The default setting for the -0001 version is 00110100.
Bit
Item
Description
7
BURST_LLC_SYNC_EN
Synchronize PFC with LLC in burst mode.
1: enable
0: disable
6
------
5
POWER_ON
4
LLC_EN
Enable LLC part.
1: enable
0: disable
3
AUTO_VOUT_EN
Output voltage target is determined by the load.
1: enable
0: disable
2
IREF_COMP_EN
Compensate the current of the input capacitance.
1: enable
0: disable
1
JITTER_EN
Switching frequency jitter.
1: enable
0: disable
0
ZCD_EN
Valley turn on.
1: enable
0: disable
Reserved
Power on the system.
1: enable
0: disable
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r/w
6
r/w
SYS_CONFIG
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
50
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
AD_SLEEP_FS (58/57h, 10bits)
Set the ADC sample rate when PWM is off. The default setting for the -0001 version is 1100100000.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
AD_SLEEP_FS
9
8
7
6
r/w r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
TON_AHEAD (59h, 4bits)
Set the peak-current sample point. The default setting for the -0001 version is 0010.
Command
Bit
Access
7
r
6
r
5
r
TON_AHEAD
4
3
2
r
r/w r/w
1
r/w
0
r/w
OLP_HIGH (5Ah, 7bits)
Set the open-loop protection at high level. The default setting for the -0001 version is 1011100.
Command
Bit
Access
7
r
6
r/w
5
r/w
OLP_HIGH
4
3
2
r/w r/w r/w
1
r/w
0
r/w
OLP_LOW (5Bh, 7bits)
Set the open-loop protection at low level. The default setting for the -0001 version is 0111101.
Command
Bit
Access
7
r
6
r/w
5
r/w
OLP_LOW
4
3
2
r/w r/w r/w
1
r/w
0
r/w
SOFT_TON (5Ch, 7bits)
Set the soft turn-on time when the system recovers from OVP. The default setting for the -0001 version
is 0101000.
Command
Bit
Access
7
r
6
r/w
5
r/w
SOFT_TON
4
3
2
r/w r/w r/w
1
r/w
0
r/w
SOFT_SWITCH_CNT (5Dh, 4bits)
Set the number of switching events during soft turn on. The default setting for the -0001 version is 0111.
Command
Bit
Access
7
r
6
r
SOFT_SWITCH_CNT
5
4
3
2
1
r
r
r/w r/w r/w
0
r/w
MFR_MERGE_REG (5Eh, 8bits)
The default setting for the -0001 version is 00100001.
Bit
7:3
2:1
0
Item
SWITCH_BLANK_TIME1
Description
PWM off blanking time
CURRENT_MIRROR_GAIN
Set the current mirror gain. The reference current is 62.5µA.
00: GAIN =1
01: GAIN = 1.4
10: GAIN = 1.6
11: GAIN = 2
I2C_FILTER_EN
I2C filter.
1: enable
0: disable
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r/w
6
r/w
MFR_MERGE_REG
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
51
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
SWITCH_BLANK_TIME (5Fh, 8bits)
Set the PWM on blanking time. The default setting for the -0001 version is 00110101.
Bit
7:4
3:0
Item
SWITCH_BLANK_TIME2
SWITCH_BLANK_TIME3
Command
Bit
Access
Description
PWM off blanking time for OCP.
PWM off blanking time for OCL.
7
r/w
6
r/w
SWITCH_BLANK_TIME
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
OVP_DELAYTIME (60h, 6bits)
Set the blanking time of OVP. The default setting for the -0001 version is 110010.
Command
Bit
Access
7
r
6
r
OVP_DELAYTIME
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
BURST_MODE_HYS (61h, 6bits)
Set the hysteresis of the output voltage in burst mode. The default setting for the -0001 version is
001010.
Command
Bit
Access
7
r
6
r
BURST_MODE_HYS
5
4
3
2
1
r/w r/w r/w r/w r/w
0
r/w
ERROR_ZERO_REGION (62h, 5bits)
Set the non-regulation region of the output voltage. The default setting for the -0001 version is 00000.
Command
Bit
Access
7
r
ERROR_ZERO_REGION
6
5
4
3
2
1
r
r
r/w r/w r/w r/w
0
r/w
VIN_ZERO_POINT (63h, 7bits)
Set the period detection point of the input voltage. The default setting for the -0001 version is 1010010.
Command
Bit
Access
7
r
6
r/w
VIN_ZERO_POINT
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
VIN_PEAK_VALUE (64h, 7bits)
Set the value to detect the top of the input voltage. The default setting for the -0001 version is 0010100.
Command
Bit
Access
7
r
6
r/w
VIN_PEAK_VALUE
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
VIN_VALLEY_VALUE (65h, 7bits)
Set the value to detect the valley of the input voltage. The default setting for the -0001 version is
0111101.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r
VIN_VALLEY_VALUE
6
5
4
3
2
1
r/w r/w r/w r/w r/w r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
52
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
IPK_BIAS_TRIM (66h, 8bits)
Trim the bias voltage at CSP. The default setting for the -0001 version is 00000000.
Bit
Item
Description
7
CSP_FAULT_MODE
Determine the control mode when CSP is open or shorted.
1: hiccup
0: latch
6
IPK_BIAS_SAMPLE_EN
Enable sampling of the CSP bias voltage when power is on.
1: enable
0: disable
IPK_BISA_TRIM
Trim the bias voltage at CSP.
5:0
Command
Bit
Access
7
r/w
6
r/w
IPK_BIAS_TRIM
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
ADC_OFFSET_TRIM (67h, 5bits)
Trim the ADC offset. The default setting for the -0001 version is 00000.
Command
Bit
Access
7
r
6
r
ADC_OFFSET_TRIM
5
4
3
2
1
r
r/w r/w r/w r/w
0
r/w
DELTA_VOLTAGE (68h, 7bits)
Set the minimum delta voltage between the input voltage and output voltage for CSP bias voltage
sampling. The default setting for the -0001 version is 0101001.
Command
Bit
Access
7
r
6
r/w
DELTA_VOLTAGE
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
VIN_LEVEL1 (69h, 7bits)
Input voltage level one for the CSP bias voltage sample. The default setting for the -0001 version is
0010100.
Command
Bit
Access
7
r
6
r/w
5
r/w
VIN_LEVEL1
4
3
2
r/w r/w r/w
1
r/w
0
r/w
VIN_LEVEL2 (6Ah, 7bits)
Input voltage level two for the CSP bias voltage sample. The default setting for the -0001 version is
0101001.
Command
Bit
Access
7
r
6
r/w
5
r/w
VIN_LEVEL2
4
3
2
r/w r/w r/w
1
r/w
0
r/w
VIN_LEVEL3 (6Bh, 7bits)
Input voltage level three for the CSP bias voltage sample. The default setting for the -0001 version is
0111101.
Command
Bit
Access
HR1200 Rev 1.1
3/25/2020
7
r
6
r/w
5
r/w
VIN_LEVEL3
4
3
2
r/w r/w r/w
1
r/w
0
r/w
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
53
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER
NOT RECOMMENDED FOR NEW DESIGNS. REFER TO HR1203
VIN_LEVEL4 (6D/6Ch, 10bits)
Input voltage level four for the CSP bias voltage sample. The default setting for the -0001 version is
0100110011.
Command
Bit
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r/w
VIN_LEVEL4
8
7
6
r/w r/w r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
VIN_HL_HYS (6Eh, 8bits)
Set the hysteresis of the input voltage for adaptive control. The default setting for the -0001 version is
00000101.
Command
Bit
Access
7
r/w
6
r/w
5
r/w
VIN_HL_HYS
4
3
2
r/w r/w r/w
1
r/w
0
r/w
ZCD_VIN_HYS (6Fh, 6bits)
Set the hysteresis of the input voltage for valley turn on. The default setting for the -0001 version is
010100.
Command
Bit
Access
7
r
6
r
ZCD_VIN_HYS
5
4
3
2
r/w r/w r/w r/w
1
r/w
0
r/w
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
HR1200 Rev 1.1
3/25/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
54
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