MP6529
5V to 35V, Three-Phase, Brushless
DC Motor Pre-Driver
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP6529 is a gate driver IC designed for
three-phase, brushless DC motor driver
applications; it is capable of driving three halfbridges consisting of six N-channel power
MOSFETs up to 35V.
The MP6529 uses a bootstrap capacitor to
generate a supply voltage for the high-side
MOSFET driver. An internal trickle-charge
circuit maintains a sufficient gate driver voltage
at 100% duty cycle.
Full protection features include programmable
over-current protection (OCP), adjustable deadtime control, under-voltage lockout (UVLO), and
thermal shutdown.
The MP6529 is available in a 28-pin TSSOP
(9.7mmx6.4mm) package with an exposed
thermal pad and a 28-contact QFN (4mmx4mm)
package with an exposed thermal pad.
Wide 5V to 35V Input Voltage Range
Bootstrap Gate Driver with Trickle-Charge
Circuit Supports 100% Duty Cycle
Operation
Low-Power Sleep Mode for BatteryPowered Applications
Programmable Over-Current Protection of
External MOSFETs
Adjustable Dead-Time Control to Prevent
Shoot-Through
Thermal Shutdown and UVLO Protection
Fault Indication Output
Thermally Enhanced Surface-Mount
Package
APPLICATIONS
Three-Phase, Brushless DC Motors and
Permanent Magnet Synchronous Motors
Power Drills
Impact Drivers
E-Cigar
E-Bike
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP6529 Rev. 1.01
5/28/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
1
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
ORDERING INFORMATION
Part Number
MP6529GR*
MP6529GF**
Package
QFN-28 (4mmx4mm)
TSSOP-28 EP (9.7mmx6.4mm)
Top Marking
See Below
See Below
* For Tape & Reel, add suffix –Z (e.g. MP6529GR–Z)
** For Tape & Reel, add suffix –Z (e.g. MP6529GF–Z)
TOP MARKING (MP6529GR)
MPS: MPS prefix
Y: Year code
WW: Week code
MP6529: Part number
LLLLLL: Lot number
TOP MARKING (MP6529GF)
MPS: MPS prefix
YY: Year code
WW: Week code
MP6529: Part number
LLLLLLLLL: Lot number
MP6529 Rev. 1.01
5/28/2019
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2
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
QFN-28 (4mmx4mm)
TSSOP-28 EP (9.7mmx6.4mm)
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Input voltage (VIN) ........................... -0.3V to 40V
CPA ................................................. -0.3V to 40V
CPB .............................................. -0.3V to 12.5V
VREG .............................................. -0.3V to 13V
BSTA/B/C ........................................ -0.3V to 55V
GHA/B/C ......................................... -0.3V to 55V
SHA/B/C .......................................... -0.3V to 40V
GLA/B/C .......................................... -0.3V to 13V
All other pins to AGND ................... -0.3V to 6.5V
Continuous power dissipation (TA = +25°C) (2)
QFN-28 (4mmx4mm)………………….…...2.9W
TSSOP-28 EP (9.7mmx6.4mm)………....3.9W
Storage temperature .................-55C to +150C
Junction temperature .............................. +150C
Lead temperature (solder) ...................... +260C
QFN-28 (4mmx4mm) ........... …...42 ... .9 .... °C/W
TSSOP-28 EP (9.7mmx6.4mm)..32 ... .6 .... °C/W
θJA θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Input voltage (VIN) ............................... 5V to 35V
OC_REF voltage (VOC) ............... 0.125V to 2.4V
Operating junct. temp (TJ).........-40C to +125C
MP6529 Rev. 1.01
5/28/2019
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3
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
ELECTRICAL CHARACTERISTICS
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Power Supply
Input supply voltage
Quiescent current
Control Logic
Input logic low threshold
Input logic high threshold
Logic input current
Symbol
VIN
IQ
ISLEEP
VIL
VIH
IIN(H)
IIN(L)
nSLEEP pull-down current
ISLEEP-PD
RPD
Internal pull-down resistance
Fault Outputs (Open-Drain Outputs)
Output low voltage
VOL
Output high leakage current
IOH
Protection Circuit
VIN_RISE
UVLO rising threshold
VIN_HYS
UVLO hysteresis
VREG_RISE
VREG rising threshold
VREG_HYS
VREG hysteresis
VREG start-up delay
tREG
OC_REF threshold
OCP deglitch time
SLEEP wake-up time
LSS OCP threshold
Thermal shutdown
MP6529 Rev. 1.01
5/28/2019
Condition
VOC
tOC
tSLEEP
VLSS-OCP
TTSD
Min
Typ
5
nSLEEP = 1,
gate not switching
nSLEEP = 0
VIH = 5V
VIL = 0.8V
0.95
2
-20
-20
Max
Units
35
V
2
mA
1
µA
0.8
20
20
V
V
µA
µA
µA
kΩ
0.5
1
V
µA
4.5
V
mV
V
V
µs
V
V
µs
ms
V
oC
1
880
IO = 5mA
VO = 3.3V
3.3
6.8
VOC = 1V
VOC = 2.4V
0.8
2.18
0.4
3.9
200
7.6
0.54
700
1
2.4
3
1
0.5
150
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8.4
1
1.2
2.62
0.6
4
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Gate Drive
Symbol
Bootstrap diode forward voltage
VFBOOT
Condition
ID = 10mA
ID = 100mA
VIN = 5.5V-35V
VIN = 5V
Min
10
2xVIN-1
Typ
Max
Units
V
V
11.5
0.9
1.3
12.8
VREG output voltage
VREG
Maximum source current
Maximum sink current
Gate drive pull-up resistance
HS gate drive pull-down
resistance
LS gate drive pull-down
resistance
LS passive pull-down
resistance
LS automatic turn-on time
Charge pump frequency
IOSO(5)
IOSI(5)
RUP
VDS = 1V
RHS-DN
VDS = 1V
1.2
4.7
Ω
RLS-DN
VDS = 1V
1
5.5
Ω
Dead time
V
A
A
Ω
0.8
1
8
RLS-PDN
590
kΩ
tLS
fCP
1.8
110
6
0.74
30
µs
kHz
µs
µs
ns
tDEAD
Leave DT open
RDT = 200kΩ
DT tied to GND
NOTE:
5) Guaranteed by design.
MP6529 Rev. 1.01
5/28/2019
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5
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
TYPICAL CHARACTERISTICS
VIN = 24V, OC_REF = 0.5V, RDT = 200k, ENA = ENC = H, FPWMA = 20kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
0.96
0.95
4.4
7.8
4.3
7.78
7.76
4.2
0.94
0.93
0.92
7.7
3.9
7.68
7.66
7.64
3.7
-20
10
40
70
100 130
3.6
-50
2.43
0.505
2.425
0.504
7.62
-20
10
40
70
100 130
-20
10
40
70
100 130
7.6
-50
-20
10
40
70
100 130
0.503
2.42
0.502
2.415
0.501
2.41
0.5
2.405
0.499
0.498
2.4
0.497
2.395
2.39
-50
7.72
4
3.8
0.91
0.9
-50
7.74
4.1
0.496
-20
MP6529 Rev. 1.01
5/28/2019
10
40
70
100 130
0.495
-50
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6
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 24V, OC_REF = 0.5V, RDT = 200k, ENA = ENC = H, FPWMA = 20kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
Steady State
Steady State
Duty=10%
Steady State
Duty=50%
Duty=90%
VGHA
20V/div.
VGHA
20V/div.
VGHA
20V/div.
VGLA
10V/div.
VGLA
10V/div.
VGLA
10V/div.
VSHA
20V/div.
VSHA
20V/div.
IOUTA
100mA/div.
VSHA
20V/div.
IOUTA
500mA/div.
IOUTA
500mA/div.
Power Ramp Up
Power Ramp Up
Power Ramp Up
Duty=10%
Duty=50%
Duty=90%
VIN
10V/div.
VGHA
20V/div.
VIN
10V/div.
VGHA
20V/div.
VSHA
20V/div.
VSHA
20V/div.
IOUTA
100mA/div.
IOUTA
500mA/div.
VIN
10V/div.
VGHA
20V/div.
VSHA
20V/div.
IOUTA
1A/div.
Sleep Recovery
Sleep Recovery
Sleep Recovery
Duty=10%
Duty=50%
Duty=90%
VnSLEEP
2V/div.
VGHA
20V/div.
VnSLEEP
2V/div.
VGHA
20V/div.
VnSLEEP
2V/div.
VGHA
20V/div.
VSHA
20V/div.
VSHA
20V/div.
VSHA
20V/div.
IOUTA
100mA/div.
IOUTA
500mA/div.
IOUTA
1A/div.
MP6529 Rev. 1.01
5/28/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
7
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 24V, OC_REF = 0.5V, RDT = 200k, ENA = ENC = H, FPWMA = 20kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
Sleep Entry
Sleep Entry
Duty=10%
Sleep Entry
Duty=50%
Duty=90%
VnSLEEP
2V/div.
VnSLEEP
2V/div.
VnSLEEP
2V/div.
VGHA
20V/div.
VGLA
20V/div.
VGLA
20V/div.
VSHA
10V/div.
VSHA
10V/div.
IOUTA
100mA/div.
MP6529 Rev. 1.01
5/28/2019
IOUTA
500mA/div.
VSHA
10V/div.
IOUTA
1A/div.
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8
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PIN FUNCTIONS
QFN-28
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSSOP-28
Pin #
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
Description
VIN
CPA
CPB
VREG
BSTA
SHA
GHA
GLA
BSTB
SHB
GHB
GLB
BSTC
SHC
GHC
GLC
LSS
PWMC
PWMB
PWMA
21
18
ENC
22
19
ENB
23
20
ENA
24
21
nFAULT
25
22
nSLEEP
26
27
28
23
24
25
OC_REF
DT
GND
Input supply voltage.
Charge pump capacitor connect terminal.
Charge pump capacitor connect terminal.
Gate driver supply output.
Bootstrap output phase A.
High-side source connection phase A.
High-side gate drive phase A.
Low-side gate drive phase A.
Bootstrap output phase B.
High-side source connection phase B.
High-side gate drive phase B.
Low-side gate drive phase B.
Bootstrap output phase C.
High-side source connection phase C.
High-side gate drive phase C.
Low-side gate drive phase C.
Low-side source connection.
PWM input for phase C.
PWM input for phase B.
PWM input for phase A.
Enable for phase C. Pull ENC below the specified threshold to disable
the gate driver output for phase C.
Enable for phase B. Pull ENB below the specified threshold to disable
the gate driver output for phase B.
Enable for phase A. Pull ENA below the specified threshold to disable
the gate driver output for phase A.
Fault indication. Open-drain output. nFAULT is in a fault condition at
logic low.
Sleep mode input. Logic low to enter low-power sleep mode; high to
enable. Internal pulldown.
Over-current protection reference input.
Dead time setting.
Ground.
MP6529 Rev. 1.01
5/28/2019
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MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
MP6529 Rev. 1.01
5/28/2019
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MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
OPERATION
The MP6529 is a three-phase, BLDC motor predriver that can drive three half-bridges with a
0.8A source and a 1A sink current capability over
a wide input voltage range of 5V to 35V. It is
designed for use in battery-powered equipment.
The MP6529 features a low-power sleep mode,
which disables the device and draws a very low
supply current.
The MP6529 provides several flexible functions,
such as adjustable dead-time control and overcurrent protection (OCP), which allow the device
to cover a wide range of application fields.
Input Logic
Driving nSLEEP low will put the device into a
low-power sleep state. In this state, all the
internal circuits are disabled, and all inputs are
ignored. nSLEEP has an interval pulldown, so it
must be driven high for the device to operate.
When exiting sleep mode, a brief time period of
approximately 1ms must pass before issuing a
PWM command. This time period allows the
internal circuitry to stabilize.
ENx controls the gate driver outputs of this phase.
When ENx is low, the gate driver outputs are
disabled, and the PWM inputs are ignored. When
ENx is high, the gate driver outputs are enabled,
and the PWM inputs are recognized. Refer to
Table 1 below for the logic truth table.
Table 1: Input Logic Truth Table
ENx
H
H
L
PWMx
H
L
x
SHx
VIN
GND
High impendence
nFAULT
nFAULT reports to the system when a fault
condition is detected, such as OCP and OTP.
nFAULT can be an open-drain output, and is
driven low once a fault condition occurs. If the
fault condition is released, nFAULT is pulled high
by an external pull-up resistor.
Over-Current Protection (OCP)
The MP6529 implements VDS sensing circuitry
to protect the power stage from damage caused
by high currents. Based on the RDS-ON of the
power MOSFETs and the maximum allowed IDS,
a voltage threshold can be calculated, which
MP6529 Rev. 1.01
5/28/2019
triggers the over-current protection (OCP) feature
when exceeded.
This voltage threshold level is programmable
through the OC_REF terminal by applying an
external reference voltage with a DAC. Also,
OCP occurs if the LSS voltage exceeds 0.5V.
Once an OCP event is detected, the MP6529 will
enter a latched fault state and disable all
functions. The MP6529 will stay latched off until it
is reset by nSLEEP or UVLO.
OCP Deglitch Time
Usually, a current spike occurs during the
switching transition due to either the body diode’s
reverse-recovery current or the distributed
inductance or capacitance. This current spike
requires filtering to prevent it from erroneously
triggering OCP and shutting down the external
MOSFET. An internal fixed deglitch time (tOC)
(which is also the minimum on time for the
MOSFET) blanks the output of the VDS monitor
when the outputs are switched.
Dead-Time Adjustment
To prevent a shoot-through at any phase of the
bridge, it is necessary to have a dead time (tDEAD)
between a high- or low-side turn-off and the next
complementary turn-on event. The dead time for
all three phases is set by a single dead-time
resistor (RDT) between DT and ground and is
calculated with Equation (1):
tDEAD(nS) = 3.7*R(kΩ)
(1)
If DT is tied to GND directly, an internal minimum
dead time of 30ns is applied. Leaving DT open
generates a 6µs dead time.
Input UVLO Protection
If at any time the voltage on VIN falls below the
under-voltage lockout threshold voltage, all
circuitry in the device is disabled, and the internal
logic resets. Operation resumes when VIN rises
above the UVLO threshold.
Thermal Shutdown
If the die temperature exceeds its safe limits, the
MP6529 enters a latched fault-state similar to an
OCP event, and nFAULT is driven low. Only a
reset by nSLEEP or UVLO unlatches the device
from an OTP fault lockout.
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11
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PACKAGE INFORMATION
QFN-28 (4mmx4mm)
MP6529 Rev. 1.01
5/28/2019
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12
MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PACKAGE INFORMATION
TSSOP-28 EP (9.7mmx6.4mm)
6.00
TYP
9.60
9.80
0.65
BSC
0.40
TYP
28
15
1.60
TYP
4.30
4.50
PIN 1 ID
3.20
TYP
6.20
6.60
5.80
TYP
14
1
TOP VIEW
RECOMMENDED LAND PATTERN
0.80
1.05
1.20 MAX
SEATING PLANE
0.19
0.30
0.65 BSC
0.00
0.15
0.09
0.20
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
GAUGE PLANE
0.25 BSC
5.40
5.90
0o-8o
DETAIL
2.60
3.10
BOTTOM VIEW
0.45
0.75
A
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AET.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP6529 Rev. 1.01
5/28/2019
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