MP6530
5V to 60V, Three-Phase Brushless
DC Motor Pre-Driver
FEATURES
DESCRIPTION
The MP6530 is a gate driver IC designed for
three-phase brushless DC motor driver
applications. It is capable of driving three half
bridges consisting of 6 N-channel power
MOSFETs up to 60V.
Wide 5V to 60V Input Voltage Range
Charge Pump Gate Drive Supply
Bootstrap High-Side Driver with TrickleCharge Circuit Supports 100% Duty Cycle
Operation
Low-Power Sleep Mode
Programmable Short-Circuit Protection
Over-Current Protection
Adjustable Dead-Time Control to Prevent
Shoot-Through
Thermal Shutdown and UVLO Protection
Fault Indication Output
Thermally
Enhanced
Surface-Mount
Package
The MP6530 integrates a regulated charge
pump to generate gate drive power, and uses a
bootstrap capacitor to generate a supply
voltage for the high-side MOSFET driver. An
internal trickle-charge circuit maintains sufficient
high-side gate driver voltage even when an
output is operated at 100% duty cycle.
Internal
protection
features
include
programmable short-circuit protection, overcurrent protection, adjustable dead-time control,
undervoltage lockout, and thermal shutdown.
APPLICATIONS
The MP6530 is available in 28-pin, 9.7mm ×
6.4mm TSSOP and 4mm x 4mm QFN
packages with an exposed thermal pad.
Three-Phase Brushless DC Motors and
Permanent Magnet Synchronous Motors
Power Drills
Impact Drivers
E-Bike
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP6530
DT
RDEAD
CPA
CPB
0.47uF
10uF
VIN
VREG
VIN
CIN
nFAULT
OCREF
BSTA
nSLEEP
ENA
ENB
To
Phase
C
GHA
SHA
ENC
To
Phase
B
GLA
PWMA
PWMB
LSS
Phase A
(repeat for B and C)
PWMC
GND
MP6530 Rev. 1.13
8/9/2018
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1
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
ORDERING INFORMATION
Part Number
MP6530GR*
Package
QFN-28 (4mm x 4mm)
Top Marking
See Below
MP6530GF**
TSSOP-28 EP
See Below
* For Tape & Reel, add suffix –Z (e.g. MP6530GR–Z)
** For Tape & Reel, add suffix –Z (e.g. MP6530GF–Z)
TOP MARKING (MP6530GR)
MPS: MPS prefix
Y: Year code
WW: Week code
MP6530: Part number
LLLLLL: Lot number
TOP MARKING (MP6530GF)
MPS: MPS prefix
YY: Year code
WW: Week code
MP6530: Part number
LLLLLLLLL: Lot number
MP6530 Rev. 1.13
8/9/2018
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2
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PACKAGE REFERENCE
22 ENB
TOP VIEW
23 ENA
24 nFAULT
nSLEEP
25
DT
27
26 OCREF
GND
28
TOP VIEW
VREG
1
28
CPB
BSTA
2
27
CPA
SHA
3
26
VIN
GHA
4
25
GND
DT
VIN
1
21
ENC
GLA
24
2
5
CPA
20
PWMA
BSTB
6
23
OCREF
CPB
3
19
PWMB
SHB
7
22
nSLEEP
VREG
4
18
PWMC
GHB
8
21
nFAULT
GLB
9
20
ENA
BSTC
10
19
ENB
SHC
11
18
ENC
GHC
12
17
PWMA
GLC
13
16
PWMB
LSS
14
15
PWMC
MP6530
GLC
GHA
7
15
GHC
SHC
BSTC
GLB
GHB
SHB
BSTB
GLA
EXPOSED PAD ON
BACKSIDE
CONNECTED TO GND
14
16
13
6
12
SHA
11
LSS
9
17
10
5
8
BSTA
MP6530
EXPOSED PAD ON
BACKSIDE
CONNECTED TO GND
QFN-28 (4mm x 4mm)
TSSOP-28 EP
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Input Voltage (VIN).......................... -0.3V to 65V
CPA ............................................... -0.3V to 60V
CPB ............................................ -0.3V to 12.5V
VREG ............................................ -0.3V to 13V
BSTA/B/C ...................................... -0.3V to 70V
GHA/B/C ........................................ -0.3V to 70V
GHA/B/C (Transient, 2μS) ................ -8V to 70V
SHA/B/C ........................................ -0.3V to 65V
SHA/B/C (Transient, 2μS) ................. -8V to 65V
GLA/B/C ........................................ -0.3V to 13V
LSS.................................................. -0.3V to 1V
All other pins to AGND .................. -0.3V to 6.5V
(2)
Continuous power dissipation (TA = +25°C)
QFN-28 (4mm x 4mm)……………………2.9W
TSSOP-28 EP ...........................................3.9W
Storage temperature ................ -55C to +150C
Junction temperature ............................. +150C
Lead temperature (solder) ..................... +260C
ESD (Human Body Model)……………….1500V
QFN-28 (4mm x 4mm) ........... 42 ....... 9 .... °C/W
Recommended Operating Conditions
(4)
θJA
θJC
TSSOP-28 EP ........................ 32 ....... 6 .... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will produce an excessive die temperature,
causing the regulator to go into thermal shutdown. Internal
thermal shutdown circuitry protects the device from
permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
(3)
Input voltage (VIN) ............................ +5V to 60V
OCREF voltage (VOC) ................ 0.125V to 2.4V
Operating Junct. temp (TJ) ....... -40C to +125C
MP6530 Rev. 1.13
8/9/2018
www.MonolithicPower.com
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3
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
ELECTRICAL CHARACTERISTICS
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Power Supply
Input supply voltage
Quiescent current
Symbol
VIN
IQ
ISLEEP
Control Logic
Input logic ‘low’ threshold
Input logic ‘high’ threshold
Logic input current
VIL
VIH
IIN(H)
IIN(L)
nSLEEP pull-down current
ISLEEP-PD
RPD
Internal pull-down resistance
nFAULT Output (Open-Drain Output)
VOL
Output low voltage
Output high leakage current
IOH
Protection Circuits
VIN_RISE
UVLO rising threshold
VIN_HYS
UVLO hysteresis
VREG_RISE
VREG rising threshold
VREG_HYS
VREG hysteresis
VREG start-up delay
Short-Circuit Threshold
Accuracy (MOSFET VDS)
OCP deglitch time
SLEEP wakeup time
LSS OCP threshold
Thermal shutdown
MP6530 Rev. 1.13
8/9/2018
Condition
Min
5
nSLEEP = 1, gate not
switching
nSLEEP = 0
VIH = 5V
VIL = 0.8V
0.95
2
-20
-20
IO = 5mA
VO = 3.3V
3.3
6.8
tOC
tSLEEP
VLSS-OCP
TTSD
VOC = 1V, TJ =25°C
VOC = 2.4V, TJ =25°C
Max
Units
60
V
2
mA
1
µA
0.8
20
20
V
V
µA
µA
µA
kΩ
0.5
1
V
µA
4.5
V
mV
V
V
µs
V
V
µs
ms
V
o
C
1
880
All logic inputs except nSLEEP
tREG
VSC
Typ
0.8
2.18
0.4
3.9
200
7.6
0.54
700
1
2.4
3
1
0.5
150
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8.4
1
1.2
2.62
0.6
4
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Gate Drive
Symbol
Bootstrap diode forward voltage
VFBOOT
Condition
ID = 10mA
ID = 100mA
VIN = 5.5V-60V
VIN = 5V
Min
10
2xVIN-1
Typ
Max
Units
V
V
11.5
0.9
1.3
12.8
VREG output voltage
VREG
Maximum source current
Maximum sink current
Gate drive pull-up resistance
HS gate drive pull-down
resistance
LS gate drive pull-down
resistance
LS passive pull-down
resistance
LS automatic turn-on time
Charge pump frequency
IOSO
(5)
IOSI
RUP
VDS = 1V
RHS-DN
VDS = 1V
1.2
4.7
Ω
RLS-DN
VDS =1V
1
5.5
Ω
Dead time
(5)
RLS-PDN
tLS
At ENx rising edge
fCP
tDEAD
DT open
RDT = 200kΩ
DT tied to GND
V
A
A
Ω
0.8
1
8
590
kΩ
1.8
110
6
0.74
30
µs
kHz
µs
µs
ns
NOTE:
5) Guaranteed by design – not tested in production
MP6530 Rev. 1.13
8/9/2018
www.MonolithicPower.com
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5
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
TYPICAL CHARACTERISTICS
MP6530 Rev. 1.13
8/9/2018
www.MonolithicPower.com
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6
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 24V, OCREF = 0.5V, RDT = 200k, ENA = ENC = H, fPWMA = 20kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
MP6530 Rev. 1.13
8/9/2018
www.MonolithicPower.com
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7
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 24V, OCREF = 0.5V, RDT = 200k, ENA = ENC = H, fPWMA = 20kHz, TA = 25°C,
resistor + inductor load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
MP6530 Rev. 1.13
8/9/2018
www.MonolithicPower.com
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8
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PIN FUNCTIONS
QFN
Pin #
TSSOP
Pin #
Name
1
26
VIN
2
3
27
28
CPA
CPB
4
1
VREG
5
2
BSTA
6
7
8
3
4
5
SHA
GHA
GLA
9
6
BSTB
10
11
12
7
8
9
SHB
GHB
GLB
13
10
BSTC
14
15
16
17
11
12
13
14
SHC
GHC
GLC
LSS
18
15
PWMC
19
16
PWMB
20
17
PWMA
21
18
ENC
22
19
ENB
23
20
ENA
24
21
nFAULT
25
22
nSLEEP
26
23
OCREF
27
24
DT
28
25
GND
MP6530 Rev. 1.13
8/9/2018
Description
Input supply voltage. Bypass to ground with a ceramic capacitor. Additional
bulk capacitance may be required. See Applications Information section.
Charge pump capacitor. Connect a ceramic capacitor between these pins.
See Applications Information section.
Gate drive supply output. Connect a ceramic capacitor to ground. See
Applications Information section.
Bootstrap phase A. Connect a ceramic capacitor to SHA.
See Applications Information section.
High-side source connection phase A.
High-side gate drive phase A.
Low-side gate drive phase A.
Bootstrap phase B. Connect a ceramic capacitor to SHB.
See Applications Information section.
High-side source connection phase B.
High-side gate drive phase B.
Low-side gate drive phase B.
Bootstrap phase C. Connect a ceramic capacitor to SHC.
See Applications Information section.
High-side source connection phase C.
High-side gate drive phase C.
Low-side gate drive phase C.
Low-side Source Connection.
PWM input pin for phase C. High drivers phase C high; low drivers phase C
low. Internal pulldown.
PWM input pin for phase B. High drivers phase B high; low drivers phase B
low. Internal pulldown.
PWM input pin for phase A. High drivers phase A high; low drivers phase A
low. Internal pulldown.
Enable pin for phase C. Active high enables the gate driver for phase C; low
disables the gate driver for phase C. Internal pulldown.
Enable pin for phase B. Active high enables the gate driver for phase B; low
disables the gate driver for phase B. Internal pulldown..
Enable pin for phase A. Active high enables the gate driver for phase A; low
disables the gate driver for phase A. Internal pulldown.
Fault indication. Open-drain output. nFAULT is logic low when in a fault
condition.
Sleep mode input. Logic low to enter low-power sleep mode; high to enable.
Internal pulldown.
Over-current protection reference voltage input.
Dead time setting. Connect a resistor to ground to set the dead time. See
Applications Information section.
Ground.
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9
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
FUNCTIONAL BLOCK DIAGRAM
CPB
CPA
nSLEEP
ENA
ENB
ENC
PWMA
PWMB
PWMC
VIN
VIN
Charge
Pump
Timing and
Control
Logic
VREG
Trickle
Charge
BSTA
HS Gate
Drive
DT
Phase A,
repeat for
B&C
GHA
SHA
RDT
VREG
TSD
UVLO
VIN
VREG
LS Gate
Drive
SC
Comparator
nFAULT
OCREF
Fault
Handling
LSS
VDS
Monitor
GND
VIN
OCP
Comparator
GLA
RSENSE
0.5V
Figure 1: Functional Block Diagram
MP6530 Rev. 1.13
8/9/2018
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10
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
OPERATION
Sleep Mode (nSLEEP Input)
The MP6530 is a three-phase BLDC motor predriver that drives three external N-channel
MOSFET half bridges, with 0.8A source and 1A
sink current capability. It operates over a wide
input voltage range of 5V to 60V, generating a
boosted gate drive voltage when the input supply
is below 12V. The MP6530 features a low-power
sleep mode, which disables the device and
draws a very low supply current.
Driving nSLEEP low will put the device into a
low-power sleep state. In this state, all the
internal circuits are disabled, and all inputs are
ignored. nSLEEP has an interval pulldown, so it
must be driven high for the device to operate.
The MP6530 provides several flexible functions,
such as adjustable dead-time control and overcurrent protection, which allow the device to
cover a wide range of applications.
Power-Up Sequence
The power-up sequence is initiated by the
application of voltage to VIN pin. To initiate
power-up, VIN must be above the undervoltage
lockout threshold VUVLO.
After power-up begins, the VREG supply starts
operating. VREG must rise above VREG_RISE
before the device becomes functional.
The power-up process takes between 1mS and
2mS, after which the MP6530 will respond to
logic inputs and drive the outputs.
Gate Drive Power Supplies
Gate drive voltages are generated from the input
power, VIN. A regulated charge pump doubler
circuit supplies a voltage of approximately 11.5V
at the VREG pin. This voltage is used for the lowside gate drive supply. The charge pump
requires external capacitors between the CPA
and CPB pins, and from VREG to ground.
The high side gate drive is generated by a
combination of a bootstrap capacitor and an
internal “trickle” charge pump. Bootstrap
capacitors are charged to the VREG voltage
when the low side MOSFET is turned on. This
charge is then used to drive the high side
MOSFET gate when it is turned on.
To keep the bootstrap capacitors charged and
allow operation at 100% duty cycle, an internal
“trickle” charge pump supplies a small current
(about 5µA) to overcome leakages that would
discharge the bootstrap capacitors.
When exiting sleep mode, the part will initiate the
power-up sequence described above.
Input Logic
The ENx input pins controls both the high- and
low-side gate drive outputs of each phase. When
ENx is low, the gate drive outputs are pulled low,
and the PWMx input of that phase is ignored.
When ENx is high, the gate drive outputs are
enabled, and the PWM input is recognized. Refer
to Table 1 for the logic truth table.
Table 1: Input Logic Truth Table
ENx
H
H
L
PWMx
H
L
x
SHx
VIN
GND
High impedance
Low-side Automatic Turn-on
To ensure that the bootstrap capacitor is charged
enough to turn on the high-side MOSFET, each
time that the ENx pin transitions from low to
active high, the low-side MOSFET for that phase
is turned on for a short pulse (tLS). This occurs
regardless of the state of the PWMx input pin.
nFAULT
The nFAULT output pin reports to the system
when a fault condition (such as an output short
circuit, overcurrent, or overtemperature) is
detected. nFAULT is an open-drain output, and it
is driven low when a fault condition occurs. If the
fault condition is released, nFAULT is pulled high
by an external pull-up resistor.
Short Circuit Protection (VDS Sensing)
To protect the power stage from damage due to
high currents, a VDS sensing circuitry is
implemented in the MP6530. The voltage drop
across each MOSFET is sensed. (This voltage is
proportional to the RDS-ON of the MOSFET and
the IDS current passing through it). If this voltage
exceeds the voltage supplied to the OCREF
terminal, a short circuit is recognized.
Refer to the applications information section for
details on the selection of external components.
MP6530 Rev. 1.13
8/9/2018
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11
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
In the event of a short circuit, the MP6530
disables all of the gate drive outputs. nFAULT is
driven active low. The device will stay latched off
until it is reset by nSLEEP or VIN UVLO.
If DT is tied to directly to ground, an internal
minimum dead time (30ns) will be applied.
Leaving DT open generates approximately a 6µs
dead time.
Short circuit protection can be disabled by
connection a 100kΩ resistor from VREG to the
OCREF pin.
UVLO Protection
If at any time the voltage on VIN falls below the
undervoltage lockout threshold VIN_RISE, all
circuitry in the device is disabled and the internal
logic will be reset.
Over-current Protection (OCP)
The MP6530 can implement output overcurrent
protection (OCP) by monitoring the current
through a low-side shunt resistor connected to
the low-side MOSFETs.
This resistor is
connected to the LSS input pin and the low-side
MOSFET source terminals. If the OCP function
is not desired, the LSS pin and MOSFET source
terminals should all be connected directly to
ground.
If the LSS voltage (the voltage across the shunt
resistor) exceeds the LSS OCP threshold voltage
VLSS-OCP, an OCP event is recognized. Once an
OCP event is detected, the MP6530 will enter a
latched fault state and disable all functions. The
device will stay latched off until it is reset by
nSLEEP or VIN UVLO.
Operation will resume with the power-up
sequence when VIN rises above the UVLO
thresholds.
After power-up, if the voltage on VREG drops
below the VREG_RISE threshold, the MP6530 will
enter a latched fault state and disable all
functions. The nFAULT pin will be driven active
low. The device will stay latched off until it is
reset by nSLEEP or VIN UVLO.
Thermal Shutdown
If the die temperature exceeds safe limits, the
MP6530 will enter a latched fault state and
disable all functions. The device will stay latched
off until it is reset by nSLEEP or VIN UVLO.
The OCP current limit level is selected by the
value of the current sense resistor at LSS pin.
Refer to the applications information section for
more information.
OCP protection can be disabled by connection a
100kΩ resistor from VREG to the OCREF pin.
Short-circuit and OCP Deglitch Time
There is often a current spike during switching
transitions, due to body diode reverse-recovery
current or the distributed capacitance of the load.
This current spike requires filtering to prevent it
from erroneously triggering OCP. An internal
fixed deglitch time (tOC) blanks the output of the
VDS monitor when the outputs are switched.
Dead-Time Adjustment
To prevent shoot-through in any phase of the
bridge, it is necessary to have a dead time (tDEAD)
between a high- or low-side turn-off and the next
complementary turn-on event. The dead time for
all three phases is set by a single dead-time
resistor (RDT) between DT and ground with
Equation (1):
tDEAD(nS) = 3.7*R(kΩ)
(1)
MP6530 Rev. 1.13
8/9/2018
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12
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
APPLICATIONS INFORMATION
VIN Input Voltage
The VIN pin supplies all power to the device. It
must be properly bypassed with a capacitor to
ground
–
see
below
for
specific
recommendations.
The normal operating range of VIN is between
5V and 60V.
VIN should never be allowed to exceed the
absolute maximum ratings, even in a short term
transient condition, or damage to the device may
result. In some cases – especially where
mechanical energy can turn a motor into a
generator – it may be necessary to use some
form of overvoltage protection, such as a TVS
diode, between VIN and ground.
Component Selection
MOSFET selection
Correctly selecting the power MOSFETs used to
drive a motor is crucial to designing a successful
motor drive.
The first requirement is that the MOSFET must
have a VDS breakdown voltage that is higher
than the supply voltage. It is recommended that
considerable margin – 10-15 volts - be added to
prevent MOSFET damage from transient
voltages that can be caused by parasitic
inductances in the PCB layout and wiring. For
example, for 24V power supply applications,
MOSFETs having a breakdown voltage of 40V60V minimum are recommended. More margin is
desirable in high current applications, as the
transients caused by parasitic inductances may
be larger. Also, there are conditions like
regenerative braking that can inject current back
into the power supply; care must be taken that
this does not cause an increase in the power
supply voltage large enough to damage
components.
The MOSFETs must be able to safely pass the
current needed to run the motor. The highest
current condition, which is normally when the
motor is first started or stalled, needs to be
supported. This is typically called the “stall
current” of the motor.
MP6530 Rev. 1.13
8/9/2018
Related to the current capability of the MOSFET
is the rds(on). This is the resistance of the
MOSFET when it is in the fully “turned on” state.
The MOSFET will dissipate power proportional to
the rds(on) and the motor current: P=I2R. The
rds(on) needs to be selected so that for the
desired motor current, the heat generated in this
power can be safely dissipated. In some cases,
this may require special PCB design
considerations and/or external heatsinks to be
used for the MOSFETs.
Some consideration should be made for the safe
operating area (SOA) of the MOSFETs in fault
conditions, such as a short circuit. The IC will act
quickly in the event of a short, but there is still a
very short time (on the order of 3µS) where large
currents can flow in the MOSFETs while the
protection circuits recognize the fault and disable
the outputs.
External Capacitor Selection
The MP6530 has a unique feature in that it can
provide a gate drive voltage (VREG) of 10-12V
even if the input supply voltage drops as low as
5V. This gate drive voltage is generated by a
charge pump inside the part, which uses external
capacitors.
The charge pump flying capacitor, CCP, should
have a capacitance of 470nF. It needs to be
rated to withstand the maximum VIN power
supply voltage. An X7R or X5R ceramic capacitor
is recommended. With a 470nF capacitor, VREG
can output approximately 10mA when VIN is 5V.
If operation below 10V is not needed, a 220nF
capacitor can be used
To provide the large peak currents needed to
turn on the HS MOSFET, bootstrap capacitors
are used. These capacitors are charged when
the output is driven low, then the charge in the
bootstrap capacitor is used to turn on the HS
MOSFET when the output is driven high. (Note
that an internal charge pump will keep the
bootstrap capacitor changed when the output is
held high for an extended period).
The bootstrap capacitors are selected depending
on the MOSFET total gate charge. When the HS
MOSFET is turned on, the charge stored in the
bootstrap capacitor is transferred to the HS
MOSFET gate. As a simplified approximation, the
minimum bootstrap capacitance can be
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MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
estimated as CBOOT > 8*QG, where QG is the total
gate charge of the MOSFET in nC, and CBOOT is
in nF. The bootstrap capacitors should not
exceed 1µF, or they may cause improper
operation at start-up.
For most applications, bootstrap capacitors
between 0.1µF and 1µF, X5R or X7R ceramic,
rated for 25V minimum, are recommended.
The VREG pin requires a bypass capacitor to
ground of 10µF. This should be an X7R or X5R
ceramic capacitor rated for 16V minimum.
VIN requires a bypass capacitor to ground,
placed as close as possible to the device. At a
minimum, a 0.1µF X5R or X7R ceramic capacitor,
rated for the VIN voltage, is recommended.
conditions that the HS and LS MOSFETs are
never turned on at the same time.
Dead time can be set over a large range, by
selecting the value of the external resistor that is
connected to the DT pin. Usually, a good starting
point is a dead time of about 1µS, which requires
a 200k resistor on the DT pin. If faster switching
and/or a high PWM frequency (over ~30kHz) is
used, shorter dead time may be desirable; if
switching is slowed using external gate resistors,
longer dead time may be needed.
The waveform below shows about a 300nS dead
time between the LS gate turn-off and the HS
gate turn-on.
Depending on the power supply impedance and
the distance between the MOSFETs and the
power supply, additional bulk capacitance is
usually needed. Between 47µF and 470µF of low
ESR electrolytic capacitors are typically used.
Dead Time Resistor Selection
During the transition between driving an output
low and high, there is a short period when neither
the HS nor LS MOSFET is turned on. This
period, called “dead time”, is needed to prevent
any overlap in conduction between HS and LS
MOSFETs, which would effectively provide a
short-circuit directly between the power supply
and ground. This condition, referred to as “shootthrough”, causes large transient currents, and
can destroy the MOSFETs.
Since motors are inductive by nature, once
current is flowing in the motor, it cannot stop
immediately, even if the MOSFETs are turned off.
This “recirculation current” continues to flow in
the original direction until the magnetic field has
decayed.
When the MOSFETs are turned off, this current
will flow through the “body diode” which is
inherent in the MOSFET device.
MOSFET body diodes have a much higher
voltage drop than the MOSFET has during
conduction, so there more power dissipated in
body diode conduction than during the on time.
Because of this, it is desirable to minimize the
dead time. However, the dead time must be
made large enough to guarantee under all
MP6530 Rev. 1.13
8/9/2018
LSS Resistor Selection
If the voltage applied to the LSS pin ever
exceeds 500mV, an overcurrent event will be
recognized. The external sense resistor is sized
to provide less than 500mV drop at the maximum
expected motor current. For example, if a 50 mΩ
resistor is used, a current of 10 amps would
cause a 500mV drop, and activate the
overcurrent protection.
If this function is not needed, connect LSS
directly to ground.
OCREF Voltage Selection
An internal comparator compares the voltage
drop across each MOSFET with a voltage that is
externally provided on the OCREF input pin.
This voltage is normally provided by an external
resistor divider from a convenient power supply.
If the drop across any MOSFET ever exceeds
the voltage on the OCREF pin, a short-circuit
event is recognized.
If this function is not needed, connect OCREF to
VREG through a 100k resistor.
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14
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
Gate Drive Considerations
The gate characteristics of the selected
MOSFETs will affect how fast they will be
switched and off. The gate drive outputs of the
device can be connected directly to the gates of
the power MOSFETs, which results in the fastest
possible turn-on and turn-off times. However, it
may be advantageous to add external
components (resistors and/or diodes) to modify
the MOSFET turn-on and turn-off characteristics.
Adding external series resistance – typically
between 10 and 100 ohms – will limit the current
that charges and discharges the gate of the
MOSFET, which will slow down the turn-on and
turn-off times. Sometimes this is desirable to
control EMI and noise. Slowing the transition
down too much, however, results in large power
dissipation in the MOSFET during switching.
In some cases, it is desirable to have a slow turnon, but a fast turn-off. This can be implemented
by using a series resistor in parallel with a diode.
At turn-on, the resistor limits the current flow into
the gate; at turn-off, the gate is discharged
quickly through the diode.
This waveform shows the effect of adding a
100Ω series resistor between the GLA and GLH
pins and the MOSFET gates. Rise time on the
phase node has been slowed significantly. The
scale here is 200nS/div.
This waveform shows the effect of adding a
1N4148 diode in parallel with the 100Ω resistors
(with the cathode connected to the IC). You can
see that the fall time of the LS gate is quite fast
compared to the HS gate rise time. The phase
node moves even slower, because of a longer
period of time between when the LS FET is
turned off, and the HS FET is turned on.
1N4148
RGHS
1N4148
RGLS
This waveform below shows the gates of the LS
and HS MOSFETs, and the phase node (output)
with no series resistance. You can see that the
gates transition quickly. The resulting rise time on
the phase node is quite fast. Note the scale of
100nS/div.
PCB Layout
Proper PCB layout is critical to the performance
of MOSFET gate drivers. In particular, the
connection between the HS source and LS drain
needs to be as direct as possible, to avoid
negative undershoot on the phase node due to
parasitic inductances. The pre-driver is designed
to accommodate negative undershoot, but if it is
excessive, unpredictable operation or damage to
the IC can result.
An example PCB layout is shown below. It uses
surface mount N-channel MOSFETs, which
allows very short connection between the HS and
MP6530 Rev. 1.13
8/9/2018
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MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
LS MOSFETs. You can also see the use of wide
copper areas for all of the high current paths.
The low-side sense resistor is composed of three
resistors in parallel (R25, R26, and R27), and is
connected to the input supply and LS MOSFET
source terminals by wide copper areas.
MP6530 Rev. 1.13
8/9/2018
Note the location of the charge pump and supply
bypass capacitors, very close to the IC. The
grounded side of these capacitors is connected
to a ground plane, which is connected to the
device ground pin and exposed pad. The highcurrent ground path between the input supply,
input bulk capacitor C19, and MOSFETs is kept
away from this area.
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16
MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PACKAGE INFORMATION
QFN-28 (4mm × 4mm)
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
PIN 1 ID INDEX
AREA
BOTTOM VIEW
TOP VIEW
PIN 1 ID OPTION A
0.30x45° TYP.
SIDE VIEW
PIN 1 ID OPTION B
R0.25 TYP.
DETAIL A
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS
MAX.
4) DRAWING CONFORMS TO JEDEC MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP6530 Rev. 1.13
8/9/2018
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MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER
PACKAGE INFORMATION
TSSOP-28 EP
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP6530 Rev. 1.13
8/9/2018
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