MP6534
5V to 55V, Three-Phase, Brushless
DC Motor Pre-Driver with Buck Regulator
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP6534 is a gate driver IC designed for
three-phase brushless DC motor driver
applications. It is capable of driving three half
bridges consisting of 6 N-channel power
MOSFETs up to 55V. The MP6534 includes a
500mA buck regulator to generate local power
for microcontrollers or other circuitry.
The MP6534 integrates a regulated charge
pump to generate gate drive power, and uses a
bootstrap capacitor to generate a supply
voltage for the high-side MOSFET driver. An
internal trickle-charge circuit maintains sufficient
high-side gate driver voltage even when an
output is operated at 100% duty cycle.
Wide 5V to 55V Input Voltage Range
Charge Pump Gate Drive Supply
Bootstrap High-Side Driver with TrickleCharge Circuit Supports 100% Duty Cycle
Operation
500mA Buck Regulator
Low-Power Sleep Mode
Programmable Short-Circuit Protection
Over-Current Protection
Adjustable Dead-Time Control to Prevent
Shoot-Through
Thermal Shutdown and UVLO Protection
Fault Indication Output
Thermally
Enhanced
Surface-Mount
Package
Internal
protection
features
include
programmable short-circuit protection, overcurrent protection, adjustable dead-time control,
undervoltage lockout, and thermal shutdown.
APPLICATIONS
The MP6534 is available in a 40-contact QFN
(5mm x 5mm) package with an exposed
thermal pad.
3-Phase, Brushless DC Motors and
Permanent Magnet Synchronous Motors
Power Drills
E-Bikes
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
VIN
RIN
MP6534
RBST
VB
RSW
RFB
REN
nFAULT
nSLEEP
ENA
ENB
CPA
CPB
VREG
BSTA
VIN
ENC
PWMA
PWMB
PWMC
GHA
To Phase C
SHA
To Phase B
GLA
OCREF
LSS
Phase A
(repeat for B and C)
DT
RDEAD
MP6534 Rev. 1.13
10/24/2018
GND
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
1
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP6534GU
QFN-40 (5mmx5mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP6535GU–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP6534: Part number
LLLLLLL: Lot number
PACKAGE REFERENCE
QFN-40 (5mmx5mm)
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
2
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
ABSOLUTE MAXIMUM RATINGS (1)
Input voltage (VIN) ........................... -0.3V to 65V
Input voltage (VRIN) .......................... -0.3V to 60V
RSW ..................................... -0.3V to VRIN +0.3V
RBST ................................................... VRSW + 6V
CPA ................................................. -0.3V to 60V
CPB .............................................. -0.3V to 12.5V
VREG .............................................. -0.3V to 13V
BSTA/B/C ........................................ -0.3V to 70V
GHA/B/C ......................................... -0.3V to 70V
GHA/B/C (Transient, 2μS) ................. -8V to 70V
SHA/B/C .......................................... -0.3V to 60V
SHA/B/C (Transient, 2μS) ................. -8V to 65V
GLA/B/C .......................................... -0.3V to 13V
ESD rating (HBD).......................................... 2kV
All other pins to AGND ................... -0.3V to 6.5V
Continuous power dissipation (TA = +25°C) (2)
QFN-40 (5mmx5mm)……………….…...3.47W
Storage temperature .................-55C to +150C
Junction temperature .............................. +150C
Lead temperature (solder) ...................... +260C
ESD (Human Body Model)……………….1500V
MP6534 Rev. 1.13
10/24/2018
Recommended Operating Conditions (3)
Input voltage (VIN, VRIN) ..................... +5V to 55V
OCREF voltage (VOC) ............... +0.125V to 2.4V
Operating junction temp. (TJ) ....-40C to +125C
Thermal Resistance (4)
θJA
θJC
QFN-40 (5mmx5mm) .............. 36 ........ 8 .... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
3
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
ELECTRICAL CHARACTERISTICS (MOTOR PRE-DRIVER)
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Power Supply
Input supply voltage
Quiescent current
Control Logic
Input logic low threshold
Input logic high threshold
Logic input current
Symbol
VIN
IQ
ISLEEP
VIL
VIH
IIN(H)
IIN(L)
nSLEEP pull-down current
ISLEEP-PD
RPD
Internal pull-down resistance
Fault Outputs (Open-Drain Outputs)
Output low voltage
VOL
Output high leakage current
IOH
Protection Circuit
VIN_RISE
UVLO rising threshold
VIN_HYS
UVLO hysteresis
V
VREG rising threshold
REG_RISE
VREG_HYS
VREG hysteresis
VREG start-up delay
tREG
Short-Circuit Threshold
VSC
Accuracy (MOSFET VDS)
OCP deglitch time
tOC
SLEEP wake-up time
tSLEEP
LSS OCP threshold
VLSS-OCP
Thermal shutdown
TTSD
MP6534 Rev. 1.13
10/24/2018
Condition
Min
Typ
5
nSLEEP = 1,
gate not switching
nSLEEP = 0
VIH = 5V
VIL = 0.8V
0.95
2
-20
-20
Units
55
V
2
mA
1
µA
0.8
20
20
V
V
µA
µA
µA
kΩ
0.5
1
V
µA
4.5
V
mV
V
V
µs
V
V
µs
ms
V
oC
1
880
All logic inputs except nSLEEP
IO = 5mA
VO = 3.3V
3.3
6.8
VOC = 1V
VOC = 2.4V
Max
0.8
2.18
0.4
3.9
200
7.6
0.54
800
1
2.4
3
1
0.5
150
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
8.4
1
1.2
2.62
0.6
4
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
ELECTRICAL CHARACTERISTICS (MOTOR PRE-DRIVER) (continued)
VIN = 24V, TA = 25°C, unless otherwise noted.
Parameter
Gate Drive
Symbol
Bootstrap diode forward voltage
VFBOOT
Condition
ID = 10mA
ID = 100mA
VIN = 5.5V - 55V
VIN = 5V
Min
10
2xVIN-1
Typ
11.5
Max
Units
0.9
1.3
12.8
V
V
VREG output voltage
VREG
Maximum source current
Maximum sink current
Gate drive pull-up resistance
HS gate drive pull-down
resistance
LS gate drive pull-down
resistance
LS passive pull-down
resistance
LS automatic turn-on time
Charge pump frequency
IOSO
IOSI(5)
RUP
VDS = 1V
RHS-DN
VDS = 1V
1.2
4.7
Ω
RLS-DN
VDS = 1V
1
5
Ω
Dead time
RLS-PDN
tLS
fCP
tDEAD
At ENx rising edge
Leave DT open
RDT = 200kΩ
DT tied to GND
V
A
A
Ω
0.8
1
8
(5)
590
kΩ
1.8
110
6
0.74
30
µs
kHz
µs
µs
ns
NOTE:
5) Guaranteed by design – not tested in production
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
5
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
ELECTRICAL CHARACTERISTICS (BUCK REGULATOR)
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameters
Symbol Condition
Feedback voltage
VFB
Feedback current
IFB
Switch-on resistance
RDS(ON)
Switch leakage
ISW_LKG
Typ
Max
Units
0.792
0.812
0.832
V
0.1
μA
VRFB = 0.85V
1
VREN = 0V,
VRSW = 0V
Current limit
ILIM
Oscillator frequency
fSW
VFB = 0.6V
Foldback frequency
fSW_F
VRFB = 0V
Maximum duty cycle
DMAX
VRFB = 0.6V
Minimum on time
Min
Ω
1
μA
1.0
1.25
1.5
A
330
450
570
kHz
90
τON
135
kHz
93.5
%
100
ns
Under-voltage lockout threshold rising
VUVLO_R
2.9
3.3
3.7
V
Under-voltage lockout threshold falling
VUVLO_F
2.55
3.05
3.45
V
Under-voltage lockout threshold hysteresis
VUVLO_HYS
320
mV
REN threshold rising
VEN_R
1.35
V
REN threshold falling
VEN_F
1.17
V
VEN_HYS
180
mV
REN threshold hysteresis
VREN = 2V
3.1
VREN = 0V
0.1
IS
VREN = 0V
0.1
1.0
μA
IQ
VREN = 2V, VFB = 1V
0.73
0.85
mA
REN input current
IEN
Supply current (shutdown)
Supply current (quiescent)
Thermal shutdown
Thermal shutdown hysteresis
MP6534 Rev. 1.13
10/24/2018
μA
TSD
165
°C
TSD_HYS
20
°C
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
6
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
TYPICAL CHARACTERISTICS
Motor Pre-Driver
4.4
7.8
2.43
4.3
7.78
2.425
7.76
4.2
2.42
7.74
7.72
2.415
4
7.7
2.41
3.9
7.68
2.405
4.1
7.66
3.8
3.6
-50
2.4
7.64
3.7
2.395
7.62
-20
10
40
70 100 130
7.6
-50
-20
10
40
70 100 130
2.39
-50
-20
10
40
70 100 130
0.505
0.504
0.503
0.502
0.501
0.5
0.499
0.498
0.497
0.496
0.495
-50
-20
MP6534 Rev. 1.13
10/24/2018
10
40
70 100 130
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
7
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
TYPICAL CHARACTERISTICS (continued)
Buck Regulator
Current Limit vs.
Temperature
1.7
1.4
1.1
0.8
0.5
-40 -10
MP6534 Rev. 1.13
10/24/2018
20
50
80 110 140
Feedback Voltage vs.
Temperature
600
850
560
830
VFB VOLTAGE ( mV )
SWITCHING FREQUENCY ( kHz )
CURRRENT LIMIT ( A )
2.0
Frequency vs. Temperature
520
480
440
400
-40 -10
20
50
80 110 140
810
790
770
750
-40 -10
20
50
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
80 110 140
8
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
Motor Pre-Driver
VIN = 24V, OC_REF = 0.5V, RDT = 200k, ENA = ENC = H, FPWMA = 20kHz, TA = 25°C,
Resistor + Inductor Load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
Steady State
Steady State
Duty=10%
Steady State
Duty=50%
Duty=90%
VGHA
20V/div.
VGHA
20V/div.
VGHA
20V/div.
VGLA
10V/div.
VGLA
10V/div.
VGLA
10V/div.
VSHA
20V/div.
VSHA
20V/div.
IOUTA
100mA/div.
VSHA
20V/div.
IOUTA
500mA/div.
IOUTA
500mA/div.
Power Ramp Up
Power Ramp Up
Power Ramp Up
Duty=10%
Duty=50%
Duty=90%
VIN
10V/div.
VGHA
20V/div.
VIN
10V/div.
VGHA
20V/div.
VSHA
20V/div.
VSHA
20V/div.
IOUTA
100mA/div.
IOUTA
500mA/div.
VIN
10V/div.
VGHA
20V/div.
VSHA
20V/div.
IOUTA
1A/div.
Sleep Recovery
Sleep Recovery
Sleep Recovery
Duty=10%
Duty=50%
Duty=90%
VnSLEEP
2V/div.
VGHA
20V/div.
VnSLEEP
2V/div.
VGHA
20V/div.
VnSLEEP
2V/div.
VGHA
20V/div.
VSHA
20V/div.
VSHA
20V/div.
VSHA
20V/div.
IOUTA
100mA/div.
IOUTA
500mA/div.
IOUTA
1A/div.
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
9
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Motor Pre-Driver
VIN = 24V, OC_REF = 0.5V, RDT = 200k, ENA = ENC = H, FPWMA = 20kHz, TA = 25°C,
Resistor + Inductor Load: 5Ω + 1mH/phase with star connection, unless otherwise noted.
Sleep Entry
Sleep Entry
Duty=10%
Sleep Entry
Duty=50%
Duty=90%
VnSLEEP
2V/div.
VnSLEEP
2V/div.
VnSLEEP
2V/div.
VGHA
20V/div.
VGLA
20V/div.
VGLA
20V/div.
VSHA
10V/div.
VSHA
10V/div.
IOUTA
100mA/div.
MP6534 Rev. 1.13
10/24/2018
IOUTA
500mA/div.
VSHA
10V/div.
IOUTA
1A/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
10
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
Buck Regulator
VIN = 12V, VOUT = 5V, L = 22μH, TA = 25°C, unless otherwise noted.
Steady State
Steady State
Load Transient
VIN=8V, IOUT=0.8A
IOUT=0.15A
IOUT=0.2A to 0.7A
VIN
5V/div.
VIN
10V/div.
VSW
5V/div.
VSW
10V/div.
VOUT
5V/div.
VOUT
5V/div.
IL
500mA/div.
IL
1A/div.
VIN
10V/div.
VSW
10V/div.
VOUT
200mV/div.
IL
500mA/div.
Steady State
Steady State
Load Transient
VIN=6V, VOUT=3.3V, IOUT=0.1A
VIN=60V, VOUT=3.3V, IOUT=0.9A
VOUT=3.3V, IOUT=0.2A to 0.7A
VIN
5V/div.
VIN
50V/div.
VSW
5V/div.
VSW
50V/div.
VOUT
2V/div.
IL
200mA/div.
VOUT
2V/div.
VIN
10V/div.
VSW
10V/div.
VOUT
200mV/div.
IL
500mA/div.
IL
1A/div.
Power Ramp Up
Power Ramp Down
Short Output
VIN=60V, IOUT=0.5A
VIN=60V, IOUT=0.5A
IOUT=0.65A
VIN
50V/div.
VIN
50V/div.
VSW
50V/div.
VSW
50V/div.
VOUT
5V/div.
VOUT
5V/div.
IOUT
500mA/div.
IOUT
500mA/div.
MP6534 Rev. 1.13
10/24/2018
VIN
10V/div.
VSW
10V/div.
VOUT
5V/div.
IL
1A/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
11
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Buck Regulator
VIN = 12V, VOUT = 5V, L = 22μH, TA = 25°C, unless otherwise noted.
Enable On
Enable Off
Short Output Recovery
IOUT=0.5A
IOUT=0.5A
IOUT=0.65A
VEN
2V/div.
VEN
2V/div.
VIN
10V/div.
VSW
10V/div.
VSW
10V/div.
VSW
10V/div.
VOUT
5V/div.
VOUT
5V/div.
VOUT
5V/div.
IL
500mA/div.
IL
500mA/div.
IL
1A/div.
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
12
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
PIN FUNCTIONS
Pin #
1, 26,
30, 36
Name
2
BSTC
3
4
5
6
SHC
GHC
GLC
LSS
7
PWMC
8
PWMB
9
PWMA
10
ENC
11
ENB
12
ENA
13
nFAULT
14
nSLEEP
15
OCREF
16
DT
17, 34
GND
18
VIN
19
20
CPA
CPB
21
VREG
22
BSTA
23
24
25
27
28, 29
31, 32
SHA
GLA
GHA
RBST
RSW
RIN
33
RFB
35
REN
37
BSTB
38
39
40
SHB
GHB
GLB
NC
MP6534 Rev. 1.13
10/24/2018
Description
Not connected.
Bootstrap phase C. Connect a ceramic capacitor to SHC.
See Applications Information section.
High-side source connection phase C.
High-side gate drive phase C.
Low-side gate drive phase C.
Low-side source connection.
PWM input pin for phase C. High drives phase C high; low drives phase C low.
Internal pulldown.
PWM input pin for phase B. High drives phase B high; low drives phase B low.
Internal pulldown.
PWM input pin for phase A. High drives phase A high; low drives phase A low.
Internal pulldown.
Enable pin for phase C. Active high enables the gate driver for phase C; low disables
the gate driver for phase C. Internal pulldown.
Enable pin for phase B. Active high enables the gate driver for phase B; low disables
the gate driver for phase B. Internal pulldown..
Enable pin for phase A. Active high enables the gate driver for phase A; low disables
the gate driver for phase A. Internal pulldown.
Fault indication. Open-drain output. nFAULT is logic low when in a fault condition.
Sleep mode input. Logic low to enter low-power sleep mode; high to enable. Internal
pulldown.
Over-current protection reference input.
Dead time setting. Connect a resistor to ground to set the dead time. See
Applications Information section.
Ground.
Input supply voltage. Bypass to ground with a ceramic capacitor. Additional bulk
capacitance may be required. See Applications Information section.
Charge pump capacitor. Connect a ceramic capacitor between these pins. See
Applications Information section.
Gate drive supply output. Connect a ceramic capacitor to ground. See Applications
Information section.
Bootstrap phase A. Connect a ceramic capacitor to SHA.
See Applications Information section.
High-side source connection phase A.
Low-side gate drive phase A.
High-side gate drive phase A.
Buck regulator boost. Connect a ceramic capacitor between RSW and RBST.
Buck regulator switch output.
Buck regulator input (normally connected to VIN).
Buck regulator feedback input. RFB sets the buck regulator output voltage. Connect
RFB to the tap of an external resistor divider from the output to GND. The frequency
foldback comparator lowers the oscillator frequency when the FB voltage falls below
250mV to prevent current-limit runaway during a short-circuit fault.
Buck regulator enable. Pull REN above 1.2V to turn the buck regulator on. For
automatic enable, connect REN to VIN using a 100kΩ resistor.
Bootstrap phase B. Connect a ceramic capacitor to SHB.
See Applications Information section.
High-side source connection phase B.
High-side gate drive phase B.
Low-side gate drive phase B.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
13
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
BLOCK DIAGRAM
Figure 1: Function Block Diagram
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
14
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
OPERATION
The MP6534 is a three-phase BLDC motor predriver that drives three external N-channel
MOSFET half bridges, with 0.8A source and 1A
sink current capability. It operates over a wide
input voltage range of 5V to 60V, generating a
boosted gate drive voltage when the input supply
is below 12V. The MP6534 features a low-power
sleep mode, which disables the device and
draws a very low supply current.
The MP6534 provides several flexible functions,
such as adjustable dead-time control and overcurrent protection, which allow the device to
cover a wide range of applications.
The MP6534 also integrates a 500mA, stepdown, buck regulator. The regulator can be used
to generate a low supply voltage for
microcontrollers or other logic circuits.
Power-Up Sequence
The power-up sequence is initiated by the
application of voltage to VIN pin. To initiate
power-up, VIN must be above the undervoltage
lockout threshold VUVLO.
After power-up begins, the VREG supply starts
operating. VREG must rise above VREG_RISE
before the device becomes functional.
The power-up process takes between 1mS and
2mS, after which the MP6534 will respond to
logic inputs and drive the outputs.
Gate Drive Power Supplies
Gate drive voltages are generated from the input
power, VIN. A regulated charge pump doubler
circuit supplies a voltage of approximately 11.5V
at the VREG pin. This voltage is used for the
low-side gate drive supply. The charge pump
requires external capacitors between the CPA
and CPB pins, and from VREG to ground.
The high side gate drive is generated by a
combination of a bootstrap capacitor and an
internal “trickle” charge pump.
Bootstrap
capacitors are charged to the VREG voltage
when the low side MOSFET is turned on. This
charge is then used to drive the high side
MOSFET gate when it is turned on.
To keep the bootstrap capacitors charged and
allow operation at 100% duty cycle, an internal
MP6534 Rev. 1.13
10/24/2018
“trickle” charge pump supplies a small current
(about 5µA) to overcome leakages that would
discharge the bootstrap capacitors.
Refer to the applications information section for
details on the selection of external components.
Sleep Mode (nSLEEP Input)
Driving nSLEEP low will put the device into a
low-power sleep state. In this state, all the
internal circuits are disabled, and all inputs are
ignored. nSLEEP has an interval pulldown, so it
must be driven high for the device to operate.
When exiting sleep mode, the part will initiate the
power-up sequence described above.
Input Logic
The ENx input pins controls both the high- and
low-side gate drive outputs of each phase. When
ENx is low, the gate drive outputs are pulled low,
and the PWMx input of that phase is ignored.
When ENx is high, the gate drive outputs are
enabled, and the PWM input is recognized. Refer
to Table 1 for the logic truth table.
Table 1: Input Logic Truth Table
ENx
H
H
L
PWMx
H
L
x
SHx
VIN
GND
High impedance
Low-side Automatic Turn-on
To ensure that the bootstrap capacitor is charged
enough to turn on the high-side MOSFET, each
time that the ENx pin transitions from low to
active high, the low-side MOSFET for that phase
is turned on for a short pulse (tLS). This occurs
regardless of the state of the PWMx input pin.
nFAULT
The nFAULT output pin reports to the system
when a fault condition (such as an output short
circuit, overcurrent, or overtemperature) is
detected. nFAULT is an open-drain output, and it
is driven low when a fault condition occurs. If the
fault condition is released, nFAULT is pulled high
by an external pull-up resistor.
Short Circuit Protection (VDS Sensing)
To protect the power stage from damage due to
high currents, a VDS sensing circuitry is
implemented in the MP6534. The voltage drop
across each MOSFET is sensed. (This voltage is
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
15
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
proportional to the RDS-ON of the MOSFET and
the IDS current passing through it). If this voltage
exceeds the voltage supplied to the OCREF
terminal, a short circuit is recognized.
all three phases is set by a single dead-time
resistor (RDT) between DT and ground with
Equation (1):
tDEAD(nS) = 3.7*R(kΩ)
(1)
In the event of a short circuit, the MP6534
disables all of the gate drive outputs. nFAULT is
driven active low. The device will stay latched off
until it is reset by nSLEEP or VIN UVLO.
If DT is tied to directly to ground, an internal
minimum dead time (30ns) will be applied.
Leaving DT open generates approximately a 6µs
dead time.
Short circuit protection can be disabled by
connection a 100kΩ resistor from VREG to the
OCREF pin.
UVLO Protection
If at any time the voltage on VIN falls below the
undervoltage lockout threshold VIN_RISE, all
circuitry in the device is disabled and the internal
logic will be reset.
Over-current Protection (OCP)
The MP6534 can implement output overcurrent
protection (OCP) by monitoring the current
through a low-side shunt resistor connected to
the low-side MOSFETs. This resistor is
connected to the LSS input pin and the low-side
MOSFET source terminals. If the OCP function is
not desired, the LSS pin and MOSFET source
terminals should all be connected directly to
ground.
If the LSS voltage (the voltage across the shunt
resistor) exceeds the LSS OCP threshold voltage
VLSS-OCP, an OCP event is recognized. Once an
OCP event is detected, the MP6534 will enter a
latched fault state and disable all functions. The
device will stay latched off until it is reset by
nSLEEP or VIN UVLO.
Operation will resume with the power-up
sequence when VIN rises above the UVLO
thresholds.
After power-up, if the voltage on VREG drops
below the VREG_RISE threshold, the MP6534 will
enter a latched fault state and disable all
functions. The nFAULT pin will be driven active
low. The device will stay latched off until it is
reset by nSLEEP or VIN UVLO.
Thermal Shutdown
If the die temperature exceeds safe limits, the
MP6534 will enter a latched fault state and
disable all functions. The device will stay latched
off until it is reset by nSLEEP or VIN UVLO.
The OCP current limit level is selected by the
value of the current sense resistor at LSS pin.
Refer to the applications information section for
more information.
Buck Regulator Operation
The buck regulator in the MP6534 is a currentmode buck regulator. The EA output voltage is
proportional to the peak inductor current.
OCP protection can be disabled by connection a
100kΩ resistor from VREG to the OCREF pin.
At the beginning of a cycle, M1 is off. The EA
output voltage is higher than the current sense
amplifier output, and the current comparator’s
output is low. The rising edge of the 480kHz CLK
signal sets the RS flip-flop. Its output turns on M1,
connecting SW and the inductor to the input
supply.
The increasing inductor current is sensed and
amplified by the current sense amplifier. Ramp
compensation is summed to the current sense
amplifier output and compared to the error
amplifier output by the PWM comparator. When
the sum of the current sense amplifier output and
the slope compensation signal exceed the EA
output voltage, the RS flip-flop is reset and M1 is
Short-circuit and OCP Deglitch Time
There is often a current spike during switching
transitions, due to body diode reverse-recovery
current or the distributed capacitance of the load.
This current spike requires filtering to prevent it
from erroneously triggering OCP. An internal
fixed deglitch time (tOC) blanks the output of the
VDS monitor when the outputs are switched.
Dead-Time Adjustment
To prevent shoot-through in any phase of the
bridge, it is necessary to have a dead time (tDEAD)
between a high- or low-side turn-off and the next
complementary turn-on event. The dead time for
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
16
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
turned off. The external Schottky rectifier diode
conducts the inductor current.
If the sum of the current sense amplifier output
and the slope compensation signal does not
exceed the EA output for an entire cycle, then the
falling edge of the CLK resets the flip-flop.
The output of the error amplifier integrates the
voltage difference between feedback and the
0.81V bandgap reference. The polarity is such
that a FB voltage lower than 0.81V increases the
EA output voltage. Since the EA output voltage is
proportional to the peak inductor current, an
increase in its voltage also increases current
delivered to the output.
Figure 2: Functional Block Diagram of Buck Regulator
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
17
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
The normal operating range of VIN is between
5V and 60V.
Related to the current capability of the MOSFET
is the rds(on). This is the resistance of the
MOSFET when it is in the fully “turned on” state.
The MOSFET will dissipate power proportional to
the rds(on) and the motor current: P=I2R. The
rds(on) needs to be selected so that for the
desired motor current, the heat generated in this
power can be safely dissipated. In some cases,
this may require special PCB design
considerations and/or external heatsinks to be
used for the MOSFETs.
VIN should never be allowed to exceed the
absolute maximum ratings, even in a short term
transient condition, or damage to the device may
result. In some cases – especially where
mechanical energy can turn a motor into a
generator – it may be necessary to use some
form of overvoltage protection, such as a TVS
diode, between VIN and ground.
Some consideration should be made for the safe
operating area (SOA) of the MOSFETs in fault
conditions, such as a short circuit. The IC will act
quickly in the event of a short, but there is still a
very short time (on the order of 3µS) where large
currents can flow in the MOSFETs while the
protection circuits recognize the fault and disable
the outputs.
Component Selection
External Capacitor Selection
MOSFET selection
The MP6534 has a unique feature in that it can
provide a gate drive voltage (VREG) of 10-12V
even if the input supply voltage drops as low as
5V. This gate drive voltage is generated by a
charge pump inside the part, which uses external
capacitors.
GATE DRIVER APPLICATIONS
INFORMATION
VIN Input Voltage
The VIN pin supplies all power to the device. It
must be properly bypassed with a capacitor to
ground
–
see
below
for
specific
recommendations.
Correctly selecting the power MOSFETs used to
drive a motor is crucial to designing a successful
motor drive.
The first requirement is that the MOSFET must
have a VDS breakdown voltage that is higher
than the supply voltage. It is recommended that
considerable margin – 10-15 volts - be added to
prevent MOSFET damage from transient
voltages that can be caused by parasitic
inductances in the PCB layout and wiring. For
example, for 24V power supply applications,
MOSFETs having a breakdown voltage of 40V60V minimum are recommended. More margin is
desirable in high current applications, as the
transients caused by parasitic inductances may
be larger. Also, there are conditions like
regenerative braking that can inject current back
into the power supply; care must be taken that
this does not cause an increase in the power
supply voltage large enough to damage
components.
The MOSFETs must be able to safely pass the
current needed to run the motor. The highest
current condition, which is normally when the
motor is first started or stalled, needs to be
supported. This is typically called the “stall
current” of the motor.
MP6534 Rev. 1.13
10/24/2018
The charge pump flying capacitor, CCP, should
have a capacitance of 470nF. It needs to be
rated to withstand the maximum VIN power
supply voltage. An X7R or X5R ceramic capacitor
is recommended. With a 470nF capacitor, VREG
can output approximately 10mA when VIN is 5V.
If operation below 10V is not needed, a 220nF
capacitor can be used
To provide the large peak currents needed to
turn on the HS MOSFET, bootstrap capacitors
are used. These capacitors are charged when
the output is driven low, then the charge in the
bootstrap capacitor is used to turn on the HS
MOSFET when the output is driven high. (Note
that an internal charge pump will keep the
bootstrap capacitor changed when the output is
held high for an extended period).
The bootstrap capacitors are selected depending
on the MOSFET total gate charge. When the HS
MOSFET is turned on, the charge stored in the
bootstrap capacitor is transferred to the HS
MOSFET gate. As a simplified approximation, the
minimum bootstrap capacitance can be
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
18
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
estimated as CBOOT > 8*QG, where QG is the total
gate charge of the MOSFET in nC, and CBOOT is
in nF. The bootstrap capacitors should not
exceed 1µF, or they may cause improper
operation at start-up.
For most applications, bootstrap capacitors
between 0.1µF and 1µF, X5R or X7R ceramic,
rated for 25V minimum, are recommended.
The VREG pin requires a bypass capacitor to
ground of 10µF. This should be an X7R or X5R
ceramic capacitor rated for 16V minimum.
VIN requires a bypass capacitor to ground,
placed as close as possible to the device. At a
minimum, a 0.1µF X5R or X7R ceramic capacitor,
rated for the VIN voltage, is recommended.
conditions that the HS and LS MOSFETs are
never turned on at the same time.
Dead time can be set over a large range, by
selecting the value of the external resistor that is
connected to the DT pin. Usually, a good starting
point is a dead time of about 1µS, which requires
a 200k resistor on the DT pin. If faster switching
and/or a high PWM frequency (over ~30kHz) is
used, shorter dead time may be desirable; if
switching is slowed using external gate resistors,
longer dead time may be needed.
The waveform below shows about a 300nS dead
time between the LS gate turn-off and the HS
gate turn-on.
Depending on the power supply impedance and
the distance between the MOSFETs and the
power supply, additional bulk capacitance is
usually needed. Between 47µF and 470µF of low
ESR electrolytic capacitors are typically used.
Dead Time Resistor Selection
During the transition between driving an output
low and high, there is a short period when neither
the HS nor LS MOSFET is turned on. This period,
called “dead time”, is needed to prevent any
overlap in conduction between HS and LS
MOSFETs, which would effectively provide a
short-circuit directly between the power supply
and ground. This condition, referred to as “shootthrough”, causes large transient currents, and
can destroy the MOSFETs.
Since motors are inductive by nature, once
current is flowing in the motor, it cannot stop
immediately, even if the MOSFETs are turned off.
This “recirculation current” continues to flow in
the original direction until the magnetic field has
decayed.
When the MOSFETs are turned off, this current
will flow through the “body diode” which is
inherent in the MOSFET device.
MOSFET body diodes have a much higher
voltage drop than the MOSFET has during
conduction, so there more power dissipated in
body diode conduction than during the on time.
Because of this, it is desirable to minimize the
dead time. However, the dead time must be
made large enough to guarantee under all
MP6534 Rev. 1.13
10/24/2018
LSS Resistor Selection
If the voltage applied to the LSS pin ever
exceeds 500mV, an overcurrent event will be
recognized. The external sense resistor is sized
to provide less than 500mV drop at the maximum
expected motor current. For example, if a 50 mΩ
resistor is used, a current of 10 amps would
cause a 500mV drop, and activate the
overcurrent protection.
If this function is not needed, connect LSS
directly to ground.
OCREF Voltage Selection
An internal comparator compares the voltage
drop across each MOSFET with a voltage that is
externally provided on the OCREF input pin.
This voltage is normally provided by an external
resistor divider from a convenient power supply.
If the drop across any MOSFET ever exceeds
the voltage on the OCREF pin, a short-circuit
event is recognized.
If this function is not needed, connect OCREF to
VREG through a 100k resistor.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
19
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
Gate Drive Considerations
The gate characteristics of the selected
MOSFETs will affect how fast they will be
switched and off. The gate drive outputs of the
device can be connected directly to the gates of
the power MOSFETs, which results in the fastest
possible turn-on and turn-off times. However, it
may be advantageous to add external
components (resistors and/or diodes) to modify
the MOSFET turn-on and turn-off characteristics.
Adding external series resistance – typically
between 10 and 100 ohms – will limit the current
that charges and discharges the gate of the
MOSFET, which will slow down the turn-on and
turn-off times. Sometimes this is desirable to
control EMI and noise. Slowing the transition
down too much, however, results in large power
dissipation in the MOSFET during switching.
In some cases, it is desirable to have a slow turnon, but a fast turn-off. This can be implemented
by using a series resistor in parallel with a diode.
At turn-on, the resistor limits the current flow into
the gate; at turn-off, the gate is discharged
quickly through the diode.
This waveform shows the effect of adding a
100Ω series resistor between the GLA and GLH
pins and the MOSFET gates. Rise time on the
phase node has been slowed significantly. The
scale here is 200nS/div.
This waveform shows the effect of adding a
1N4148 diode in parallel with the 100Ω resistors
(with the cathode connected to the IC). You can
see that the fall time of the LS gate is quite fast
compared to the HS gate rise time. The phase
node moves even slower, because of a longer
period of time between when the LS FET is
turned off, and the HS FET is turned on.
1N4148
RGHS
1N4148
RGLS
This waveform below shows the gates of the LS
and HS MOSFETs, and the phase node (output)
with no series resistance. You can see that the
gates transition quickly. The resulting rise time on
the phase node is quite fast. Note the scale of
100nS/div.
PCB Layout
Proper PCB layout is critical to the performance
of MOSFET gate drivers. In particular, the
connection between the HS source and LS drain
needs to be as direct as possible, to avoid
negative undershoot on the phase node due to
parasitic inductances. The pre-driver is designed
to accommodate negative undershoot, but if it is
excessive, unpredictable operation or damage to
the IC can result.
An example PCB layout (the MP6530 is shown,
which is similar to the MP6534) is shown below.
It uses surface mount N-channel MOSFETs,
which allows very short connection between the
HS and LS MOSFETs. You can also see the use
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
20
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
of wide copper areas for all of the high current
paths.
The low-side sense resistor is composed of three
resistors in parallel (R25, R26, and R27), and is
connected to the input supply and LS MOSFET
source terminals by wide copper areas.
MP6534 Rev. 1.13
10/24/2018
Note the location of the charge pump and supply
bypass capacitors, very close to the IC. The
grounded side of these capacitors is connected
to a ground plane, which is connected to the
device ground pin and exposed pad. The highcurrent ground path between the input supply,
input bulk capacitor C19, and MOSFETs is kept
away from this area.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
21
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
BUCK REGULATOR APPLICATION
INFORMATION
Setting the Output Voltage
The external resistor divider sets the output
voltage (see the Typical Application schematic).
Table 2 lists resistors for common output
voltages. The feedback resistor (R1) also sets
the feedback loop bandwidth with the internal
compensation capacitor (see Figure 2). R2 can
be calculated with Equation (2):
R2
R1
VOUT
1
0.81V
(2)
Table 2: Resistor Selection for Common Output
Voltages
VOUT (V)
R1 (kΩ)
R2 (kΩ)
1.8
2.5
3.3
5
80.6 (1%)
49.9 (1%)
49.9 (1%)
49.9 (1%)
64.9 (1%)
23.7 (1%)
16.2 (1%)
9.53 (1%)
Selecting the Inductor
For most applications, use an inductor with a DC
current rating at least 25% higher than the
maximum load current. For best efficiency, the
inductor’s DC resistance should be less than
200mΩ. For most designs, the required
inductance value can be derived from Equation
(3):
( VIN VOUT )
V
L OUT
VIN IL f SW
(3)
Where ∆IL is the inductor ripple current.
Choose the inductor ripple current to be 30% of
the maximum load current. The maximum
inductor peak current can be calculated with
Equation (4):
IL(MAX) ILOAD
I
L
2
Selecting the Input Capacitor
The input capacitor reduces the surge current
drawn from the input supply and the switching
noise from the device. The input capacitor
impedance at the switching frequency should be
less than the input source impedance to prevent
high frequency switching current from passing
through the input. Ceramic capacitors with X5R
or X7R dielectrics are recommended for their low
ESR and small temperature coefficients. For
most applications, a 4.7µF capacitor is sufficient.
Selecting the Output Capacitor
The output capacitor keeps the output voltage
ripple small and ensures feedback loop stability.
The output capacitor impedance should be low at
the switching frequency. Use ceramic capacitors
with X5R or X7R dielectrics for their low ESR
characteristics. For most applications, a 22µF
ceramic capacitor is sufficient.
PCB Layout Guide
Efficient PCB layout is critical for stable operation.
For best results, follow the guidelines below.
1) Keep the path of the switching current short.
2)
Minimize the loop area formed by the input
capacitor, high-side MOSFET, and Schottky
diode.
3)
Keep the connection from the power ground
to the Schottky diode to RSW as short and
wide as possible.
4)
Ensure that all feedback connections are
short and direct.
5)
Place
the
feedback
resistors
and
compensation components as close to the
chip as possible.
6)
Route RSW away from sensitive analog
nodes such as RFB.
(4)
Under light-load conditions (below 100mA), use a
larger inductance to improve efficiency.
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
22
MP6534 – 5V TO 55V, 3-PHASE BLDC PRE-DRIVER WITH BUCK REGULATOR
PACKAGE INFORMATION
QFN-40 (5mmx5mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP6534 Rev. 1.13
10/24/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
23
工商网监
湘ICP备2023018690号
