MP6900DJ-LF-P

MP2362 Dual 2A, 23V, 380KHz Step-Down Converter with Frequency Synchronization The Future of Analog IC Technology DESCRIPTION FEATURES The MP2362 is a dual monolithic step-down switch mode converter with built-in internal power MOSFETs. It achieves 2A continuous output current for each output over a wide input supply range with excellent load and line regulation. Each channel can be independently synchronized to a frequency up to 1.2MHz. • • • • • • • • • • • Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. In shutdown mode the regulator draws 40µA of supply current. • • • The MP2362 requires a minimum number of readily available standard external components. EVALUATION BOARD REFERENCE 2A Current for Each Output 0.18Ω Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 90% Efficiency 40µA Shutdown Mode Fixed 380KHz Frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75V to 23V Operating Input Range Each Output Adjustable from 1.22V to 16V Configurable for Single Output with Double the Current Programmable Under Voltage Lockout Frequency Synchronization Input Available in TSSOP20 with Exposed Pad Package APPLICATIONS Board Number Dimensions EV2362DF-00A 2.2”X x 1.6”Y x 0.4”Z • • • • Distributed Power Systems I/O and Core supplies Set top boxes Cable Modems “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 12V Efficiency vs Output Current Voltage 3.3V @ 2A 2 3 10nF B230A 4 5 6 7 8 9 OFF ON 10 SYNCA NC1 ENA COMPA BSA FBA INA SGB SWA PGA MP2362 PGB SWB SGA INB FBB NC2 COMPB BSB ENB SYNCB 95 20 19 18 90 10nF 17 16 15 14 13 10nF 12 11 VOUT = 5.0V OFF ON B230A 5V @ 2A EFFICIENCY (%) 1 SYNC CLOCK VOUT = 3.3V VOUT = 2.5V 85 80 75 10nF VIN = 10V 70 0 0.5 1 1.5 2 OUTPUT CURRENT (A) MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 1 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE TOP VIEW SYNCA 1 20 ENA NC1 2 19 COMPA BSA 3 18 FBA INA 4 17 SGB SWA 5 16 PGB PGA 6 15 SWB SGA 7 14 INB FBB 8 13 NC2 COMPB 9 12 BSB ENB 10 11 SYNCB Recommended Operating Conditions (2) Supply Voltage (VIN) ...................... 4.75V to 23V Operating Temperature.................–40°C to +85°C Thermal Resistance (3) θJA θJC TSSOP20F ............................. 40 ....... 6.... °C/W EXPOSED PAD FOR TSSOP20F ONLY Part Number* Package Temperature MP2362DF TSSOP20F –40°C to +85°C * Supply Voltage (INA, INB )................................ 25V Switch Voltage (SWA, SWB).............................. 26V Bootstrap Voltage (BSA, BSB) .................. VSW + 6V Feedback Voltage (FBA, FBB) ............ –0.3V to +6V Enable/UVLO Voltage (ENA, ENB) ..... –0.3V to +6V Comp Voltage (COMPA, COMPB) .......... –0.3V to +6V SYNC Voltage (SYNCA, SYNCB) ........... –0.3V to +6V Junction Temperature.............................+150°C Lead Temperature ..................................+260°C Storage Temperature ..............–65°C to +150°C Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. For Tape & Reel, add suffix –Z (eg. MP2362DF–Z) For RoHS compliant packaging, add suffix –LF (eg. MP2362DF–LF–Z) ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameter Feedback Voltage Symbol Condition VFB Upper Switch-On Resistance RDS(ON)1 Lower Switch-On Resistance RDS(ON)2 Upper Switch Leakage Current Limit (4) Current Limit Gain GCS Output Current to Comp Pin Voltage Error Amplifier Voltage Gain AVEA Error Amplifier GEA Transconductance Oscillator Frequency fOSC Short Circuit Frequency fSC SYNC Frequency MP2362 Rev. 0.93 1/25/2010 4.75V ≤ VIN ≤ 23V Min Typ Max Units 1.198 1.222 1.246 V 0.18 10 3.4 Ω Ω µA A 1.95 A/V 400 V/V VEN = 0V, VSW = 0V 10 2.4 ∆IC = ±10 µA 500 770 1100 µA/V VFB = 0V SYNC Drive = 0V to 2.7V 340 20 0.45 380 35 420 54 1.2 KHz KHz MHz www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 2 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TA = +25°C, unless otherwise noted. Parameter EN Shutdown Threshold Voltage Enable Pull-Up Current EN UVLO Threshold Rising EN UVLO Threshold Hysteresis Symbol Condition VEN IEN VUVLO Min Typ Max Units ICC > 100µA 0.7 1.0 1.3 V VEN Rising 2.37 1.0 2.50 2.62 µA V 210 mV Supply Current (Shutdown) IOFF VEN ≤ 0.4V 40 70 µA Supply Current (Quiescent) ION VEN ≥ 3V 2.0 2.8 mA Thermal Shutdown TS Maximum Duty Cycle Minimum On Time 160 VFB = 1.0V, fSW = 380KHz tON 90 100 °C % ns Note: 4) Equivalent output current = 1.5A ≥ 50% Duty Cycle 2.0A ≤ 50% Duty Cycle Assumes ripple current = 30% of load current. Slope compensation changes current limit above 40% duty cycle. MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 3 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER PIN FUNCTIONS Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name Description Synchronization Input for Channel A. It is internally pulled down to ground with a 11kΩ resistor. Leave it open if unused. NC No Connect BSA High-Side Driver Boost Pin. Connect a 10nF capacitor from this pin to SWA. Supply Voltage Channel A. The MP2362 operates from a +4.75V to +23V unregulated input. INA Input Ceramic Capacitors should be close to this pin. SWA Switch Channel A. This connects the inductor to either INA through M1A or to PGA through M2A. Power Ground Channel A. This is the Power Ground Connection to the input capacitor PGA ground. Signal Ground Channel A. This pin is the signal ground reference for the regulated output voltage. For this reason care must be taken in its layout. This node should be placed outside SGA of the D1 to C1 ground path to prevent switching current spikes from inducing voltage noise into the part. Feedback Voltage for Channel B. This pin is the feedback voltage. The output voltage is ratio scaled FBB through a voltage divider, and the center point of the divider is connected to this pin. The voltage is compared to the on board 1.22V reference. Compensation Channel B. This is the output of the transconductance error amplifier. A series COMPB RC is placed on this pin for proper control loop compensation. Please refer to more in the datasheet. Enable/UVLO Channel B. A voltage greater than 2.62V enables operation. Leave ENB unconnected for automatic startup. An Under Voltage Lockout (UVLO) function can be ENB implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown the ENB pin voltage needs to be less than 700mV. Synchronization Input for Channel B. It is internally pulled down to ground with a 11kΩ SYNCB resistor. Leave it open if unused. BSB High-Side Driver Boost Pin. Connect a 10nF capacitor from this pin to SWB. NC No Connect. Supply Voltage Channel B. The MP2362 operates from a +4.75V to +23V unregulated input. INB Input Ceramic Capacitors should be close to this pin. SWB Switch Channel B. This connects the inductor to either INB through M1B or to PGB through M2B. Power Ground Channel B. This is the Power Ground Connection to the input capacitor PGB ground. Signal Ground Channel B. This pin is the signal ground reference for the regulated output voltage. For this reason care must be taken in its layout. This node should be placed outside SGB of the D1 to C1 ground path to prevent switching current spikes from inducing voltage noise into the part. Feedback Voltage for Channel A. This pin is the feedback voltage. The output voltage is ratio scaled FBA through a voltage divider, and the center point of the divider is connected to this pin. The voltage is compared to the on board 1.22V reference. Compensation Channel A. This is the output of the transconductance error amplifier. A series COMPA RC is placed on this pin for proper control loop compensation. Please refer to more in the datasheet. Enable/UVLO Channel A. A voltage greater than 2.62V enables operation. Leave ENA unconnected for automatic startup. An Under Voltage Lockout (UVLO) function can be ENA implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown the ENA pin voltage needs to be less than 700mV. SYNCA MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 4 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER OPERATION If the sum of the Current Sense Amplifier output and the Slope Compensation signal does not exceed the COMP voltage, the falling edge of the CLK resets the Flip-Flop. The MP2362 is a dual channel current mode regulator. The COMP pin voltage is proportional to the peak inductor current. At the beginning of a cycle, the upper transistor M1 is off, and the lower transistor M2 is on (see Figure 1). The COMP pin voltage is higher than the current sense amplifier output, and the current comparator’s output is low. The rising edge of the 380KHz CLK signal sets the RS Flip-Flop. Its output turns off M2 and turns on M1 thus connecting the SW pin and inductor to the input supply. The increasing inductor current is sensed and amplified by the Current Sense Amplifier. Ramp compensation is summed to Current Sense Amplifier output and compared to the Error Amplifier output by the Current Comparator. The output of the Error Amplifier integrates the voltage difference between the feedback and the 1.22V bandgap reference. The polarity is such that a voltage at the FB pin lower than 1.22V increases the COMP pin voltage. Since the COMP pin voltage is proportional to the peak inductor current, an increase in its voltage increases current delivered to the output. The lower 10Ω switch ensures that the bootstrap capacitor voltage is charged during light load conditions. External Schottky Diode D1 carries the inductor current when M1 is off (see Figure 1). When the sum of the Current Sense Amplifier output and the Slope Compensation signal exceeds the COMP pin voltage, the RS FlipFlop is reset and the MP2362 reverts to its initial M1 off, M2 on state. INA/ INB CURRENT SENSE AMPLIFIER INTERNAL REGULATORS SYNCA/ SYNCB OSCILLATOR 35/380KHz 1.0V -- ENA/ ENB -2.5V/ 2.29V + FREQUENCY FOLDBACK COMPARATOR SLOPE COMP CLK + + SHUTDOWN COMPARATOR 5V -- + -- BSA/ BSB S Q R Q SWA/ SWB CURRENT COMPARATOR LOCKOUT COMPARATOR 1.8V -- + -- COMPA/ COMPB 0.7V 1.222V + ERROR AMPLIFIER PGA/ PGB SGA/ SGB FBA / FBB Figure 1—Functional Block Diagram (Diagram portrays ½ of the MP2362) MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 5 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER APPLICATION INFORMATION COMPONENT SELECTION The MP2362 has two channels: A and B. The following formulas are used for component selection of both channels. Refer to components with reference “A” for channel A, and components with reference “B” for channel B, respectively, as indicated in Figure 3 (i.e. – R1A for Channel A and R1B for Channel B). Setting the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin. The voltage divider divides the output voltage down to the feedback voltage by the ratio: VFB = VOUT R2 R1 + R2 Thus the output voltage is: VOUT = 1.22 V × R1 + R2 R2 Where VFB is the feedback voltage and VOUT is the output voltage A typical value for R2 can be as high as 100kΩ, but a typical value is 10kΩ. Using that value, R1 is determined by: R1 = R2 × ( VOUT − 1) 1.22V For example, for a 3.3V output voltage, R2 is 10kΩ, and R1 is 17.0kΩ. Choose a 16.9kΩ, 1% resistor. Inductor The inductor is required to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule for determining the inductance to use is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum MP2362 Rev. 0.93 1/25/2010 switch current limit. The inductance value can be calculated by: L1 = ⎛ ⎞ VOUT V × ⎜⎜1 − OUT ⎟⎟ fS × ∆IL ⎝ VIN ⎠ Where VIN is the input voltage, fS is the switching frequency, and ∆IL is the peak-topeak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated by: ILP = ILOAD + ⎛ ⎞ VOUT V × ⎜⎜1 − OUT ⎟⎟ 2 × fS × L1 ⎝ VIN ⎠ Where ILOAD is the load current. Output Rectifier Diode The output rectifier diode supplies the current to the inductor when the high-side switch is off. To reduce losses due to the diode forward voltage and recovery times, use a Schottky diode. Choose a diode whose maximum reverse voltage rating is greater than the maximum input voltage, and whose current rating is greater than the maximum load current. Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD × VOUT ⎛⎜ VOUT × 1− VIN ⎜⎝ VIN ⎞ ⎟ ⎟ ⎠ The worst-case condition occurs at VIN = 2VOUT, where: IC1 = ILOAD 2 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 6 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ∆VIN = ⎛ ILOAD V V × OUT × ⎜⎜1 − OUT fS × C1 VIN ⎝ VIN ⎞ ⎟⎟ ⎠ Output Capacitor The output capacitor is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: ∆VOUT = VOUT ⎛ V × ⎜1 − OUT f S × L1 ⎜⎝ VIN ⎞ ⎞ ⎛ 1 ⎟ ⎟⎟ × ⎜ R ESR + ⎜ 8 × f S × C2 ⎟⎠ ⎠ ⎝ Where L1 is the inductor value, C2 is the output capacitance value, and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ∆VOUT = ⎞ ⎛ V × ⎜⎜1 − OUT ⎟⎟ VIN ⎠ × L1 × C2 ⎝ VOUT 8 × fS 2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ∆VOUT = VOUT ⎛ V ⎞ × ⎜1 − OUT ⎟ × RESR fS × L1 ⎝ VIN ⎠ MP2362 can be optimized for a wide range of capacitance and ESR values. Compensation Components The MP2362 employs current mode control on each channel for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP pin is the output of the internal transconductance error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC gain of the voltage feedback loop is given by: A VDC = R LOAD × G CS × A VEA × VFB VOUT Where AVEA is the error amplifier voltage gain, GCS is the current sense transconductance and RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3) and the output resistor of error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at: fP1 = G EA 2π × C3 × A VEA fP2 = 1 2π × C2 × R LOAD is Where GEA transconductance. the error amplifier The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: f Z1 = 1 2π × C3 × R3 The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: The characteristics of the output capacitor also affect the stability of the regulation system. The MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 7 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER fESR = 1 2π × C2 × R ESR In this case (as shown in Figure 2), a third pole set by the compensation capacitor (C6) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: fP3 = 1 2π × C6 × R3 The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback loop has the unity gain is important. Lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies could cause system unstable. A good rule of thumb is to set the crossover frequency to below one-tenth of the switching frequency. To optimize the compensation components for conditions not listed in Table 2, the following procedure can be used: 1. Choose the compensation resistor (R3) to set the desired crossover frequency. Determine the R3 value by the following equation: R3 = 2π × C2 × f C VOUT × G EA × G CS VFB Where fC is the desired crossover frequency, which is typically less than one tenth of the switching frequency. 2. Choose the compensation capacitor (C3) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero, fZ1, to below one forth of the crossover frequency provides sufficient phase margin. Determine the C3 value by the following equation: C3 > 4 2π × R3 × f C 3. Determine if the second compensation capacitor (C6) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: f 1 < S 2π × C2 × R ESR 2 If this is the case, then add the second compensation capacitor (C6) to set the pole fP3 at the location of the ESR zero. Determine the C6 value by the equation: C6 = C2 × R ESR R3 Frequency Synchronization Each channel of the MP2362 can be driven with an external clock of up to 1.2MHz. The rising edge of the external clock resets the internal clock, and the amplitude of the external clock must be greater than 2.7V. External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external BST diode are: z VOUT=5V or 3.3V; and z Duty cycle is high: D= VOUT >65% VIN In these cases, an external BST diode is recommended from the output of the voltage regulator to BST pin, as shown in Figure2 External BST Diode IN4148 BST MP2362 SW CBST L + COUT 5V or 3.3V Figure 2—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. Where R3 is the compensation resistor value. MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 8 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER PCB Layout Guide PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure3 for references. 1) 2) Keep the path of switching current short and minimize the loop area formed by Input cap, high-side MOSFET and schottky diode. 3) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 4) Route SW away from sensitive analog areas such as FB. 5) Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. Keep the connection of schottky diode between SW pin and input power ground as short and wide as possible. PGND PGND R1A C1B C1A R2A D1A C2B R4A D1B C2A C5A R3B C6B L1A C3B 1 2 3 4 5 6 7 8 9 10 SYNCA NC1 BSA INA SWA PGA SGA FBB COMPB ENB ENA COMPA FBA SGB PGB SWB INB NC2 BSB SYNCB 20 19 18 17 16 15 14 13 12 11 R3A C6A C3A C5B L1A R2B R4B R1B Top Layer SGND Bottom Layer Figure3―PCB Layout MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 9 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS 12V 3.3V @ 2A 1 2 3 SYNCA NC1 COMPA BSA FBA C5A 4 INA 10nF 5 SWA D1A B230A 6 7 8 9 10 OFF ON C6B NS ENA SGB MP2362 PGB PGA SWB SGA INB FBB NC2 COMPB BSB SYNCB ENB 20 OFF ON 19 C6A NS 18 17 16 D1B B230A 15 14 13 C3A 10nF 2.5V @ 2A C5B 10nF 12 11 C3B 10nF 3.3V 1.2MHz CLOCK INPUT 50% Duty Cycle Figure 4—Dual Phase 1.2MHz, 2.5V @ 2A and 3.3V @ 2A Step-down Converter from 12V Input MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 10 MP2362 — DUAL 2A, 23V, 380KHZ STEP-DOWN CONVERTER PACKAGE INFORMATION TSSOP20F NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2362 Rev. 0.93 1/25/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 11