MP6907
Fast Turn-off Flyback
Synchronous Rectifier
that Supports CCM, DCM
and QR Operation Modes
DESCRIPTION
FEATURES
The MP6907 is a low-drop diode emulator
controller IC that, when combined with an
external MOSFET, can replace Schottky diodes
in high-efficiency flyback converters. The
MP6907 regulates the forward drop of an
external switch to about 70mV, which switches
off once the voltage becomes negative.
The MP6907 provides a SYNC interface to
receive an external signal to shut down the gate
driver for reliable continuous conduction mode
(CCM) operation. A programmable light-load
sleep mode can reduce the IC’s quiescent
current to ~150μA.
The MP6907 is available in compact SOIC8
and TSOT23-6 packages.
Works with 12V Standard and 5V Logic
Level MOSFETS
Compatible with Energy Star 1W Standby
Requirements
Fast Turn-Off Total Delay of 25ns
4.2V~35V Wide VDD Operating Range
~150μA Quiescent Current in Light-Load
Mode(1)
Supports CCM, DCM, and Quasi-Resonant
Operation
SYNC Interface for CCM Operation
Supports
High-Side
and
Low-Side
Rectification
Power Savings of up to 1.5W in a Typical
Notebook Adapter
Available in SOIC8 and TSOT23-6
Packages
APPLICATIONS
Industrial Power Systems
Distributed Power Systems
Battery Powered Systems
Flyback Converters
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
NOTE:
1)
Related issued patent: US Patent US8,067,973; US8,400,790. CN Patent
ZL201010504140.4; ZL200910059751.X. Other patents pending.
TYPICAL APPLICATION
C1
4
2
VDD
VD
SYNC
LL
3
VSS
5
R2
R1
8
MP6907 Rev. 1.02
2/7/2017
VG
C2
PGND 1
EN
MP6907
7
6
C3
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1
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
ORDERING INFORMATION
Part Number*
MP6907GS
MP6907GJ
Package
SOIC8
TSOT23-6
Top Marking
See Below
See Below
* For Tape & Reel, add suffix –Z (e.g. MP6907GS–Z)
* For Tape & Reel, add suffix –Z (e.g. MP6907GJ–Z)
TOP MARKING (MP6907GS)
MP6907: Part number
LLLLLLLL: Lot number
MPS: MPS prefix
Y: Year code
WW: Week code
TOP MARKING (MP6907GJ)
ATP: Product code of MP6907GJ
Y: Year code
MP6907 Rev. 1.02
2/7/2017
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2
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
PACKAGE REFERENCE
TOP VIEW
PGND
1
EN
2
MP6907
TOP VIEW
8
VG
7
SYNC
PGND
LL
3
VD
4
6
VDD
5
VSS
SOIC8
ABSOLUTE MAXIMUM RATINGS (1)
VDD to VSS ........................... -0.3V to +38V
PGND to VSS ....................... -0.3V to +0.3V
VG to VSS ............................. -0.3V to +20V
VD to VSS .............................. -1V to +180V
SYNC, LL, EN to VSS........... -0.3V to +6.5V
Continuous power dissipation (TA = +25°C)
(2)
SOIC8 .................................................. 1.4W
Junction temperature ......................... 150°C
Lead temperature (solder) ................. 260°C
Storage temperature .......... -55°C to +150°C
Recommended Operation Conditions (3)
VDD to VSS ...............................4.2V to 35V
Maximum junction temp. (TJ) ........... +125°C
MP6907 Rev. 1.02
2/7/2017
6
VG
5
VSS
4
VDD
MP6907
LL
SOIC8
1
2
TSOT23-6
VD
3
TSOT23-6
Thermal Resistance (4) θJA
θJC
SOIC8............................... 90 ...... 45 ... °C/W
TSOT23-6........................ 220 .... 110 .. °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of
the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any
ambient
temperature
is
calculated
by
PD(MAX)=(TJ(MAX)-TA)/θJA.
Exceeding
the
maximum
allowable power dissipation produces an excessive die
temperature, causing the regulator to go into thermal
shutdown. Internal thermal shutdown circuitry protects the
device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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3
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
ELECTRICAL CHARACTERISTICS
VDD = 12V, -40°C ≤ TJ ≤ +125°C, unless otherwise noted.
Parameter
VDD voltage range
VDD UVLO rising
VDD UVLO hysteresis
Symbol Conditions
Operating current
ICC
Quiescent current
IQ
Shutdown current
Light-load mode current
Thermal shutdown (5)
Thermal shutdown hysteresis (5)
Enable UVLO rising
Enable UVLO hysteresis
Internal pull-up current on EN
Control Circuitry Section
VSS - VD forward voltage
Turn-off threshold (VSS - VD)
CLOAD = 4.7nF,
FSW = 100kHz
VSS - VD = 0.5V
VDD = 4V, EN = 0V
VDD = 20V, EN = 0V
VDD = 4V, LL = 0V
VDD = 20V, LL = 0V
Typ
3.97
0.185
Max
35
4.2
0.24
Units
V
V
V
8.5
10
mA
2.5
105
120
3.2
150
200
400
450
210
mA
155
150
10
1.74
0.27
12
VEN-R
1.4
0.1
Vfwd
48
5
65
15
60
85
0.85
1.55
160
1.7
2.12
TDon
TDon
Turn-on delay
Input bias current on VD
Turn-on blanking time
Turn-off blanking time (5)
Turn-off blanking VDS threshold
Turn-off threshold on SYNC
Internal pull-down current on
SYNC
Light-load enter SYNC duration
Light-load enter pulse width
Light-load enter pulse width
hysteresis
Gate disable threshold on LL
Turn-on threshold (VDS)
Gate Driver Section
VG (low)
Min
4.2
3.7
0.13
TB_ON
TB_OFF
VB_OFF
VSYN
CLOAD = 4.7nF, VGS = 2V
CLOAD = 10nF, VGS = 2V
VD = 180V
CLOAD = 4.7nF
CLOAD = 4.7nF
1.2
1.8
VSYNC = 5V
TSYN
TLL
RLL = 100kΩ
TLL-H
RLL = 100kΩ
VLL_DIS
VLL-DS
VDD = 12V
VG (high)
VG-L
VG-H
SYNC
turn-off
propagation
delay
Turn-off propagation delay
TDoff
TDoff
VD = VSS
VD = VSS, CLOAD = 4.7nF,
RGATE = 0Ω, VGS = 2V
VD = VSS, CLOAD = 10nF,
RGATE = 0Ω, VGS = 2V
82
28
105
150
1
2.35
µA
°C
°C
V
V
µA
2.2
2.5
mV
mV
ns
ns
µA
µs
ns
V
V
10
15
µA
95
1.95
125
2.5
µs
µs
0.25
0.1
-320
0.2
-220
10
11.7
VDD
45
Turn-off total delay
Maximum source current (5)
Pull-down impedance
ILOAD = 1mA
VDD > 10V
VDD ≤ 10V
70
1.4
2.1
0.45
21
µA
µs
0.3
-120
V
mV
0.1
13
V
V
90
ns
15
ns
40
80
ns
50
100
ns
0.5
0.8
1.6
A
Ω
NOTE:
5) Guaranteed by characterization or design.
MP6907 Rev. 1.02
2/7/2017
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4
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
PIN FUNCTIONS
Pin #
Pin #
(SOIC8) (TSOT23-6)
Name
Description
Power ground. PGND is the return for the driver switch.
Enable. Active high.
1
2
1
-
PGND
EN
3
2
LL
4
5
3
5
VD
VSS
6
4
VDD
7
-
SYNC
8
6
VG
MP6907 Rev. 1.02
2/7/2017
Light-load timing setting. Connect a resistor to LL to set the light load timing.
If LL is not left open, the IC will not enter light-load mode. Pull LL low to disable
the gate driver.
FET drain voltage sense.
Ground. VSS is also used as a reference for VD.
Supply voltage.
Interface for external signal control. Pull SYNC high to shut down the gate
driver immediately.
Gate driver output.
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5
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 12V, unless otherwise noted.
MP6907 Rev. 1.02
2/7/2017
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6
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 12V, unless otherwise noted.
MP6907 Rev. 1.02
2/7/2017
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7
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 12V, unless otherwise noted.
NOTE:
6)
See Figure 20 for the test circuit.
MP6907 Rev. 1.02
2/7/2017
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8
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
BLOCK DIAGRAM
LL
VDD
Power
Management
Logic
EN
VD
VDD
Protection
Switcher
Control
Circuitry
Driver
VG
VSS
SYNC
PGND
Figure 1: Functional Block Diagram
MP6907 Rev. 1.02
2/7/2017
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9
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
OPERATION
The MP6907 supports flyback converter
operation in continuous conduction mode
(CCM), discontinuous conduction mode (DCM),
and quasi-resonant mode. The control circuitry
controls the gate in forward mode and turns the
gate off when the MOSFET current is fairly low.
VD Clamp
Because VD can rise as high as 180V, a highvoltage JFET is used at the input. To avoid
excessive currents when VG drops below -0.7V,
a 1kΩ resistor is recommended between VD
and the drain of the external MOSFET.
Under-Voltage Lockout (UVLO)
When VDD is below the 4.2V UVLO threshold,
the MP6907 enters sleep mode, and VG
remains at a low level.
Enable (EN)
If EN is pulled low, the MP6907 is in shutdown
mode, which consumes ~150μA of shutdown
current. If EN is pulled high during the
rectification cycle, the gate driver will not start
until the next rectification cycle begins (see
Figure 2).
Turn-On Blanking
The control circuitry contains a blanking
function. When the MOSFET turns on, the
control circuit ensures that the on state lasts for
a specific period of time. The turn on blanking
time is ~1.6μs, during which the turn-off
threshold is blanked (see Figure 3).
Conduction Phase
When VDS rises above the forward voltage drop
(-70mV) according to the decrease of the
switching current, the MP6907 pulls down the
gate voltage level to make the on resistance of
the synchronous MOSFET larger to ease the
rise of VDS.
VDS
2V
-15mV
-70mV
Driver begin to
be pulled down
VGS
Driver turn off
2V
~1.6μs
VDS
Turn On
Delay
Turn On
Blanking
Turn Off Turn Off
Delay Blanking
Figure 3: Turn On/Off Timing Diagram
VGS
Will not start
gate driver until
next cycle
EN
Figure 2: EN Control Scheme
Thermal Shutdown
If the junction temperature of the chip exceeds
150°C, VG is pulled low, and the MP6907 stops
switching. The MP6907 resumes normal
operation after the junction temperature drops
to 140°C.
Turn-On Phase
When the switch current flows through the body
diode of the MOSFET, there is negative VDS
(VD-VSS) across the MOSFET. The VDS is much
lower than the forward voltage drop of the
control circuitry (-70mV), which then turns on
the MOSFET after a turn-on delay (see Figure
3).
MP6907 Rev. 1.02
2/7/2017
With this control scheme, VDS is adjusted to be
around -70mV, even when the current through
the MOSFET is fairly low. The function keeps
the driver voltage at a very low level when the
synchronous MOSFET is turned off, which
boosts the turn-off speed.
Turn-Off Phase
When VDS rises to trigger the turn off threshold
(-15mV), the gate voltage is pulled to zero after
a very short turn-off delay (see Figure 3).
SYNC Turn-Off for CCM Operation
An external turn-off signal can be applied on
SYNC to turn off the gate driver signal, which
can provide a more reliable operation in CCM.
A rising edge that exceeds 2V applied on SYNC
turns off the gate driver signal immediately (see
Figure 4).
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10
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
The gate driver of the MP6907 remains low for
as long as the SYNC voltage is high.
VDS
0mV
The light-load enter time (TLL) is programmable
by connecting a resistor (RLL) to LL. By
monitoring the LL current, TLL is set. The LL
voltage remains at ~2V internally. Calculate TLL
with Equation (1):
-70mV
TLL RLL (k )
ISD
VGS
Driver turn off
by SYNC signal
SYNC
Figure 4: SYNC Turn-Off for CCM
Turn-Off Blanking
After the gate driver is pulled to zero by VDS
reaching the turn-off threshold (-15mV), a turnoff blanking time is applied, during which the
gate driver signal is latched off. The turn-off
blanking is removed when VDS rises above 2V
(see Figure 3)
Light-Load Latch-Off Function
The gate driver of the MP6907 is latched off to
save driver loss and improve efficiency during
light-load condition.
When the synchronous MOSFET conducting
period stays lower than TLL for longer than the
light-load enter delay (TLL-Delay), the MP6907
enters light-load mode and latches off the gate
driver (see Figure 5). The synchronous
MOSFET conducting period lasts from the time
the gate driver turns on to when VGS drops
below 1V (VLL-GS).
Normal Mode
1.95s
100k
(1)
During light-load mode, the MP6907 monitors
the
synchronous MOSFET body diode
conducting period by sensing the time duration
when VDS is below -250mV (VLL_DS). If it is
longer than TLL + TLL-H (the light-load enter
pulse-width hysteresis), light-load mode ends,
and the gate driver is unlatched to restart
synchronous rectification (see Figure 6).
Light Load Mode
tLL+tLL-H
tLL+tLL-H
tLL+tLL-H
tLL+tLL-H
Secondary Side Current
Figure 6: MP6907 Exiting Light-Load Mode
The MP6907 also enters light-load mode when
the SYNC voltage is pulled high (>2V) for more
than 100μs. Light-load mode ends once the
SYNC voltage is pulled low (see Figure 7).
Normal Mode
Light Load Mode Normal Mode
100us
Light Load Mode
SYNC
TLL-dELAY
tLL
tLL
tLL
Figure 7: Light-Load Mode Controlled by SYNC
Secondary Side Current
Figure 5: MP6907 Entering Light-Load Mode
MP6907 Rev. 1.02
2/7/2017
If light-load mode ends during the rectification
cycle, the gate driver signal will not appear
until the next rectification cycle begins (see
Figure 8)
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11
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
VDS
R4
6
4
VDD
VD
D1
2
EN
VGS
C1
MP6907
PGND
LL
7
3
C3
R3
SYNC
R1
Will not start
gate driver until
next cycle
C2
1
8
5
VG
VSS
R2
Light Load Mode
Normal Mode
Figure 8: Gate Driver Starts after Exiting LightLoad Mode
Typical System Implementations
Figure
9
shows
the
typical
system
implementation for the IC power supply directly
derived from the output voltage, which is
available in low-side rectification.
Figure 10: IC Power Derived from the Auxiliary
Winding in Low-Side Rectification
C1
R1
R2
8
C3
3
R3
VG
VD
MP6907
LL
5 VSS
D1
1
R4
EN
SYNC
PGND
4
2
7
VDD 6
C2
C1
4
2
7
VDD
VD
EN
C2
PGND 1
MP6907
SYNC
LL 3
R3
R1
8
Figure 11: IC Power Derived from the Auxiliary
Winding in High-Side Rectification
6
VG
C3
VSS 5
R2
Figure 9: IC Power Derived from Output Voltage
The IC benefits from a wide VDD operating
range (4.2V to 35V). The MP6907 supports
most application fields with low-side rectification
by deriving the supply power from the system
output directly.
If the output voltage is out of the VDD operating
range or high-side rectification is used, an
auxiliary winding solution for the IC’s power
supply is recommended (see Figure 10 and
Figure 11). The auxiliary winding turn count (Nau)
can be set using Equation (2):
Nau
VDD
Ns
VOUT
(2)
Where Ns is the secondary winding turn count.
MP6907 Rev. 1.02
2/7/2017
A simple non-auxiliary winding solution for the
IC’s power supply is shown in Figure 12 and
Figure 13. The IC power is derived from the
secondary transformer winding through a diode.
When using this power solution, ensure that the
winding voltage is lower than the higher limit of
the VDD operating range (35V).
R4
C1
D1
4
2
7
R1
8
VDD
VD
EN
MP6907
PGND
LL
6
3
R3
SYNC
VG
C2
1
VSS
C3
5
R2
Figure 12: IC Power Derived from the Secondary
Winding in Low-Side Rectification
In Figure 12, the winding voltage is VS = VOUT +
VIN_MAX/n, where VOUT is the output voltage,
VIN_MAX is the maximum input voltage, and n is
the transformer turn ratio.
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12
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
C1
R1
R2
8
C3
VG
3
R3
MP6907
LL
5 VSS
D1
1
2
EN
7
SYNC
PGND
R4
4
VD
VDD 6
C2
Figure 13: IC Power Derived from the Secondary
Winding in High-Side Rectification
including driver loss. Because VDS is adjusted at
about -70mV during the driving period when the
switching current is fairly small, a MOSFET with
an RDS(ON) that is too low is not recommended
because the gate driver will be pulled low when
VDS = -ISDxRDS(ON) becomes larger than -70mV.
The RDS(ON) of the MOSFET does not contribute
to conduction loss. The conduction loss is PCON
= -VDSxISD ≈ ISDx70mV.
In Figure 13, VS = VIN_MAX/n.
Figure 16 shows the typical waveform of a QR
flyback, assuming a 50% duty cycle and where
IOUT is the output current.
If the secondary winding voltage exceeds the
higher limit of the VDD operating range (35V),
then an external LDO circuit with a Zener diode
is needed for the non-auxiliary winding solution
(see Figure 14 and Figure 15).
To achieve a fairly high use of the MOSFET’s
RDS(ON), the MOSFET should be turned on
completely for at least 50% of the SR
conduction period. Calculate VDS with Equation
(3):
Vds Ic Ron 2 IOUT Ron Vfwd
R4
C1
D2
D1
Where VDS is the drain-source voltage of the
MOSFET, and Vfwd is the forward voltage
threshold (~70mV).
R5
4
2
7
R1
8
EN
6
VDD
VD
MP6907
SYNC
VG
PGND
1
LL
3
C2
R3
C3
5
VSS
(3)
R2
Figure 14: IC Power Derived from the Secondary
Winding through an External LDO in Low-Side
Rectification
The MOSFET’s RDS(ON) is recommended to be
no lower than ~35/IOUT (mΩ). For example, for a
5A application, the RDS(ON) of the MOSFET is
recommended to be no lower than 7mΩ.
Id
50% SR Conduction Period
Ipeak
Ic
Ipeak≈4·IOUT
Ic≈2·IOUT
C1
R1
R2
D1
8
C3
R5
R4
3
R3
5
1
D2
VG
LL
VSS
PGND
MP6907
VD
EN
SYNC
VDD
Vg
4
2
7
6
C2
SR Conduction Period
Figure 16: Synchronous Rectification Typical
Waveforms in QR Flyback
Figure 15: IC Power Derived from the Secondary
Winding through an External LDO in High-Side
Rectification
SR MOSFET Selection
Power MOSFET selection is a trade-off
between RDS(ON) and QG. To achieve higher
efficiency, a MOSFET with a smaller RDS(ON) is
preferred. Typically, QG is larger when the
RDS(ON) is smaller, which makes the turn-on/-off
speed lower and leads to larger power loss,
MP6907 Rev. 1.02
2/7/2017
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13
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 17,
Figure 18, and Figure 19, and follow the
guidelines below.
Layout Example
Figure 18 shows a layout example of a single
layer with a through-hole transformer and a
TO220 package SR FET. RSN and CSN are the
RC snubber network for the SR FET.
Sensing for VD/VSS
The sensing loop (VD and VSS to the SR
FET) is minimized and kept separate from
the power loop. The VDD decoupling
capacitor (C4) is placed beside VDD.
1) Make the sensing connection (VD/VSS)
as close as possible to the MOSFET
(drain/source).
2) Make the sensing loop as small as
possible
C3
R3
R2
Q1
G
3) Place the VD resistor close to VD.
D
4) Keep the IC out of the power loop to
prevent the sensing loop and power
loop from interrupting each other (see
Figure 17).
R1
S
CSN
0
C2
RSN
C1
MP6907
0
R4
RD
VD
Sensing loop
as small as
possible
G
D
D1
LAYOUT TRACE
VSS
COMPONENTS PAD
JUMP WIRE
S
Sensing loops separated
from power loop
Figure 17: Voltage Sensing for VD/VSS on MP6907
5) Place a decoupling ceramic capacitor no
smaller than 1µF from VDD to PGND close
to the IC for adequate filtering.
Gate Driver Loop
1) Make the gate driver loop as small as
possible to minimize parasitic inductance.
2) Keep the driver signal far away from the VD
sensing trace on the layout.
Figure 18: Layout Example with TO220 Package
SR FET
Figure 19 shows another layout example of a
single layer with a PowerPAK/SO8 package SR
FET, which also has a minimized sensing loop
and power loop to prevent the loops from
interfering with one another.
R3 C3
R4
D1
R1
C2
0
Q1
C1
R2
LAYOUT TRACE
COMPONENTS PAD
JUMP WIRE
Figure 19: Layout Example with PowerPAK/SO8
Package SR FET
MP6907 Rev. 1.02
2/7/2017
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14
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
TYPICAL APPLICATION CIRCUIT
VIN
F1
1A
CY1
4.7nF/250VAC
CY2
4.7nF/250VAC
R1
1MΩ
CX1
0.22µF/250VAC
R2
1MΩ
LX1
24mH
GBU4J
1
BD1
2
C1
100µF
R11
R13
10kΩ
R12
1KΩ
R10
150KΩ 150KΩ
R9
10
Ω
R7
20KΩ
PGND
R5
DRV
NC
HV
C11
8
6
7
5
PGND
CY3 2.2nF/250VAC
T1
AGND
TL431
U2
U3
PC817B
1KΩ
R24
45:9:7:7 EE28_L
R22
20Ω
C12
0.1µF/25V
22µF/25V
PGND
CS
VCC
R16
51KΩ
GND
FSET
HF0300
C10
4.7nF/1kV
4
3
2
1
D2
US1K-F
C13
22pF
C5
10nF
COMP
D5
RT1
5Ω
Q1
R4
C15
390p
PGND
AGND
Vaux
0Ω
100nF
C16
Vs
R25
R26
2KΩ
R27
66.5KΩ
VG
Q2
R28
10KΩ
VS
C3
1nF
VOUT
R8
100K D1
AGND
220µF
C6
VD
AGND
R14
10Ω
D3
U1
MP6907GS
VD
EN
VG
SYNC
LL
VSS
PGND
VDD
C4
1µF
R15
10Ω
R17
VG
1KΩ
D4
VD
3
4
15
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MP6907 Rev. 1.02
2/7/2017
1Ω
PGND
1.5Ω
AP2761I
R3
1Ω
4
2
Vaux
Figure 20: MP6907 for a Secondary Synchronous Controller in a 90W Flyback Application
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
PACKAGE INFORMATION
SOIC8
MP6907 Rev. 1.02
2/7/2017
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16
MP6907 – FAST TURN-OFF FLYBACK SYNCHRONOUS RECTIFIER
PACKAGE INFORMATION (continued)
TSOT23-6
See note 7
EXAMPLE
TOP MARK
PIN 1 ID
IAAAA
RECOMMENDED LAND PATTERN
TOP VIEW
SEATING PLANE
SEE DETAIL ''A''
FRONT VIEW
SIDE VIEW
NOTE:
DETAIL "A"
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-193, VARIATION AB.
6) DRAWING IS NOT TO SCALE.
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK
FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP6907 Rev. 1.02
2/7/2017
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17
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