MP6924GS-Z

MP6924, MP6924A Fast Turn-off, CCM/DCM Compatible Dual LLC Synchronous Rectifier with low Sleep Mode Current DESCRIPTION FEATURES The MP6924, MP6924A is a dual, fast turn-off, intelligent rectifier for synchronous rectification in LLC resonant converters. • • • • • The IC drives two N-channel MOSFETs, regulates their forward voltage drop to Vfwd(MP6924:45mV,MP6924A:29mV), and turns the MOSFETs off before the switching current goes negative. • • The MP6924, MP6924A has a light-load function to latch off the gate driver under lightload conditions, limiting the current to 175μA. • The MP6924, MP6924A’s fast turn-off enables both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). • Works with Standard and Logic Level MOSFETs Compatible with Energy Star Fast Turn-Off Total Delay of 35ns Wide 4.2V ~ 35V VDD Operating Range 175µA Low Quiescent Current in Light-Load Mode Supports CCM, CrCM, and DCM Operation Supports High-Side and Low-Side Rectification Power Savings of Up to 1.5W in a Typical Notebook Adapter Available in a SOIC-8 Package APPLICATIONS • • • • The MP6924, MP6924A requires a minimal number of readily available, standard, external components and is available in a SOIC-8 package. AC/DC Adapters PC Power Supplies LCD and LED TVs Isolated DC/DC Power Converters All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. Table 1: MP6924A vs. MP6924 Turn-off Blanking 1.75μs vs. 210ns Time Improve noise immunity Be half Driving Capability Improve EMI performance 29mV vs. 45mV Forward Voltage Improve efficiency TYPICAL APPLICATION Q1 Cs S1 Ls Cin Q2 Lm VOUT Cout S2 GND MP6924 MP6924A C2 VG2 VG1 2 PGND VDD 7 LL VD1 6 VD2 VSS 3 R2 R1 1 4 8 5 C1 MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 1 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER ORDERING INFORMATION Part Number* MP6924GS MP6924AGS Package Top Marketing SOIC-8 See Below * For Tape & Reel, add suffix –Z (e.g. MP6924GS–Z) TOP MARKING (MP6924GS) MP6924: Part number LLLLLLLL: Lot number MPS: MPS prefix Y: Year code WW: Week code TOP MARKING (MP6924AGS) MP6924A: Part number LLLLLLLL: Lot number MPS: MPS prefix Y: Year code WW: Week code MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 2 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER PACKAGE REFERENCE TOP VIEW VG2 1 PGND 2 MP6924 MP6924A 8 VG1 7 VDD LL 3 6 VD1 VD2 4 5 VSS SOIC-8 ABSOLUTE MAXIMUM RATINGS (1) VDD to VSS .................................... -0.3V to +38V PGND to VSS ............................... -0.3V to +0.3V VG to VSS ...................................... -0.3V to +20V VD to VSS ....................................... -1V to +180V LL to VSS ..................................... -0.3V to +6.5V Continuous power dissipation (TA = +25°C) (2) SOIC-8 ......................................................1.4W Junction temperature ............................... 150°C Lead temperature (solder) ....................... 260°C Storage temperature ................ -55°C to +150°C Recommended Operation Conditions (3) Thermal Resistance (4) θJA θJC SOIC-8 ................................... 90 ...... 45 ... °C/W NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. VDD to VSS ....................................... 4.2V to 35V Operating junction temp. (TJ). .. -40°C to +125°C MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 3 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER ELECTRICAL CHARACTERISTICS VDD = 12V, -40°C ≤ TJ ≤ +125°C, unless otherwise noted. Parameter VDD voltage range VDD UVLO rising VDD UVLO hysteresis Symbol Operating current ICC Quiescent current IQ Shutdown current Conditions Min 4.2 3.7 0.13 CLOAD = 4.7nF, FSW = 100kHz VSS - VD = 0.5V VDD = 4V, LL = 0V VDD = 20V, LL = 0V Light-load mode current MP6924 Thermal shutdown (5) MP6924A Thermal shutdown hysteresis(5) Control Circuitry Section MP6924 VSS - VD forward voltage MP6924A Turn off threshold (VSS - VD) MP6924 MP6924A Turn-on delay MP6924 MP6924A Input bias current on VD Turn-on blanking time Turn-off blanking time (5) MP6924 MP6924A Turn-off blanking VDS threshold(MP6924A disabled) tDon CLOAD = 4.7nF, VGS = 2V tDon CLOAD = 10nF, VGS = 2V tB_ON VD = 180V CLOAD = 4.7nF tB_OFF CLOAD = 4.7nF VB_OFF Light-load enter pulse width Light-load turn-on pulse width hysteresis MP6924 Light-load enter delay MP6924A Gate disable threshold on LL Turn-on threshold (VDS) Gate Driver Section VG (low) TLL RLL = 100kΩ TLL-H RLL = 100kΩ TLL-D VLL_DIS VLL_DS VG_L VG (high) VG_H Turn-off propagation delay tDoff Turn-off total delay tDoff Maximum source current (6) Pull-down impedance 28 17 -56 Vfwd VDD = 12V ILOAD = 1mA VDD > 10V VDD ≤ 10V VD = VSS VD = VSS, CLOAD = 4.7nF, RGATE = 0Ω, VGS = 2V VD = VSS, CLOAD = 10nF, RGATE = 0Ω, VGS = 2V MP6924 MP6924A NOTES: 5) Guaranteed by characterization. 0.75 Typ 3.95 0.185 Max 35 4.2 0.24 Units V V V 16 20 mA 4.6 135 155 175 150 175 10 6 190 210 225 mA 45 29 -40 80 190 90 270 58 41 -20 140 300 180 410 1 1.65 1.1 µA °C °C 210 1750 mV mV ns ns µA µs ns 1 1.7 2.5 V 1.7 2.3 3 µs 0.45 0.5 45 0.1 -330 1 78 0.2 -230 11.5 VDD 15 µs 1.52 121 0.3 -130 ms µs V mV 0.1 13 V V ns 35 80 ns 45 100 ns 0.5 0.13 0.6 6) µA A 1.5 Ω Guaranteed by design. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 4 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER TYPICAL PERFORMANCE CHARACTERISTICS VDD = 12V, MP6924/MP6924A, unless otherwise noted. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 5 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD = 12V, unless otherwise noted. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 6 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD = 12V, unless otherwise noted. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 7 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER PIN FUNCTIONS Pin # (SOIC-8) 1 2 Name Description VG2 PGND 3 LL 4 5 6 VD2 VSS VD1 MOSFET 2 gate driver output. Power ground. PGND is the power switch return. Light-load timing setting. Connect a resistor to LL to set the light-load timing. Leave LL open to prevent the IC from entering light-load mode. Pull LL low to disable the gate driver. MOSFET 2 drain voltage sense. Source pin used as reference for VD1 and VD2. MOSFET 1 drain voltage sense. 7 8 VDD VG1 Supply voltage. MOSFET 1 gate driver output. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 8 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER BLOCK DIAGRAM LL VDD PGND VD1 VG1 VSS VG2 VD2 Figure 1: Functional Block Diagram MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 9 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER OPERATION The MP6924, MP6924A operates in discontinuous conduction mode (DCM), continuous conduction mode (CCM), and critical conduction mode (CrCM). When the MP6924, MP6924A operates in either DCM or CrCM, the control circuitry controls the gate in forward mode, and the gate turns off when the MOSFET current is low. In CCM, the control circuitry turns off the gate during very fast transients. Turn-On Phase When the switch current flows through the body diode of the MOSFET, there is a negative voltage drop (VD - VSS) across the body diode. VDS is much lower than the turn-on threshold of the control circuitry (VLL-DS), which triggers a maximum 500mA of charge current to turn on the MOSFET (see Figure 3). Under-Voltage Lockout (UVLO) When VDD is below the VDD UVLO threshold, the MP6924, MP6924A falls into sleep mode and VG1,2 remains at a low level. Turn-On Blanking The control circuitry contains a blanking function that ensures that when the MOSFET turns on or off, it remains in that state for tB_ON (~1.1µs), which determines the minimum on time. During the turn-on blanking period, the turn-off threshold is not blanked completely, but changes to about +100mV (instead of +40mV). This ensures that the part can always turn off, even during the turn-on blanking period, although it does so slower. Avoid setting the synchronous period below tB_ON in CCM condition in the LLC converter to eliminate shoot-through. Enable If LL is pulled low, the MP6924, MP6924A is in shutdown mode, which consumes 175µA of shutdown current. If LL is pulled high during the rectification cycle, the gate driver will not appear until the next rectification cycle begins (see Figure 2). Conduction Phase When VDS rises above the forward voltage drop (-Vfwd) according to the decrease of the switching current, the MP6924, MP6924A pulls down the gate voltage level to make the on resistance of the synchronous MOSFET larger to ease the rise of VDS. VD Clamp Because VD1,2 can go as high as 180V, a highvoltage JFET is used at the input. To prevent excessive currents when VDS1,2 goes below -0.7V, a 1kΩ resistor is recommended between VD1,2 and the drain of the external MOSFET. VDS VDS +40mV -Vfwd -230mV VGS Driver begin to be pulled down VGS Driver turn off Will not start gate driver until next cycle LL Turn On Blanking Turn Off Blanking Figure 3: Turn-On/-Off Timing Diagram Figure 2: LL Control Scheme Thermal Shutdown If the junction temperature of the chip exceeds thermal shutdown threshold, VG1,2 is pulled low, and the MP6924, MP6924A stops switching. The IC resumes normal function after the junction temperature drops 10°C. The control scheme in Figure 3 shows VDS adjusted to be around -Vfwd, even when the current through the MOSFET is fairly low. This function puts the driver voltage at a very low level when the synchronous MOSFET is turning off, which boosts the turn-off speed. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER Turn-Off Phase When VDS rises to trigger the turn-off threshold (+40mV), the gate voltage is pulled to zero after a very short turn-off delay (see Figure 3). Turn-Off Blanking After the gate driver is pulled to zero by VDS reaching the turn-off threshold (+40mV), turn-off blanking is triggered to ensure that the gate driver is off for at least tB_ON to prevent an error trigger on VDS. Light-Load Latch-Off Function The gate driver of the MP6924, MP6924A is latched off to save driver loss in light-load condition and improve efficiency. When the MOSFET’s switching cycle conducting period falls below TLL, the MP6924, MP6924A enters light-load mode and latches off the MOSFET after a light-load enter delay, TLL-D (see Figure 4). Light-Load Mode tLL+tLL-H Light-Load Mode tLL+tLL-H tLL+tLL-H Secondary Side Current Figure 5: MP6924, MP6924A Exiting Light-Load Mode If the light-load mode of the MP6924, MP6924A ends during the rectification cycle, the gate driver signal does not appear until the next rectification cycle starts (see Figure 6). VDS VGS Normal Mode tLL+tLL-H Normal Mode Will not start gate driver until next cycle TLL-D Light Load Mode tLL Normal Mode tLL Figure 6: Gate Driver Starts After Exiting LightLoad Mode tLL Anti-Bounce Logic (MP6924) The MP6924 has anti-bounce logic, which helps protect the two-channel driver against cross conduction. MP6924A disables this feature. Secondary Side Current Figure 4: MP6924, MP6924A Entering Light-Load Mode During light-load mode, the MP6924, MP6924A monitors the body diode conduction time. If this time exceeds TLL + TLL-H, the IC exits light-load mode and initiates the gate driver in the next new switching cycle (see Figure 5 and Figure 6). Light-load enter timing (TLL) is programmable by connecting a resistor (RLL) to LL. By monitoring the LL current (the LL voltage is kept at ~2V internally), TLL can be calculated with Equation (1): TLL = RLL (k)  2.3us 100k Figure 7 shows the anti-bounce logic for the two-channel driver. When channel 1 or 2 are turned off, the corresponding channel gate driver is blanked until another channel is switched off. VDS2 VDS1 VGS1 VGS2 (1) VGS1 Blanking VGS2 Blanking Figure 7: Anti-Bounce Logic of the Gate Driver MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 11 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER APPLICATION INFORMATION Layout Considerations Listed below are the main recommendations that should be taken into consideration when designing the PCB. Sensing for VD/VS 1. Keep the sensing connections (VD1/VSS, VD2/VSS) as close to each of the MOSFETs (drain/source) as possible. 2. Keep the two channels’ sensing loops separated from each other. 3. Make the sensing loop as small as possible (see Figure 8). System Power Loop 1. Keep the two channels’ power loops separated from each other (see Figure 10). This minimizes the interaction between the two channels’ power loops, which may affect the voltage sensing of the IC. 2. Make the power loop as small as possible to reduce parasitic inductance. S1 T Power loops separated from each other VOUT Cout MP6924 MP6924A S2 GND VD1 Sensing loop as small as possible G D S Sensing connections close to MOSFET VSS VD2 Sensing loops separated from each other G D S Figure 8: Sensing for VD/VS Figure 9 shows a layout example of the MP6924, MP6924A driving PowerPAK SO8 package MOSFETs with two, separate, small sensing loops. MP6924/24A Figure 10: System Power Loop Figure 11 shows a layout example of the power loop trace, which has a minimized loop length. The two channel power traces do not cross each other. It is highly recommended to place the driver’s sensing loop trace away from the power loop trace (see Figure 11). The sensing loop trace and power loop trace can be placed on different layers to keep them separate from each other. Do not place the driver IC inside the power loop; this may affect MOSFET voltage sensing. Q2 COUT Q1 Q2 LAYOUT TRACE COMPONENTS PAD Figure 9: Layout Example for Sensing Loop and VDD Decoupling Q1 VDD Decoupling Capacitor LAYOUT TRACE 1. Place a decoupling capacitor no smaller than 1µF from VDD to PGND close to the IC for adequate filtering (see Figure 10). COMPONENTS PAD Figure 11: Layout Example for System Power Loop MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 12 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER SR MOSFET Selection and Driver Ability Power MOSFET selection is a trade-off between RDS(ON) and Qg. To achieve high efficiency, a MOSFET with a smaller RDS(ON) is recommended. A larger Qg with a smaller RDS(ON) makes the turn-on/-off speed lower and the power loss larger. For the MP6924, MP6924A, VDS is adjusted at Vfwd during the driving period. A MOSFET with a small RDS(ON) is not recommended because the gate driver may be kept at a fairly low level with a small RDS(ON), even when the system load is high, which makes the advantage of the low RDS(ON) inconspicuous. Qg of the MOSFET affects the turn-on and turnoff delay. Figure 3 indicates the turn-on delay (tDon) and the turn-off delay (tDoff). tDon indicates how long the body diode conducts before the MOSFET is turned on, while tDoff indicates how long the driver takes to turn off the MOSFET. With a higher turn-on delay, the body diode conduction duration of the MOSFET is longer, which brings down the total efficiency. However, with a higher turn-off delay, the shoot-through risk is higher in CCM operation. Figure 13 and Figure 14 show the tDon and tDoff of the MP6924, MP6924A according to different Cload values. Figure 12 shows the typical waveform of the LLC on the secondary side. To achieve a fairly high usage of the MOSFET’s RDS(ON), it is expected that the MOSFET driver voltage is kept at the maximum level until the last 25% of the SR conduction period. Calculate VDS with Equation (2): VDS = −Rds(ON)  2  Ipeak = −Rds(ON)  IOUT = − Vfwd (2) 2 Where VDS is drain-source voltage of the MOSFET. The MOSFET’s RDS(ON) is recommended to be no lower than ~Vfwd/IOUT (mΩ). For example, in a 10A application with Vfwd at 45mV, the RDS(ON) of the MOSFET is recommended to be no lower than 4.5mΩ. Figure 13: Turn-On Delay vs. Cload ISR Ipeak VG 25% SR Conduction Period Figure 12: Synchronous Rectification Typical Waveform in LLC Figure 14: Turn-Off Delay vs. Cload MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 13 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER When plugging the values from Equation (4) and Equation (5) into Equation (3), the turn-on delay power loss through the SR MOSFET’s body diode can be derived with Equation (6): Ipeak VDS IDS Pon = Body diode conducts VF VGS tDon Figure 15: Turn-On Delay Effect on Efficiency Figure 15 shows how tDon affects system efficiency. During tDon, the body diode of the SR MOSFET conducts, which leads to a power loss that can be calculated with Equation (3): V I Pon  F F  2fs  tDon = VF  IF  fs  tDon 2 (3) Where VF is the body diode forward voltage drop, IF is the switching current when the turnon delay (tDon) has ended, and fs is the switching frequency. When considering the switching current as a complete sine wave, IF can be estimated with Equation (4) and Equation (5): IF = Ipeak  sin(2  fs  tDon  ) Ipeak    Iout 2 (4) (5) Where Ipeak is the peak switching current through the MOSFET, and Iout is the system output current.   Iout  VF  fs  tDon  sin(2  fs  tDon  ) (6) 2 Figure 16 shows how different turn-on delay values affect efficiency according to different output voltages. To keep the body diode conduction loss at a fairly low level (below 0.5% of the output power), the turn-on delay is recommended to be less than 5% of the switching cycle. For example, in a fsw = 200kHz LLC system, the switching cycle is ~5µs, and it is recommended to select the MOSFET to make tDon < 250ns. 6 Ratio of Body-diode Conduction Loss to Output Power (%) IF Vout=5V Vout=12V Vout=24V 5 4 3 2 1 0 0 5 10 15 20 25 Ratio of Turn-on Delay to Switching Cycle (%) Figure 16: Turn-On Delay vs. Power Loss The turn-off delay (tDoff) is critical in some fast transient CCM applications. Choose the MOSFET to make tDoff below the CCM current transient duration. Otherwise, the MOSFET may need to be selected with a lower Qg, or an external totem pole driver circuit may be added to prevent shoot-through. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 14 MP6924, MP6924A – FAST TURN-OFF, CCM/DCM COMPATIBLE DUAL LLC SYNCHRONOUS RECTIFIER PACKAGE INFORMATION SOIC-8 NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP6924, MP6924A Rev. 1.02 www.MonolithicPower.com 9/15/2017 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 15