MP8003A
IEEE 802.3af/at, PoE,
Powered Device, Interface Controller
DESCRIPTION
FEATURES
The MP8003A is an IEEE, 802.3af/at, Power
over Ethernet (PoE) compliant, powered device
(PD), interface controller. The MP8003A has all
the functions of IEEE 802.3af/at, including
detection, 1-event and 2-event classification,
input current control, and a 100V hot-swap
MOSFET.
The MP8003A sets the inrush current limit at
about 120mA during start-up and switches to
840mA when the output pass MOSFET is
turned on completely. A PG signal set to high
indicates when the output is fully charged and
pulls low when the output drops under the
overload condition. The MP8003A also provides
a T2P signal when it is connected to Type-2
power sourcing equipment (PSE).
Compatible with 802.3af/at Specifications
100V, 0.48Ω Integrated Pass Switch
120mA Inrush Current Limit
840mA Operation Current Limit
2-Event Classification
Auxiliary Adapter O-Ring Power Supply
Self-Driving Power Good Inductor
Open-Drain Type-2 PSE Indicator
Over-Temperature Protection (OTP)
Available in QFN-10 (3mmx3mm) Package
APPLICATIONS
An auxiliary power input detector (AUX)
provides a smooth power switch from PSE to
an auxiliary wall adapter. The MP8003A also
features built-in thermal protection and a wideinput UVLO hysteresis.
IEEE 802.3af/at-Compliant Devices
Security Cameras
VoIP Phones
WLAN Access Points
IoT Devices
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
The MP8003A is available in a QFN-10
(3mmx3mm) package.
TYPICAL APPLICATION
VDD
R1
VDD
DET
C1
C2
D1
CLASS
48V from
PSE
PG
R2
VSS
DC/DC
Converter
EN
MP8003A
VSS
FTY
AUX
T2P
RTN
R3
Adaptor
R4
D2
D3
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
ORDERING INFORMATION
Part Number*
MP8003AGQ
Package
QFN-10 (3mmx3mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8003AGQ–Z)
TOP MARKING
ANU: Product code of MP8003AGQ
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
VSS
1
10
RTN
FTY
2
9
NC
CLASS
3
8
PG
T2P
4
7
VDD
AUX
5
6
DET
QFN-10 (3mmx3mm)
MP8003A Rev. 1.0
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (6)
VDD, RTN, DET, T2P, AUX to VSS ...................
.................................................. -0.3V to +100V
CLASS, FTY to VSS ................... -0.3V to +6.5V
PG to RTN .................................. -0.3V to +6.5V
AUX to VDD............................ -6.5V to +0.3V (2)
T2P sinking current ................................... 10mA
AUX sinking current .............................. -5mA (2)
PG sinking current ................................. 1mA (3)
Continuous power dissipation (TA = +25°C) (4)
..................................................................2.5W
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +150°C
QFN-10 (3mmx3mm) ............ 50 ....... 12 ... °C/W
Recommended Operating Conditions (5)
Supply voltage (VDD) .......................... 0V to 57V
T2P sinking current .....................................5mA
Maximum AUX sinking current .............. -3mA (2)
Maximum PG sinking current .............. 0.6mA (3)
Operating junction temp (TJ) .... -40°C to +125°C
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) When VDD to the adapter ground voltage is high, the AUXVDD voltage may exceed -6.5V if the divider resistor is not
appropriate. In this condition, VDD clamps the -6.5V voltage
on AUX, but the current should be limited by the external
resistor.
3) If PG is pulled up higher than 6.5V externally, the pull-up
current should be limited. Refer to the Power Good (PG)
Indicator Signal section on page 14 for more details.
4) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
5) The device is not guaranteed to function outside of its
operating conditions.
6) Measured on JESD51-7, 4-layer PCB.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
ELECTRICAL CHARACTERISTICS
VDD = 48V, all voltages are with respect to VSS, RDET = 24.9kΩ, RCLASS = 28.7Ω, TJ = -40°C to
+125°C, typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Detection on
VDET-ON
VDD rising
Detection off
VDET-OFF
VDD rising
11
VDET = VDD = 57V, measure IDET
VDD = 10.1V, float DET, not in
mark event, measure ISUPPLY
VDD = 2.5V, measure ISUPPLY
VDD = 10.1V, measure ISUPPLY
0.1
Max
Units
Detection
DET leakage current
IDET-LK
Bias current
Detection current
IDET
1.9
96
395
99
410
V
V
5
μA
12
μA
102
425
μA
μA
Classification
Classification stability time
VCLASS output voltage
μs
90
VCLASS
13V < VDD < 21V
1.1
1mA < ICLASS < 42mA
13 ≤ VVDD ≤ 21V, guaranteed by VCLASS
RCLASS = 578Ω, 13V ≤ VDD ≤ 21V
1.8
1.16
1.21
2
2.4
V
RCLASS = 110Ω, 13V ≤ VDD ≤ 21V
RCLASS = 62Ω, 13V ≤ VDD ≤ 21V
RCLASS = 41.2Ω, 13V ≤ VDD ≤ 21V
RCLASS = 28.7Ω, 13V ≤ VDD ≤ 21V
9.9
17.7
26.6
38.2
10.55
18.7
28.15
40.4
11.3
19.8
29.7
42.6
VCL-ON
Regulator turns on, VDD rising
11.8
12.5
13
V
VCL-OFF
Regulator turns off, VDD rising
21
22
23
V
Classification hysteresis
VCL-HYS
Low-side hysteresis
High-side hysteresis
Mark event reset threshold
Max mark event voltage
Mark event current
Mark event resistance
IC supply current during
classification
CLASS leakage current
UVLO
VMARK-L
VMARK-H
IMARK
RMARK
2-point measure at 7V and 10V
IIN-CLASS
VDD = 17.5V, CLASS floating
ILEAKAGE
VCLASS = 0V, VDD = 57V
VDD-VSS-R
VDD rising
35
VDD-VSS-F VDD falling
VDD-VSS-HYS
29
4.9
Classification current
Classification lower
threshold
Classification upper
threshold
VDD turn on threshold
VDD turn off threshold
VDD UVLO hysteresis
IC supply current during
operation
ICLASS
IIN
0.8
0.5
4.5
11
0.5
mA
V
5
11.5
1.5
5.5
12
2
12
V
V
mA
kΩ
220
300
μA
1
μA
37.5
40
V
31
33
V
V
450
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μA
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VDD = 48V, all voltages are with respect to VSS, RDET = 24.9kΩ, RCLASS = 28.7Ω, TJ = -40°C to
+125°C, typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Pass Device and Current Limit
On resistance
Leakage current
Current limit
Inrush limit
Inrush current termination
Inrush to operation mode
delay
Current foldback threshold
RON-RTN
IRTN-LK
ILIMIT
IINRUSH
IRTN = 600mA
1
15
μA
720
840
120
1.2
920
mA
mA
V
80
100
ms
VRTN rising
VRTN rising to inrush current
foldback
10
V
1
ms
IT2P = 2mA, respect to VSS
VT2P = 48V
0.1
VDD = VRTN = 57V
VRTN = 1V
VRTN = 2V
VRTN falling
TDELAY
Foldback deglitch time
Ω
0.48
T2P
T2P output low voltage
T2P high leakage current
AUX
AUX high threshold
voltage(7)
AUX low threshold voltage(7)
AUX leakage current
PG
Respect to VDD
Respect to VDD
VDD - VAUX = 6V
PG output high voltage
PG source current
PG pull-down resistance
Thermal Shutdown
Thermal shutdown
temperature(8)
Thermal shutdown
hysteresis(8)
PG floating
PG = high, force PG = 4V
PG is logic low, pull PG up to 1V
0.3
1
V
μA
-2.3
V
2
V
μA
-0.6
5.5
1000
V
μA
kΩ
TSD
150
°C
THYS
20
°C
7
NOTES:
7) VDD - AUX > 2.3V, IC enable adapter input. If VDD - AUX < 0.6V, IC enables the PSE input. Refer to the Wall Power Adapter Detection
and Operation section on page 12 for the AUX setting.
8) Guaranteed by engineering sample characterization.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = (VDD - VSS) = 48V, RDET = 24.9kΩ, RCLASS = 28.7Ω, TA = 25°C, unless otherwise noted.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = (VDD - VSS) = 48V, RDET = 24.9kΩ, RCLASS = 28.7Ω, TA = 25°C, unless otherwise noted.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = (VDD - VSS) = 48V, RDET = 24.9kΩ, RCLASS = 28.7Ω, TA = 25°C, unless otherwise noted.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
PIN FUNCTIONS
PIN#
Name
1
VSS
2
FTY
3
CLASS
4
T2P
5
AUX
6
DET
7
VDD
8
PG
9
NC
10
RTN
Description
Negative power supply terminal from the PoE input power rail.
Factory use only. FTY must be connected to VSS during application.
Power class. Connect resistor from CLASS to VSS to program the classification
current.
Type-2 PSE indictor, open-drain output. T2P is pulled low to VSS to indicate the
presence of a Type-2 PSE or if AUX is enabled.
Auxiliary power input detector. Use AUX for adapter auxiliary power applications.
Drive VDD - AUX higher than 2.3V to disable the hot-swap MOSFET and CLASS
function and force T2P and PG active.
Detection. Connect a 24.9kΩ resistor between VDD and DET for PoE detection.
Positive power supply terminal from the PoE input power rail.
PD supply power good indicator. The PG signal can be used to enable the
downstream DC/DC converter. PG is pulled up by an internal current source in outputhigh condition and can be floated during application.
No connection. NC is not connected internally, but can be connected to VSS and the
exposed thermal pad during layout.
Drain of PD hot-swap MOSFET. Connect the next stage DC/DC converter’s power
return terminal to RTN.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
BLOCK DIAGRAM
VDD
AUX
24.9kΩ
DET
Detection
2.7V - 10.1V
Inrush and
Current Limit
T2P
Start-Up Delay
Control
CLASS
Classification
14.5V - 20.5V
Mark Event
6.9V - 10.1V
CLOAD
Control Logic
and
Gate Driver
RCLASS
Current /
Voltage Sense
VSS
Current
PG
5.5V
RTN
Figure 1: Functional Block Diagram
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
The MP8003A is an IEEE 802.3af/at PoE PD
interface. The MP8003A operates as a safety
device that supplies voltage only when the
power sourcing equipment recognizes a unique,
tightly specified resistance at the end of an
unknown length of Ethernet cable. If the PSE
sees the correct load, then it increases the
applied voltage further to enter the classification
operation range and switch on the nominal 48V
power to the load. Figure 2 shows the typical
PD interface power operation sequence.
OPERATION
Compared with IEEE 802.3af, the IEEE 802.3at
standard establishes a higher power allocation
for Power over Ethernet (PoE) while
maintaining backwards compatibility with
existing IEEE 802.3af systems. Power sourcing
equipment (PSE) and powered devices (PD)
are distinguished as Type-1 (complying with
IEEE 802.3af power levels) or Type-2
(complying with the IEEE 802.3at power levels).
The IEEE 802.3af/at standard establishes a
method of communication between PD and
PSE with detection, classification, and event
mark.
Voltage
57V
42.5V
37V
On
Range
Classification
Range
Class Event 2
20.5V
37-57V (af)
Class Event 1
14.520.5V
14.5V
Signature
Range
6.9V
V2
42.5-57V (at)
IEEE 802.3at
Start-Up
2.710.1V
10.1V
IEEE 802.3af
Start-Up
Mark
Range
6.9-10.1V
V1
Turn
On
Mark Event
2.7V
Reset
Signature
Classification
Intermediate Idle
ON
Time
Figure 2: PD Interface Operation Description
Detection
RDET connected between DET and VDD is
presented as a load to the PSE in detection
mode. When the PSE applies two safe voltages
between 2.7V to 10.1V while measuring the
change in current drawn to determine the load
resistance. A 24.9kΩ (1%) resistor between
VDD and DET is recommended to present one
correct signature. The valid signature
resistance seen from the power interface (PI) is
between 23.7kΩ and 26.3kΩ.
Classification
The classification mode can specify the
expected load range of the device under power
to the PSE so that the PSE can distribute power
intelligently to as many loads as it can within its
maximum current capability. The classification
mode is active between 14.5V and 20.5V. The
MP8003A presents a current in classification
mode (see Table 1).
The detection resistance seen from the PI is the
result of the input bridge resistance in series
with the VDD load. The input bridge resistance
is cancelled partially by the effective leakage
resistance during detection.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
Table 1: Class Resistor Selection
Class
0
1
2
3
4
Max Input
Power to PD
(W)
12.95
3.84
6.49
12.95
25.5
Classification
Current (mA)
RCLASS
(Ω)
2
10.55
18.7
28.15
40.4
578
110
62
41.2
28.7
2-Event Classification
The MP8003A can be used as a Type-1 PD
class 0-3 (as shown in Table 1). It also
distinguishes class 4 with 2-event classification.
If VDD - VSS drops below the input falling
UVLO threshold, the hot-swap MOSFET is
disabled.
If the output current overloads on the internal
pass MOSFET, the current limit works, and
VRTN - VSS rises. If VRTN rises above 10V for
longer than 1ms or rises above 20V, the current
limit reverts to the inrush value and pulls down
PG simultaneously.
Figure 3 shows the current limit, PG, and T2P
work logic during start-up from the PSE power
supply.
PSE Power On
In 2-event classification, the Type-2 PSE reads
the power classification twice. Figure 2 shows
an example of a 2-event classification. The first
classification event occurs when the PSE
presents a voltage between 14.5V to 20.5V to
the MP8003A, and the MP8003A presents a
class-4 load current. The PSE then drops the
input voltage into the mark voltage range of
6.9V to 10.1V signaling the first mark event.
The MP8003A presents a load current between
0.5mA to 2mA in the mark event voltage range.
The PSE repeats this sequence, signaling the
second classification and second mark event.
The PSE then applies power to the MP8003A,
which charges up the downstream DC/DC input
capacitor (C2) with a controlled inrush current.
When C2 is fully charged, T2P presents an
active low signal with respect to VSS after
TDELAY. The T2P output becomes inactive when
the MP8003A input voltage (VDD) falls below
UVLO (see Figure 3).
Under-Voltage Lockout (UVLO) and Current
Limit
When the PD voltage is powered by PSE, and
VDD is higher than the turn-on threshold, the
hot-swap switch starts passing a limited current
(IINRUSH) to charge the downstream DC/DC
converter’s input capacitor. The start-up
charging current is around 120mA.
If RTN drops below 1.2V, the hot-swap current
limit switches to 840mA. After the TDELAY from
UVLO begins, the MP8003A asserts the PG
signal and switches from start-up mode to
normal operation mode. The PG signal can
enable the downstream DC/DC converter
directly.
VDD > UVLO_R?
No
Yes
120mA Inrush
100ms Timer
VRTN-Vss < 1.2V?
Timer-out?
No
Yes
Yes
Current Limit
change to 840mA
Both are OK
PG rises to high
No
VRTN>10V
for 1ms
Or VRTN>20V?
Yes
PG drops
T2P acts based
on PSE type
VDD < UVLO_F?
No
Yes
T2P resets
PSE Power Off
Figure 3: Start-Up Sequence
Wall
Power
Adapter
Detection
and
Operation
For applications where an auxiliary power
source such as a wall adapter is used to power
the device, the MP8003A features wall power
adapter detection (see Figure 4). Once the
input voltage (VDD - VSS) exceeds about
11.5V, the MP8003A enables wall adapter
detection. The wall power adapter detection
resistor divider is connected from VDD to the
negative terminal of an adapter. DADP3 in Figure
4 is added for more accurate hysteresis. There
is a -2.3V turn-on voltage from AUX to VDD for
adapter detection.
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
The adapter is detected when Equation (1) is
met:
VDD VAUX (VADP VDADP3 )
RADPUP
2.3V
RADPUP RADPDOWN
(1)
Where VADP is the adapter voltage, VDADP3 is the
Zener voltage, and RADPUP and RADPDOWN are the
AUX divider resistors from the adapter power.
If applied adapter voltage is much higher than
the design adapter voltage, the VDD - VAUX
voltage is high. If the applied adapter voltage is
higher than 6.5V, the MP8003A inner circuit
clamps the VDD - VAUX voltage at 6.5V. A
current then flows out through AUX. The current
should be limited below 3mA by an external
resistor (RADPUP/RADPDOWN or RT from the resistor
divider to AUX).
Power Good Indicator (PG)
The PG signal is driven by the internal current
source. After TDELAY from UVLO starts, and RTN
drops to 1.2V, or a wall power adapter is
detected, the PG signal is pulled high to
indicate the output power condition and enable
the downstream DC/DC converter. Figure 3
shows the PG logic when powered from PSE.
PG is high if the adapter is detected.
Thermal Shutdown
The MP8003A has a temperature protection
circuit. When the junction temperature exceeds
150°C, the IC shuts down. The IC recovers with
limited inrush current if the junction temperature
drops below 130°C.
To make the MP8003A work stably with adapter
power, one Schottky diode (DADP1, D2 in the
schematic on page 1) is required between the
negative terminal of the adapter and VSS. DADP2
(D3 in the schematic on page 1) is used to
block reverse current between the adapter and
PSE power source. When a wall adapter is
detected, the internal MOSFET between RTN
and VSS turns off, the classification current is
disabled, and T2P becomes active. The PG
signal is active when the adapter power is
detected so that it can enable the downstream
DC/DC converter, even if the input hot-swap
MOSFET is disabled.
MP8003A
To DCDC
VDD
2.3V
From PSE
Shut down Hot-swap
Shut down Classification
Pull up PG
+
AUX
-
VSS
Adaptor
RTN
R ADPUP
R ADPDOWN
DADP3
DADP1
DADP2
Figure 4: Adapter Power Detection
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MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
APPLICATION INFORMATION
Detection Resistor
In detection mode, a resistor connected
between DET and VDD is required as a load to
the PSE. The resistance is calculated as ∆V/∆I
with an acceptable range of 23.7kΩ to 26.3kΩ.
Use a typical value of 24.9kΩ as a detection
resistor.
Classification Resistor
To distribute power to as many loads as
possible from PSE, a resistor between CLASS
and VSS is used to classify the PD power level,
which draws a fixed current set by the
classification resistor. The supplied power set
by the classification resistor is shown in Table 1.
The typical voltage on CLASS is 1.16V in the
classification range and produces about 47mW
of power loss on the CLASS resistor, even in
class-4 condition.
Protection TVS
To limit the input transient voltage within the
absolute maximum ratings, a TVS across the
rectified voltage (VDD - VSS) must be used. A
SMAJ58A TVS or equivalent is recommended
for general indoor applications. Outdoor
transient levels or special applications require
additional protection.
PD Input Capacitor
A 0.05μF to 0.12μF input bypass capacitor from
VDD to VSS is needed for IEEE 802.3at
standard specifications. Typically, a 0.1μF,
100V, ceramic capacitor is sufficient.
Wall Power Adapter Detection Circuit
When an auxiliary power source, such as a wall
power adapter, is used to power the device,
the divider resistors, RADPUP, RADPDOWN, and
DADP3 should be chosen to satisfy Equation (1)
for correct wall power adapter detection (see
Figure 5).
RADPUP with a typical 3kΩ value is
recommended to balance power loss and DADP1
and DADP2 leakage current discharge.
VADP
VDD
Q PG
RPG2
R ADPUP
AUX
PG
RPG1
RPG3
R ADPDOWN
VSS
RTN
DADP3
Adaptor GND
DADP1
DADP2
Figure 5: Wall Adapter Detection Circuit
One small Schottky diode with a 100V voltage
rating, such as BAT46W, is suggested for
DADP1, typically. The voltage rating of DADP2
must also be 100V or higher, while the current
rating must be higher than the load current. A
low voltage drop Schottky diode, such as
SS1H10, is recommended to reduce conduction
power loss. The MP8003A enables wall adapter
detection when VDD is 11.5V. If one adapter
power with a lower voltage rating (such as 10V)
is used to power the converter, one external PG
pull-up circuit is necessary to enable the
downstream DC/DC converter.
Power Good (PG) Indicator Signal
The MP8003A integrates one PG indicator.
Since PG is pulled high through an internal pullup current source when the logic is high, it can
be used to enable the downstream DC/DC
converter without an external pull-up circuit. PG
disables the internal pull-up current and is
pulled low through a 1MΩ internal resistor when
PG is in a logic-low state. If there is a low
resistance pulling down on EN of the
downstream converter, some external PG pullup current is needed. The MP8003A can
provide 7µA of pull-up current. If PG is pulled
up higher than the 5.5V power source, the PG
sink current should be limited to protect the
internal clamp Zener diode. Normally, an input
current 0.6mA or lower on PG is suggested.
If one adapter power less than 11.5V is
connected to supply the converter, the PG
function cannot work with such a low input. The
external PG pull-up circuit is recommended
(see Figure 5). Typically, QPG requires a VCE
voltage higher than 100V, such as BSS63LT1.
Choose RPG2 = 7.5kΩ and RPG3 = 100kΩ for a
12V adapter with some adapter regulation
margin, and choose RPG1 = 100kΩ to limit the
PG sink current.
MP8003A Rev. 1.0
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7/14/2016
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14
MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
T2P Indicator Connection
T2P is an active-low, open-drain output which
indicates the presence of a Type-2 PSE or
adapter power. An optocoupler is used as the
interface from T2P to the circuitry on the output
of the converter, typically (see Figure 6). A
high-gain optocoupler and a high-impedance
receiver (i.e.: CMOS) are recommended.
VOUT of DC/DC
VDD
IT2P
RT2P
IT2P-OUT
RT2P-O
Type-2 inductor
low active
3. Place the MP8003A local ground planes
referenced to VSS.
4. Place the next-stage DC/DC converter
ground planes referenced to RTN.
5. Connect the exposed pad to VSS, since it is
used to heat sink the part to the circuit
board traces.
6. Place large copper traces and vias on the
exposed pad and VSS trace for thermal
dissipation.
Figure 7 shows the recommended component
placement for the MP8003A based on the
schematic on page 1.
T2P
C2
RTN
VDD/VAPD
If using an LED from VDD to T2P to indicate
T2P activity, the RT2P’s resistance can be higher
to match the LED’s max current and reduce
power loss.
PCB Layout Guidelines
Efficient layout of the PoE front end should
guarantee solid performance, low power loss,
and no EMI/ESD problems. The spacing
between VDD (48V) and VSS must comply with
safety standards such as IEC60950. For best
results, refer to Figure 7 and follow the
guidelines below.
1. Ensure that all component placement
follows the power flow from RJ-45 to the
Ethernet transformer to the diode bridges to
TVS to the 0.1μF capacitor to the DC/DC
converter input bulk capacitor.
2. Make all leads as short as possible with
wide power traces.
6 DET
7VDD
C1
D3
D1
MP8003A
R2
AUX 5
T2P 4
CLASS 3
VSS 1
APD
GND
FTY 2
VSS
D2
Considering the T2P sinking current (typically
2mA), the T2P output low voltage 0.1V, and the
diode forward voltage drop, choose RT2P to be
23.7kΩ. Suppose VOUT of the DC/DC converter
is 12V. To match the typical 48V input, choose
RT2P-O = 20kΩ based on the CRT, though it may
vary with temperature, LED bias current, and
aging.
8 PG
Figure 6: T2P Inductor Circuit
9 NC
10 RTN
R1
R3
R4
Figure 7: Recommended Layout
Design Example
Table 2 is a design example following the
application guidelines for the following
specifications.
Table 2: Design Example
VDD - VSS
RDET
RCLASS
VADAPTER
48V
24.9kΩ
28.7Ω
12V
The typical application circuit in Figure 8 shows
the detailed application schematic, and is the
basis
for
the
Typical
Performance
Characteristics section. Typically, the device is
powered by PSE (VDD - VSS = 48V). When an
adapter voltage above 9.6V is present, the
internal MOSFET between RTN and VSS turns
off. Instead, the device is powered by the
adapter regardless of what the PSE voltage is.
For more detailed device applications, please
refer to the related evaluation board datasheet.
MP8003A Rev. 1.0
www.MonolithicPower.com
7/14/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
15
MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
TYPICAL APPLICATION CIRCUITS
VDD
R1
24.9k
D1
SMAJ58A
C1
0.1μF
100V
R6
R5
7.5k
BSS63LT1
DET
R8
D5
C2
47µF
100k
CLASS
48V from
PSE
Q1
100k
VDD
PG
R2
28.7Ω
VSS
R7
T2P
VSS
FTY
3k
100k
RTN
AUX
R3
R4
1k
EN
MP8003A
DCDC
Converter
MP3910
MP3908
MP6002
MP6004
MP6001
D2
BAT46W
D3
SS1H10
D4
6.8V
Adaptor
Figure 8: Typical Application Circuit, VDD - VSS = 48V, VADAPTER = 12V
VDD
R1
24.9k
C1
0.1μF
100V
D1
SMAJ58A
R3
100k
VDD
C2
47µF
DET
D2
CLASS
48V from
PSE
PG
VSS
R2
28.7Ω
MP8003A
VSS
FTY
AUX
DCDC
Converter
MP3910
MP3908
EN MP6002
MP6004
MP6001
T2P
RTN
Figure 9: Typical Application Circuit, VDD - VSS = 48V, No Adapter Input
MP8003A Rev. 1.0
www.MonolithicPower.com
7/14/2016
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© 2016 MPS. All Rights Reserved.
16
MP8003A – IEEE 802.3af/at, PoE, POWERED DEVICE, INTERFACE CONTROLLER
PACKAGE INFORMATION
QFN-10 (3mmx3mm)
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.18
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
10
1
2.25
2.55
0.50
BSC
5
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
1.70
0.25
2.50
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP8003A Rev. 1.0
www.MonolithicPower.com
7/14/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
17
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