MP8008
Fully Integrated, 802.3af/at-Compliant,
PoE, PD Interface with a
Peak-Current-Mode Flyback Controller
DESCRIPTION
FEATURES
The MP8008 is an integrated, IEEE, 802.3af/at,
PoE-compliant, powered device (PD), power
supply converter. The MP8008 includes PD
interface and a peak-current-mode flyback
controller.
The PD interface has all the functions of IEEE
802.3af/at, including detection, 1-event and 2event classification, 120mA inrush current limit,
840mA operation current limit, and a 100V hotswap MOSFET.
The flyback PWM controller can drive an
external MOSFET capable of handling more
than 10A of current for high-powered flyback
PoE applications. Pulse-skipping mode function
improves efficiency in light-load condition. The
MP8008 flyback features protections including
overload protection (OLP), short output, and
over-voltage protection (OVP).
Compatible with 802.3af/at Specifications
100V, 0.48Ω, PD Integrated Pass Switch
120mA PD Inrush Current
840mA PD Operation Current Limit
Auxiliary Adapter O-Ring Power Supply
PD Power Good and Type-2 PSE Indicator
12V, 1A, Flyback MOSFET Gate Driver
Pulse-Skipping Operation in Light Load
Programmable Switching Frequency: 30kHz
- 400kHz
Frequency Synchronizing from 80kHz 400kHz
Cycle-by-Cycle Current Limit
Overload, Short Circuit, Over-Voltage, and
Thermal Protection
Available in a QFN-28 (4mmx5mm)
Package
APPLICATIONS
The MP8008 can support a front-end solution
for PoE PD applications with minimum external
components and is available in a QFN-28
(4mmx5mm) package.
IEEE 802.3af/at-Compliant Devices
Security Cameras
Video Telephones
WLAN Access Points
IoT Devices
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VDD
VOUT
D1
T1
R7
PSE
Supply
C1
R3
VIN
DET
T2P
VDD
U1
C3
D3
C2
C4
D2
Q1
GATE
PG
R10
EN/SYNC
R4
CLASS
VSS
MP8008
R12
ISENSE
VCC
VSS
RT
U2B
R6
D4
Adapter
MP8008 Rev. 1.0
1/6/2017
C7
FB
R8
R11
SS
GND
R5
R1
C5
COMP
RTN
AUX
R9
U2A
C6
Q2
TL431
R2
D5
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1
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
ORDERING INFORMATION
Part Number*
MP8008GV
Package
QFN-28 (4mmx5mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8008GV–Z)
TOP MARKING
MPS: MPS prefix
Y: Year code
WW: Week code
MP8008: Part number
LLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
NC
28
T2P CLASS FTY
27
26
25
VSS VSS
24
23
AUX
1
22
NC
DET
2
21
RTN
VDD
3
20
RTN
NC
4
19
ISENSE
PG
5
18
SS
GATE
6
17
NC
VCC
7
16
NC
VIN
8
15
NC
9
GND
10
11
12
13
14
RT COMP FB EN/SYNC NC
QFN-28 (4mmx5mm)
MP8008 Rev. 1.0
1/6/2017
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2
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Pins Voltages with Respect to VSS
VDD, RTN, DET, T2P, AUX, GND .....................
.................................................. -0.3V to +100V
CLASS, FTY ............................... -0.3V to +6.5V
QFN-28 (4mmx5mm) ............ 40 ........ 9 .... °C/W
Pins Voltages with Respect to GND (2)
VDD ........................................... -0.3V to +100V
VIN ................................................ -0.3V to 40V
VCC, GATE ................................... -0.3V to 15V
All other pins .................................... -0.3V to 6V
Pins Voltage with Respect to VDD
AUX ........................................ -6.5V to +0.3V (3)
Pin Currents
T2P sink current........................................ 10mA
AUX sink current ................................... -5mA (3)
PG sink current ...................................... 1mA (4)
EN/SYNC sink current ........................ 0.5mA (5)
Continuous power dissipation (TA = +25°C) (6)
................................................................ 3.12W
Maximum operating frequency ............... 500kHz
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -55°C to +150°C
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) GND must be connected to RTN.
3) When VDD to the adapter ground voltage is high, the AUXVDD voltage may exceed -6.5V if the divider resistor is not
appropriate. In this condition, VDD clamps the voltage on
AUX, but the current should be limited by an external resistor.
4) If PG is pulled higher than 6.5V externally, the pull-up current
should be limited. Refer to the Power Good Indicator Signal
on page 22 for more detail.
5) Refer to the Enable/SYNC Control section on page 20.
6) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
7) The device is not guaranteed to function outside of its
operating conditions.
8) Measured on JESD51-7, 2-layer PCB.
Recommended Operating Conditions (7)
Supply voltage (VDD) ........................ 0V to 57V
VIN voltage ........................................ 7V to 35V
Maximum T2P sink current .........................5mA
Maximum AUX sink current................... -3mA (3)
Maximum PG sink current ................... 0.6mA (4)
Maximum EN/SYNC sink current ........ 0.4mA (5)
Operating junction temp. (TJ). .. -40°C to +125°C
MP8008 Rev. 1.0
1/6/2017
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3
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
ELECTRICAL CHARACTERISTICS
VDD, CLASS, DET, T2P, and RTN voltages are referred to VSS. All other pin voltages are
referred to GND. GND and RTN are shorted together. VDD - VSS = 48V, VSS = 0V, VIN = 18V, RDET
= 24.9kΩ, RCLASS = 28.7Ω. TJ = -40°C to +125°C. Typical values are tested at TJ = 25C, unless
otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
Detection on
VDET-ON
VDD rising
1.9
V
Detection off
VDET-OFF
VDD rising
11
V
DET leakage current
VDET-LK
VDET = VDD = 57V, measure IDET
VDD = 10.1V, float DET, not in
mark event, measure ISUPPLY
VDD = 2.5V, measure ISUPPLY
VDD = 10.1V, measure ISUPPLY
0.1
PD Interface Section
Detection (DET)
Bias current
Detection current
IDET
96
395
99
410
5
μA
12
μA
102
425
μA
μA
Classification (CLASS)
Classification stability time
VCLASS output voltage
Classification current
Classification lower
threshold
Classification upper
threshold
Classification hysteresis
Mark event reset threshold
Max mark event voltage
Mark event current
Mark event resistance
IC supply current during
classification
Class leakage current
PD UVLO
VCLASS
ICLASS
VCL-ON
VCL-OFF
VCL-H
RCLASS = 578Ω, 13V ≤ VDD ≤ 21V
RCLASS = 110Ω, 13V ≤ VDD ≤ 21V
RCLASS = 62Ω, 13V ≤ VDD ≤ 21V
RCLASS = 41.2Ω, 13V ≤ VDD ≤ 21V
RCLASS = 28.7Ω, 13V ≤ VDD ≤ 21V
Class regulator turns on,
VDD rising
Class regulator turns off,
VDD rising
Low-side hysteresis
High-side hysteresis
VMARK-L
VMARK-H
IMARK
RMARK
2-point measure at 7V and 10V
IIN-CLASS
VDD = 17.5V, CLASS floating
ILEAKAGE
VCLASS = 0V, VDD = 57V
1.16
1.21
V
1.8
9.9
17.7
26.6
38.2
2
10.55
18.7
28.15
40.4
2.4
11.3
19.8
29.7
42.6
mA
11.8
12.5
13
V
21
22
23
V
0.8
0.5
4.5
11
0.5
VDD turn-on threshold
VDD-VSS-R VDD rising
VDD turn-off threshold
VDD-VSS-F VDD falling
VDD UVLO hysteresis
VDD-VSS-HYS
IC supply current during
IIN
operation
MP8008 Rev. 1.0
1/6/2017
μs
90
13V < VDD < 21V,
1.1
1mA < ICLASS < 43mA
13V ≤ VDD ≤ 21V, guaranteed by VCLASS
35
29
4.9
V
5
11.5
1.5
5.5
12
2
12
V
V
mA
kΩ
220
300
μA
1
μA
40
33
V
V
V
37.5
31
450
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μA
4
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VDD, CLASS, DET, T2P, and RTN voltages are referred to VSS. All other pin voltages are
referred to GND. GND and RTN are shorted together. VDD - VSS = 48V, VSS = 0V, VIN = 18V, RDET
= 24.9kΩ, RCLASS = 28.7Ω. TJ = -40°C to +125°C. Typical values are tested at TJ = 25°C, unless
otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
Pass Device and Current Limit
On resistance
RON-RTN
IRTN = 600mA
1
15
μA
720
840
120
1.2
900
mA
mA
V
80
100
ms
VRTN rising
10
V
VRTN rising to inrush current
foldback
1
ms
IT2P = 2mA, respect to VSS
0.1
Leakage current
IRTN-LK
VDD = VRTN = 57V
Current limit
Inrush current limit
Inrush current termination
Inrush to operation mode
delay
Current foldback threshold
ILIMIT
IINRUSH
VRTN = 1V
VRTN = 2V
VRTN falling
TDELAY
Foldback deglitch time
Ω
0.48
T2P
T2P output low voltage
T2P output high leakage
current
AUX
VT2P = 48V
AUX high threshold voltage
Respect to VDD
(9)
0.3
V
1
μA
-2.3
V
2
V
μA
AUX threshold hysteresis (9)
AUX leakage current
PG
Respect to VDD
VDD - VAUX = 6V
PG output high voltage
PG floating
5.5
V
Source current capability
PG is logic high, pull down PG
to 0V
30
μA
1000
kΩ
TPD-SD
150
°C
TPD-HYS
20
°C
PG pull-down resistance
PD Thermal Shutdown
Thermal shutdown
temperature (10)
Thermal shutdown
hysteresis (10)
MP8008 Rev. 1.0
1/6/2017
PG is logic low, pull up PG to 1V
-0.6
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VDD, CLASS, DET, T2P, and RTN voltages are referred to VSS. All other pin voltages are
referred to GND. GND and RTN are shorted together. VDD - VSS = 48V, VSS = 0V, VIN = 18V, RDET
= 24.9kΩ, RCLASS = 28.7Ω. TJ = -40°C to +125°C. Typical values are tested at TJ = 25°C, unless
otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
3.9
4.17
350
4.44
V
mV
10.6
11.8
12.8
V
1
μA
0.6
mA
Flyback Controller Section
Controller Input Supply Management
VCC UVLO threshold
VCC UVLO hysteresis
VCC regulation voltage
VCC-UVLO Rising edge
VCC-HYS
VCC
Shutdown current
IS
Quiescent current
IQ
Load = 0mA to 10mA
VEN = 0V, test supply from VIN
to GND
VFB = 1.35V, test supply from
VIN to GND
0.4
Gate Driving Signal (GATE)
Gate driver impedance
(sourcing)
Gate driver impedance
(sinking)
Error Amplifier (EA)
Error amplifier
transconductance
Maximum amplifier output
current
GEA
IGATE = -20mA
4.1
Ω
IGATE = 20mA
2
Ω
0.56
mA/V
75
μA
2.4
V
214
ns
VFB is ±50mV from FB
threshold, VCOMP = 1.5V
Sourcing and sinking
ISENSE = 0V, VFB = 1V
COMP high voltage
ISENSE = 1V, floating COMP
Current Sense (ISENSE)
Current comparator
leading edge blanking (11)
ISENSE limit
SCP limit (10)
Current sense amplifier
gain
ISENSE bias current
PWM
TLEB
VLIMIT
VSCP
ISENSE
VCOMP (skipping mode) (10)
Switching frequency
FSW
Minimum on time
Maximum duty cycle
TON
DMAX
MP8008 Rev. 1.0
1/6/2017
TJ = 25°C
163
185
350
∆VCOMP/∆VISENSE
2.7
TJ = 25°C
0.01
Pulse skipping mode operation
threshold, VCOMP
RT = 6.81kΩ
RT = 80.6kΩ
308
25
RT = 6.81kΩ
93
206
V/V
0.15
0.95
337
30
214
95
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mV
mV
μA
V
363
35
400
kHz
kHz
ns
%
6
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VDD, CLASS, DET, T2P and RTN voltages are referred to VSS. All other pin voltages are referred
to GND. GND and RTN are shorted together. VDD - VSS = 48V, VSS = 0V, VIN = 18V, RDET =
24.9kΩ, RCLASS = 28.7Ω. TJ = -40°C to +125°C. Typical values are tested at TJ = 25°C, unless
otherwise noted.
Parameter
Soft Start (SS)
Symbol Condition
Min
Typ
Max
Units
(12)
Charge current
ISS
Discharge current during
protection
Overload detection
discharge current
Charged threshold voltage
Overload shutdown
threshold voltage
Protection reset threshold
voltage
Voltage Feedback Management
Mode detection voltage (10)
Mode detection current (10)
Mode detection time (10)
FB reference voltage
VFB
FB bias current
OVP reference level
COMP pull-up resistor
COMP pull-up voltage (10)
Enable Control (EN/SYNC)
IFB
VOVP
Enable rising threshold
Enable hysteresis
Enable turn-off delay
Enable input current
Thermal Protection
Thermal shutdown (10)
Thermal hysteresis (10)
TJ = 25°C
TJ = -40°C to 125°C
VFB = 1.237V, TJ = 25°C
VEN-RISING TJ = 25°C
VEN-HYS
TTD-OFF
IEN
VEN = 3V
TSD
TSD-HYS
1.222
1.211
1.391
1.463
54
μA
1.66
μA
17.8
μA
3.65
V
3.27
V
0.2
V
185
55
50
mV
μA
μs
1.237
1.237
0.01
1.438
14.4
3.6
1.252
1.258
0.15
1.479
V
V
μA
V
kΩ
V
1.628
540
20
2.5
1.793
V
mV
μs
μA
160
20
5
°C
°C
NOTES:
9) If VDD - AUX > 2.3V, the IC enables the adapter input. If VDD - AUX < 0.6V, the IC enables the PSE input. Refer to the Wall Power
Adapter Detection and Operation section on page 18 for AUX settings.
10) Guaranteed by characterization, not tested in production.
11) Same as minimum on time.
12) Refer to the Soft Start section on page 20 for the detailed functions of the discharge current and threshold voltage.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL CHARACTERISTICS
VDD - VSS = 48V, VIN = 18V, TA = 25°C, unless otherwise noted.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VDD - VSS = 48V, VIN = 18V, TA = 25°C, unless otherwise noted.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VDD - VSS = 48V, VIN = 18V, TA = 25°C, unless otherwise noted.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VDD - VSS = 48V, VOUT = 12V, IOUT = 2.1A, TA = 25°C, unless otherwise noted.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD - VSS = 48V, VOUT = 12V, IOUT = 2.1A, TA = 25°C, unless otherwise noted.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD - VSS = 48V, VOUT = 12V, IOUT = 2.1A, TA = 25°C, unless otherwise noted.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
PIN FUNCTIONS
PIN#
Name
1
AUX
2
3
DET
VDD
4, 14, 15, 16,
17, 22, 28
NC
5
PG
6
GATE
7
VCC
8
9
10
11
12
13
18
19
20, 21
23, 24
25
26
27
MP8008 Rev. 1.0
1/6/2017
VIN
Description
Auxiliary power input detector. Use AUX for auxiliary power applications. Drive
VDD - AUX above 2.3V to disable hot-swap MOSFET and CLASS functions and
force T2P and PG active.
Detection. Connect a 24.9kΩ resistor between VDD and DET for PoE detection.
Positive power supply terminal from PoE input power rail.
Not connected internally. Connect NC to GND during layout.
PD supply power good indicator. PG is pulled up by an internal current source
when the PD output cap is fully charged. Connect PG to EN/SYNC for flyback
automatic start-up.
Gate driving signal. GATE drives the external N-channel power MOSFET.
Flyback controller for internal 12V regulator out pin. VCC is powered through
an internal LDO from VIN. Connect a capacitor between VCC and GND.
Flyback controller input supply. Connect a bypass capacitor from VIN to GND.
Power ground. GND is gate driver return pin.
Switching frequency set. Connect a resistor from RT to GND to set the switching
RT
frequency (30kHz ~ 400kHz).
Feedback for isolated flyback. COMP is the error amplifier output pin for nonCOMP
isolated solutions.
OVP monitor for isolated flyback. FB is the feedback and OVP monitor pin for
FB
non-isolated solutions. Connect FB to GND if it is not used in isolated flyback.
On/off control input. Connect EN/SYNC to GND internally with a 1MΩ resistor.
EN/SYNC Apply an external clock higher than the RT set frequency to EN/SYNC to
synchronize the switching frequency.
Soft start. Connect one capacitor between SS and GND to control the COMP
SS
voltage rising. SS determines both the soft-start time and hiccup protection delay.
Current sense and application mode (isolated/non-isolated) setting. During
start-up, ISENSE outputs one current signal and senses the voltage for isolated or
ISENSE non-isolated mode setting detection. During normal operation, ISENSE senses the
voltage across the sense resistor for current mode control, as well as cycle-bycycle current limit, overload, and short-circuit protection.
Drain of PD hot-swap MOSFET. Connect GND and the flyback power return to
RTN
RTN.
Negative power supply terminal from PoE input power rail.
VSS
Factory use only. FTY must be connected to VSS in application.
FTY
Classification. Connect a resistor from CLASS to VSS to program the
CLASS
classification current.
Type-2 PSE indicator. T2P is an open-drain output. T2P pulled low to VSS
T2P
indicates the presence of a Type-2 PSE or the presence of a wall adapter.
GND
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14
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
BLOCK DIAGRAM
VDD
AUX
Detection 2.7V - 10.1V
DET
Inrush and Current Limit
T2P
Start-Up Delay Control
CLASS
VSS
Classification 14.5V – 20.5V
Control Logic and
Gate Driver
0/30μA
Mark Event 6.9V – 10.1V
PG
5.5V
VSS
Current /Voltage Sense
VIN
RTN
EN/SYNC
Enable Control
VCC
Regulator
UVLO
Clock
Oscillator and Slope
Compensation
RT
Slope Comp
Burst mode
3.6V
MODE
PWM
Logic
+
PWM
Comparator
R
0.7V
COMP
GATE
Driver
OL/OV/SC
Protection
OCP
GND
3R
MODE
Detection
7R
3.65V
Current Sense
Amplifier
54µA
ISENSE
+
Gain
Soft Start
-
SS
OCP
Protection
OLP Timer
1.66µA
+
50µs
timer
-
17.8µA
EA Out
1.237V
SCP
+
EA
FB
0.185V
+
-
0.35V
R
Q
-
Error Amplifier
3.27V
+
OLP
-
+
OL/OV/SC
Protection
OVP
OVP
1.438V
-
0.2V
+
Restart
S
-
Figure 1: Functional Block Diagram
MP8008 Rev. 1.0
1/6/2017
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15
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
The MP8008 is one integrated PoE solution
with IEEE 802.3af/at PD interface and a peakcurrent-mode flyback controller. Along with the
PSE, the MP8008 operates as a safety device
to supply voltage only when the power sourcing
equipment recognizes a unique and tightly
specified resistance at the end of an unknown
length of Ethernet cable. Once it is powered
from the PSE, the MP8008 regulates the output
voltage based on the application circuit setting.
Figure 2 shows the typical PD interface power
operation sequence.
OPERATION
Compared with IEEE802.3af, the IEE802.3at
standard establishes a higher power allocation
for Power over Ethernet (PoE) while
maintaining backward compatibility with existing
IEEE 802.3af systems. Power sourcing
equipment (PSE) and power devices (PD) are
distinguished as Type-1 (compliant with IEEE
802.3af power levels) or Type-2 (compliant with
IEEE 802.3at power levels). The IEEE
802.3af/at standard establishes a method of
communication between PD and PSE with
detection, classification, and mark events.
Voltage
57V
42.5V
37V
Class Event 2
On
Range
Classification
Range
20.5V
37-57V (af)
Class Event 1
14.520.5V
IEEE 802.3af
Start-Up
IEEE 802.3at
Start-Up
14.5V
2.7-10.1V
10.1V
Signature
Range
6.9V
V2
42.5-57V
(at)
Mark
Range
6.9-10.1V
V1
Turn On
Mark Event
2.7V
Reset
Detection
Classification
Intermediate Idle
ON
Time
Figure 2: PD Interface Operation Description
Detection (DET)
RDET connected between DET and VDD is
presented as a load to the PSE in detection
mode, where the PSE applies two “safe”
voltages between 2.7V and 10.1V while
measuring the change in current drawn to
determine the load resistance. A 24.9kΩ (±1%)
resistor
between
VDD
and
DET
is
recommended to present one correct signature,
and the valid signature resistance seen from
the power interface (PI) is between 23.7kΩ and
26.3kΩ.
The detection resistance seen from the PI is the
result of the input bridge resistance in series
with VDD loading. The input bridge resistance
is partially cancelled by the MP8008’s effective
leakage resistance during detection.
MP8008 Rev. 1.0
1/6/2017
Classification (CLASS)
The classification mode can specify the
expected load range of the device under power
to the PSE so that the PSE can distribute power
intelligently to as many loads as possible within
its
maximum
current
capability.
The
classification mode is active between 14.5V and
20.5V. The MP8008 presents a current in
classification mode (see Table 1).
Table 1: CLASS Resistor Selection
Class
0
1
2
3
4
Max Input
Power to PD
(W)
12.95
3.84
6.49
12.95
25.5
Classification
Current (mA)
RCLASS
(Ω)
2
10.55
18.7
28.15
40.4
578
110
62
41.2
28.7
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16
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
2-Event Classification
The MP8008 can be used as a Type-1 PD class
0-3 (as shown in Table 1). It also distinguishes
class 4 with 2-event classification.
In 2-event classification, the Type-2 PSE reads
the power classification twice. Figure 2 shows
an example of a 2-event classification. The first
classification event occurs when the PSE
presents a voltage between 14.5V to 20.5V to
the MP8008, and the MP8008 presents a class4 load current. The PSE then drops the input
voltage into the mark voltage range of 6.9V to
10.1V, signaling the first mark event. The
MP8008 presents a load current between
0.5mA to 2mA in the mark event voltage range.
If VDD - VSS drops below the falling UVLO, the
hot-swap MOSFET is disabled.
If the output current overloads on the internal
pass MOSFET, the current limit works, and
VRTN - VSS rises. If VRTN rises above 10V for
longer than 1ms or rises above 20V, the current
limit reverts to the inrush value, and PG drops
low at the same time.
Figure 3 shows the current limit and the PG and
T2P work logic during start-up from the PSE
power supply.
PSE Power On
VDD > UVLO_R?
The PSE repeats this sequence, signaling the
second classification and second mark event.
The PSE then applies power to the MP8008,
which charges up the DC/DC input capacitor
(CBULK, C1 on the schematic on page 1) with a
controlled inrush current. When CBULK is fully
charged, T2P presents an active-low signal with
respect to VSS after TDELAY. The T2P output
becomes inactive when the MP8008 input
voltage VDD falls below UVLO (see Figure 3).
PD Interface UVLO and Current Limit
When PD is powered by PSE, and VDD is
higher than the turn-on threshold, the hot-swap
switch begins passing a limited current (IINRUSH)
to charge the downstream DC/DC converter’s
input capacitor (CBULK). The start-up charging
current is around 120mA.
If RTN drops below 1.2V, the hot-swap current
limit changes to 840mA. After TDELAY from
UVLO begins, the MP8008 asserts the PG
signal and switches from start-up mode to
running mode. If PG is connected to EN/SYNC,
the PG signal rises high only after the hot-swap
switch turns on completely, so PG enables the
flyback through EN/SYNC.
MP8008 Rev. 1.0
1/6/2017
No
Yes
120mA Inrush
100ms Timer
VRTN-Vss < 1.2V?
Timer-out?
Yes
Current Limit
change to 840mA
Yes
No
Both are OK
PG rises to high
No
VRTN>10V for 1ms
Or VRTN>20V?
Yes
PG drops
T2P acts based on
PSE type
No
VDD < UVLO_F?
Yes
T2P resets
PSE Power Off
Figure 3: Start-Up Sequence
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17
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
Wall
Power
Adapter
Detection
and
Operation
The MP8008 uses wall power adapter detection
for applications where an auxiliary power
source, such as a wall adapter, is used to
power the device (see Figure 4). Once the input
voltage (VDD - VSS) exceeds about 11.5V, the
MP8008 enables wall adapter detection. The
wall power adapter detection resistor divider is
connected from VDD to the negative terminal of
the adapter, and DADP3 is added for a more
accurate hysteresis. There is a -2.3V reference
voltage from AUX to VDD for adapter detection.
The adapter is detected when the AUX voltage
triggers, shown in Equation (1):
VDD VAUX (VADP VDADP3 )
RADPUP
2.3V (1)
RADPUP RADPDOWN
Where VADP is the adapter voltage, VDADP3 is the
Zener voltage, and RADPUP and RADPDOWN are the
AUX divider resistors from the adapter power.
If the applied adapter voltage is much higher
than the design adapter voltage, the VDD VAUX voltage is high. If the applied voltage
between VSS and AUX is higher than 6.5V, the
MP8008’s inner circuit clamps the VDD - VAUX
voltage at 6.5V. A current then flows out
through AUX. The current should be limited
below
3mA
by
an
external
resistor
(RADPUP/RADPDOWN or RT resistor from the resistor
divider to AUX).
To make the MP8008 work stably with adapter
power, one Schottky diode (DAPD1, D4 on the
schematic on page 1) is required between the
negative terminal of the adapter and VSS. DAPD2
(D5 on the schematic on page 1) is used to
block reverse current between the adapter and
PSE power source. When a wall adapter is
detected, the internal MOSFET between RTN
and VSS turns off, classification current is
disabled, and T2P becomes active. The PG
signal is active when the adapter power is
detected, so that it can enable the downstream
DC/DC converter, even if the input hot-swap
MOSFET is disabled.
MP8008 Rev. 1.0
1/6/2017
MP8008
To DCDC
VDD
2.3V
From PSE
Shut down Hot-swap
Shut down Classification
Pull up PG
+
AUX
-
VSS
Adaptor
RTN
R ADPUP
R ADPDOWN
DADP3
DADP1
DADP2
Figure 4: Adapter Power Detection
Power Good Indicator (PG)
The PG signal is driven by the internal current
source. After TDELAY from UVLO starts, and RTN
drops to 1.2V or a wall power adapter is
detected, the PG signal is pulled high to
indicate the power condition. Figure 3 shows
the PG logic when powered from PSE. PG is
high if the adapter is detected in any condition.
Connect PG to EN/SYNC to set automatic
start-up mode after power is applied.
Flyback Controller Operation
The MP8008 integrates a flyback controller,
which uses a programmable frequency and
peak-current-mode architecture to regulate the
output voltage.
At the beginning of each cycle, the external Nchannel MOSFET is turned on, forcing the
current in the transformer to increase. The
current through the MOSFET can be sensed.
When the sum voltage of the amplified ISENSE
signal and slope signal rises above the voltage
set by COMP, the external MOSFET is turned
off. The transformer current flows from the
primary side to the secondary side, and then
flows to the output capacitor through the output
Schottky diode. The transformer current is
controlled by the COMP voltage (VCOMP), which
itself is controlled by the output voltage.
Therefore, the output voltage controls the
transformer current to satisfy the load. This
current mode architecture improves transient
response and control loop stability.
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18
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
Pulse-Skipping Mode
In light-load condition, the MP8008 goes into
pulse-skipping mode to improve light-load
efficiency. The pulse-skipping decision is based
on its internal COMP voltage. If COMP is lower
than the internal sleep threshold with a typical
0.95V valule, a pause command is generated to
block the turn-on clock pulse, so the power
MOSFET is turned off immediately, saving gate
driving and switching losses. This pause
command also puts the entire chip into sleep
mode, which consumes very low quiescent
current to further improve light-load efficiency.
The gate driver output remains low until VCOMP
is higher than the sleep threshold, and then the
pause signal is reset so the chip resumes
normal PWM operation.
Internal VCC Regulator
VIN works with a 7V ~ 35V supply voltage. An
internal regulator is applied to regulate the
power at VCC to supply the internal circuitry of
the controller and the gate driver. The regulator
has a nominal output voltage of 12V at VCC
and must be bypassed with a capacitor no less
than 1μF.
When EN/SYNC is high, the capacitor at VCC
is charged through VIN. VCC has its own UVLO
protection. This UVLO’s rising threshold is
4.17V with a hysteresis of 350mV.
Feedback Loop Setting
The MP8008 can feed back the output signal
through either FB or COMP by a different
setting on ISENSE.
For isolated flyback, the feedback signal from
the optocoupler is amplified by the secondary
circuitry. Connect the signal to COMP directly to
make loop compensation easier by eliminating
the primary-side amplifier. For non-isolated
flyback, the MP8008 integrates one error
amplifier, which can amplify the output error
signal from FB. COMP needs one R-C network
for compensation.
The different feedback loops can be set by
different ISENSE connections. When the part is
enabled, ISENSE outputs a 50µs current pulse
with a typical 55µA value (see Figure 5). If the
reflected voltage on ISENSE is higher than
185mV, the MP8008 disables the internal error
amplifier between FB and COMP and pulls
COMP up to a 3.6V source with a 14.4kΩ
resistor. The feedback signal can be connected
to COMP directly. If the detection voltage is
lower than 185mV, the MP8008 enables the
internal error amplifier and turns off the pull-up
resistor. Then COMP is just one output pin of
the error amplifier, and the feedback signal
should be connected to FB.
VIN
When the voltage at VCC crosses the VCC
UVLO, flyback is enabled, and all internal
circuitry is powered by VCC. As the capacitor is
charged, VCC increases until it reaches the
12V regulated voltage if VIN is high enough.
When VIN is below 12V, VCC is lower than VIN
due to an LDO drop. For normal operation, VIN
voltage should be higher than 7V. If VCC and
VIN are connected together, the MP8008’s
flyback converter can start up, even if VIN is 5V,
but the max VCC value should not be higher
than 13V. If both VIN and VCC are powered by
an external source, VCC cannot be higher than
VIN since there is one body diode from VCC to
VIN.
MP8008 Rev. 1.0
1/6/2017
55µA
50µs
Start up
GATE
+
High / Low
I SENSE
-
R MODE
0.185V
R SENSE
V SENSE
= 55µA x(R MODE+R SENSE)
Figure 5: Feedback Mode Setting
Generally, it is recommended to place one 5kΩ
~ 10kΩ resistor between ISENSE and the
current sense resistor for feedback mode
through COMP, and connect ISENSE to the
current sense resistor directly for feedback
mode through FB.
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19
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
Soft Start (SS)
The MP8008 uses one external capacitor on SS
to control VCOMP rising for a soft start. When the
chip starts up, the capacitor on SS is charged
by a 54µA current source at a slow pace set by
the capacitance. When the SS voltage is lower
than the external VCOMP, SS overrides the
COMP signal, so the PWM comparator uses SS
instead of COMP as the PWM turn-off
reference. When SS is higher than VCOMP,
COMP regains control, and the soft start
finishes. Soft start can reduce voltage stresses
and surge currents during start-up and prevent
the converter output voltage from overshooting
during start-up. Soft start occurs during the
start-up time and protection recovery time after
OLP, SCP, and OVP. During normal condition,
the SS voltage is clamped at 3.65V.
Programmable Oscillator
The MP8008 oscillating frequency is set by an
external resistor from RT to ground. The value
of RT can be estimated with Equation (2):
RT
2.35 103
fSW
(2)
Where RT is in kΩ, and fSW is in kHz.
The frequency setting resistor value should not
be too large when considering noise immunity.
It is recommended to set the frequency within
30kHz to 400kHz.
Enable/SYNC Control
EN/SYNC is a digital control pin that turns the
MP8008 flyback controller on and off. Drive
EN/SYNC high to turn on the controller; drive
ENSYNC low to turn off the controller. An
internal 1MΩ resistor from EN/SYNC to GND
allows EN/SYNC to be floated to shut down the
chip.
For external clock synchronization, connect a
clock with a frequency higher than RT to set the
frequency between 80kHz to 400kHz. The
internal clock rising edge synchronizes with the
external clock rising edge. Select an external
clock pulse signal with a low level width less
than 10μs; otherwise, the MP8008 may treat
this function as an EN/SYNC power off.
MP8008 Rev. 1.0
1/6/2017
EN/SYNC and PG should be connected
together so that the flyback controller starts up
automatically once the PD enters an operation
mode. If EN/SYNC is pulled high by an external
power, then the EN/SYNC pull-up current
should be limited to less than 0.4mA.
Current Sense and Over-Current Protection
The current through the external MOSFET can
be sensed through a sensing resistor used in
series with the source terminal of the MOSFET.
The sensed voltage on ISENSE is amplified
and fed to the high-speed current comparator
for current-mode control purposes. The current
comparator takes this sensed voltage (pulseslope compensation) as one of its inputs and
compares the power switch current with VCOMP.
When the amplified current signal is higher than
VCOMP, the comparator output is low and turns
off the power MOSFET.
If the voltage on ISENSE exceeds the currentlimit threshold voltage with a typical value of
185mV, the PWM controller turns off the GATE
output for that cycle until the internal oscillator
starts the next cycle, and the current is sensed
again. The MP8008 limits the current of the
MOSFET cycle-by-cycle.
Overload Protection (OLP)
The peak current is limited cycle-by-cycle. If the
load continues increasing after triggering overcurrent protection (OCP), the output voltage
decreases, and the peak current triggers OCP
during every cycle. The MP8008 sets overload
detection by monitoring the ISENSE voltage
continuously.
Once the SS voltage is charged to 3.65V after
start-up, OLP is enabled. If an OCP signal is
detected, the soft-start charging current is
disabled, and an over-current discharge source
is enabled. The SS voltage drops with the rate
of 17.8µA. At the same time, a 50µs one-shot
timer is activated and remains active for 50µs
after the OCP condition stops. The 17.8µA
discharge source cannot be turned off until the
one-shot timer becomes inactive. If the OCP
condition is removed before at least 50µs prior
to the SS capacitor discharging to 3.27V, the
MP8008 resumes normal working condition,
and the SS capacitor is re-charged to 3.65V
with a 54µA rate.
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20
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
If the SS capacitor is discharged to 3.27V, the
MP8008 registers this as an overload condition
and turns off the gate output until the next
restart cycle. At the same time, the 17.8µA
discharge current is disabled, and the 1.66µA
overload discharge source is enabled. After the
SS voltage is discharged to 0.2V, the PWM
controller starts up again with a new soft-start
cycle. This is called hiccup mode protection.
The OLP detection function is disabled after the
SS voltage is discharged below 3.27V and is reenabled after the SS voltage is recharged to
3.65V. OLP only occurs after the soft-start is
completed.
Short-Circuit Protection (SCP)
When the output is shorted to ground, the
MP8008 works in OCP mode, and the current is
limited cycle-by-cycle. The MP8008 may run
into OLP.
If the peak current cannot be limited by the
185mV ISENSE voltage every cycle due to the
leading edge blanking (LEB) time, the current
may run out of control, and the transformer may
run into saturation. If the voltage on ISENSE
reaches 0.35V, the MP8008 pulls GATE down
and run into hiccup mode immediately by
discharging the SS capacitor with a 1.66µA
current. The MP8008 restarts if the SS voltage
is discharged to 0.2V. If a short condition is still
detected, the MP8008 runs into SCP again
immediately without having to wait for SS to
charge completely. This prevents damage
during the soft start-up period.
Once the short circuit is removed, the output
voltage recovers only after the next restart cycle.
MP8008 Rev. 1.0
1/6/2017
Over-Voltage Protection (OVP)
For isolated flyback application, the positive
plateau of the auxiliary winding voltage is
proportional to the output voltage. The MP8008
features over-voltage protection (OVP) by using
the auxiliary winding voltage instead of
monitoring the output voltage directly. The
auxiliary voltage can be monitored by FB
through a resistor divider. Once the voltage is
higher than the OVP reference voltage, the
MP8008 turns off GATE and discharges the SS
voltage with 1.66µA current until the SS voltage
is lower than 0.2V. The MP8008 then enters a
new restart cycle.
If OVP is still detected, the MP8008 runs into
OVP again without waiting for SS to charge
completely. To prevent a mistrigger due to the
oscillation of the leakage inductance and the
parasitic capacitance, OVP sampling has an
OVP blanking time (typically 500ns). For some
oscillation conditions, one external filter is
necessary to work with the 500ns LEB time.
For non-isolated solutions, the DC output
voltage is applied to FB and can detect the
OVP condition easily.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from running away thermally. The
MP8008 has a separated temperature monitor
circuit for PD and flyback controllers. The
flyback’s thermal protection does not affect the
PD interface, but the PD temperature protection
turns off both the PD and flyback controller if
EN/SYNC is connected to the PG signal. When
the temperature is below its recovery threshold,
thermal shutdown is removed, and the MP8008
is enabled.
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21
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
APPLICATION INFORMATION
Detection Resistor
In detection mode, a resistor connected
between DET and VDD is needed as a load to
the PSE. The resistance is calculated as ∆V/∆I,
with an acceptable range of 23.7kΩ to 26.3kΩ.
Use a typical value of 24.9kΩ as the detection
resistor.
Classification Resistor
To distribute power to as many loads as
possible from PSE, a resistor between CLASS
and VSS is used to classify the PD power level,
which draws a fixed current set by the
classification resistor. The supplied power to
PD set by the classification resistor is shown in
Table 1. The typical voltage on CLASS is 1.16V
in the classification range and produces about
47mW of power loss on the class resistor in a
class-4 condition.
Protection TVS
To limit the input transient voltage within the
absolute maximum rating, a TVS across the
rectified voltage (VDD - VSS) must be used. A
SMAJ58A TVS or equivalent is recommended
for general indoor applications. Outdoor
transient levels or special applications require
additional protection.
PD Input Capacitor
An input bypass capacitor 0.05μF to 0.12μF
from VDD to VSS is needed for IEEE 802.3at/af
standard specifications. Typically, a 0.1μF,
100V, ceramic capacitor is used.
Wall Power Adapter Detection Circuit
When an auxiliary power source, such as a wall
power adapter, is used to power the device, the
divider resistors RADPUP, RADPDOWN, and DADP3
must be chosen to satisfy Equation (1) for
correct wall power adapter detection (see
Figure 6).
RADPUP with a typical 3kΩ value is
recommended to balance the power loss and
DADP1 and DADP2 leakage current discharge.
MP8008 Rev. 1.0
1/6/2017
VADP
VDD
Q PG
RPG2
R ADPUP
RPG1
AUX
PG
RPG3
R ADPDOWN
VSS
RTN
DADP3
DADP1
Adaptor GND
DADP2
Figure 6: Wall Adapter Detection Circuit
One small Schottky diode with a 100V rating,
such as BAT46W, is usually recommended for
DADP1. The voltage rating of DADP2 must also be
100V or higher, while the current rating must be
higher than the load current. A low-voltage drop
Schottky diode, such as STPS2H100, is
recommended to reduce conduction power
loss.
The MP8008 enables wall adapter detection at
VDD = 11.5V. If one adapter power with a lower
voltage rating (such as 10V) is used to power
the converter, one external PG pull-up resistor
is necessary to enable the downstream DC/DC
converter. Refer to Figure 6 and the following
Power Good (PG) section for more detail.
Power Good (PG) Indicator Signal
The MP8008 integrates one power good (PG)
indicator. PG is pulled high through an internal
pull-up current source when the logic is high, so
PG can connect with EN/SYNC to enable the
flyback portion without any external pull-up
circuit. PG disables the internal pull-up current,
and PG is pulled low through an internal
resistor when PG is in a logic low state.
If one adapter power lower than 11.5V is
connected to supply the converter, the PG
function cannot work with such a low input. An
external PG pull-up circuit is recommended
(see Figure 6). Typically, QPG needs a VCE
voltage higher than 100V (such as BSS63LT1).
Choose RPG2 = 7.5kΩ and RPG3 = 100kΩ for a
12V adapter with some margin of adapter
regulation. Choose RPG1 = 100kΩ to limit the
PG sink current below 0.6mA when VDD is
high.
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22
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
T2P Indicator Connection
T2P is an active-low, open-drain output that
indicates the presence of a Type-2 PSE or the
presence of a wall adapter. An optocoupler is
usually used as the interface from T2P to the
circuitry on the output of the converter (see
Figure 7). A high-gain optocoupler and a highimpedance receiver are recommended (i.e.:
CMOS).
VOUT of DCDC
VDD
IT2P
RT2P
IT2P-OUT
RT2P-O
Type 2 inductor
low active
T2P
Figure 7: T2P Indicator Circuit
Considering the T2P sinking current (typically
2mA), the T2P output-low voltage (0.1V), and
the diode forward voltage drop, choose RT2P =
23.7kΩ to match the typical 48V input. Suppose
VOUT of the DC/DC part is 12V, choose RT2P-O =
20kΩ based on the CRT, even if it varies with
temperature, LED bias current, and aging.
If just using an LED from VDD to T2P to
indicate if Type-2 PSE is available, RT2P’s
resistance can be higher to match the LED’s
max current and reduce power loss.
Flyback Controller Power Supply Setting
VIN supports up to 35V of input voltage. For a
typical PoE application, one external voltage
regulator circuit is needed to clamp the 48V
PoE input. After the flyback starts, VIN can be
powered from the transformer auxiliary winding
to save external high-voltage regulator power
loss.
Output Voltage Setting
When the MP8008 works in isolated flyback
mode, the output voltage cannot be set by FB.
An additional external shunt regulator (i.e.:
TL431) can be used to set VOUT. Supposing that
this regulator’s reference voltage is 2.5V, and
the expected output voltage is 12V, then the
MP8008 Rev. 1.0
1/6/2017
upper and lower divider resistor ratio is 3.8, the
lower resistor is 49.9kΩ, and the upper resistor
is 191kΩ. Typically, the upper resistor should
lower than 500kΩ to avoid noise injection.
Then TL431 generates an amplified signal
which transfers to the MP8008 through an
optocoupler, such as PC817. Then VOUT is
regulated based on the feedback signal.
Selecting the Soft-Start Capacitor
The MP8008 ramps the external capacitor
voltage on SS to control VCOMP, which
determines the transformer primary-side peak
current, resulting in a lower inrush current. The
SS voltage can be calculated by Equation (3):
Vss
54A
Tss
Css
(3)
More importantly, SS acts as a hiccup timer
when OLP, SCP, or OVP occurs. Once
protection occurs, a 1.66µA current discharges
the SS capacitor for hiccup protection. Normally,
a 0.22µF SS capacitor is sufficient for most
applications.
Selecting the Input Capacitor
A DC/DC controller input capacitor is required
to supply AC ripple current to the transformer
while limiting noise at the input source. This
controller acts as a voltage bulk between the
PD and DC/DC converter. A large capacitance
leads to longer PD charge time and higher cost;
a lower capacitance leads to higher input
voltage ripple and higher input current ripple.
Typically, a 47µF ~ 100µF E-cap is
recommended in parallel with a high-quality
ceramic capacitor. The input voltage ripple can
be estimated with Equation (4):
VIN IIN
VIN
FSW CIN (N VOUT VIN )
(4)
Where ∆VIN is the input voltage ripple, IIN is the
input current, FSW is switching frequency, CIN is
the input capacitance, and N is the transformer
ratio.
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage and also affects system stability. For
best result, use low ESR capacitors to minimize
the output voltage ripple. Electrolytic capacitors
are also sufficient, but must be used in parallel
with a high-quality ceramic capacitor to filter the
high-frequency noise.
If the voltage ripple is too high, a π filter is
needed. Choose the inductor to be between
0.1µH ~ 0.47µH to achieve good VOUT ripple
and system stability.
Selecting Transformer and ISENSE Resistor
A transformer is important in a flyback converter
since it determines the duty cycle, peak current,
efficiency, MOSFET, output diode rating, and
so on. A good transformer should consider the
winding
ratio,
primary-side
inductance,
saturation current, leakage inductance, current
rating, and core selection.
The transformer winding ratio is a very
important since it determines the duty cycle.
Calculate the duty with Equation (5):
D
NVOUT
NVOUT VIN
The energy stored in the leakage inductance
cannot couple to the secondary side, causing a
high spike when the MOSFET turns off. This
decreases efficiency and increases MOSFET
stress. Normally, the transformer leakage
inductance can be controlled below 3% of the
transformer inductance.
The current rating counts the max RMS current,
which allows flow through each winding. The
current density should be controlled; otherwise,
it can cause a high resistive power loss.
After the transformer is chosen, determine the
peak current. To avoid reaching the current limit,
the voltage across the sensing resistor (RSENSE)
should be less than 80% of the worst-case
current limit voltage (185mV). Calculate RSENSE
with Equation (7):
RSENSE
(5)
Where N is the transformer winding ratio, and D
is the duty cycle. Typically, a max duty cycle of
about 45% is recommended for most
applications.
The primary-side inductance affects the input
current ripple ratio factor. A high inductance
results in a large transformer size and high cost;
a low inductance results in high switching peak
current and RMS current, which causes a
decrease in efficiency. Choose a primary-side
inductance to make the current ripple ratio
factor around 30% ~ 50%. Estimate the
primary-side inductance with Equation (6):
VIN D2
LP
2 n IIN FSW
The transformer should have a high saturation
current to support the switching peak current;
otherwise,
the
transformer
inductance
decreases sharply. The ISENSE resistor can be
used to limit the switching peak current.
0.8 0.185
IPEAK
(7)
RCD Snubber
The transformer leakage inductance causes
spikes and excessive ringing on the MOSFET
drain voltage waveform, and the RCD snubber
circuit limits the MOSFET voltage spike (see
Figure 8).
T1
C8
R13
Np
D2
MP8008
Ns
AGND
Q1
GATE
PGND
(6)
Where n is the current ripple ratio, IIN is the
input current, and LP is the primary inductance.
Calculate LP based on the minimum input
voltage condition.
Figure 8: RCD Snubber
The power dissipation in the snubber circuit can
be estimated with Equation (8):
PSN
1
LK IPEAK 2 FSW
2
(8)
Where LK is the leakage inductance, and IPEAK is
the peak switching current.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
Since R13 consumes the leakage inductance
power loss, R13 is selected with Equation (9):
R13
VSN2
PSN
(9)
Where VSN is the expected snubber voltage on
C8.
The snubber capacitor (C8) can be designed to
achieve an appropriate voltage ripple on the
snubber using Equation (10):
VSN
VSN
R13 C8 FSW
(10)
Generally, a 15% ripple is acceptable.
Selecting the Power MOSFET
The MP8008 is capable of driving a wide variety
of N-channel power MOSFETS. The critical
parameters of selecting a MOSFET are
maximum drain to source voltage (VDS(MAX)),
maximum current (ID(MAX)), on resistance
(RDS(ON)), gate source charge (QGS) and gate
drain charge (QGD), total gate charge (QG), and
turn-on threshold (VTH).
Ideally, the off-state voltage across
MOSFET is calculated with Equation (11):
VMOSFET VIN N VOUT
the
The on resistance of the MOSFET determines
the conduction loss and should therefore be
small.
QG is important for MOSFET selection since it
determines the commutation time. A high QG
leads to high switching loss, while a low QG
may cause fast turn on/off speed, which
determines the spike and kick.
The turn-on threshold voltage (VTH) is also
important. GATE is powered by VCC, so VTH
must be lower than VCC.
Selecting the Output Diode
The flyback output rectifier diode supplies
current to the output capacitor when the primary
side MOSFET is off. Use a Schottky diode to
reduce losses due to the diode forward voltage
and recovery time. The diode should be rated
for a reverse voltage 1.5 times greater than the
value calculated from Equation (12):
VDIODE
(11)
Considering the voltage spike when it turns off,
VDS(MAX) should be greater than 1.5 times the
output voltage.
MP8008 Rev. 1.0
1/6/2017
The maximum current through the power
MOSFET occurs when the input voltage is at its
minimum and the output power is at its
maximum. The current rating of the MOSFET
should be greater than 1.5 times IRMS.
VIN
VOUT
N
(12)
The average current rating must exceed the
maximum expected load current, and the peak
current rating must exceed the output winding
peak current.
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25
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
PCB Layout Guidelines
Efficient layout of the PoE front-end and highfrequency switching power supply is critical for
stable operation. Poor layout may result in
reduced performance, excessive EMI, resistive
loss, and system instability. For best results,
refer to Figure 9 (referenced to schematic on
page 1) and follow the guidelines below.
For the PD interface circuit:
All component placement must follow the power
flow from RJ-45, Ethernet transformer, diode
bridges, TVS to 0.1μF capacitor, and DC/DC
converter input bulk capacitor. The spacing
between VDD and VSS must comply with
safety standards such as IEC60950.
1. Make all leads as short as possible with
wide power traces.
2. Place the PD interface circuit ground planes
referenced to VSS.
3. Place the switching converter ground planes
referenced to RTN/GND.
4. Connect the exposed pad to GND. It cannot
be connected to VSS.
5. Place the AUX divider resistor close to AUX
if adapter power detection is enabled.
6. Place the diode (D4) close to VSS and
RTN.
For the flyback circuit:
1. Keep the input loop between the input
capacitor, transformer, MOSFET, current
sense resistor, and GND plane as short as
possible for minimal noise and ringing.
For more detail information, refer to the flyback
evaluation board datasheet.
Figure 9: Layout Guide
Design Example
Table 2 is a design example following the
application guidelines for the following
specifications.
Table 2: Flyback Design Example
VDD - VSS
RDET
RCLASS
VADAPTER (13)
VOUT
IOUT
37V - 57V (PoE supply)
24.9kΩ
28.7Ω (class 4)
12V
12V
2.1A
The typical application circuit in Figure 10
shows the detailed application schematic and is
the basis for the typical performance
waveforms. Typically, the device is powered by
PSE (VDD - VSS = 48V). For more detailed
device applications, please refer to the related
evaluation board datasheets.
NOTE:
13) When using A 12V adapter, and the load is 2.1A, the board’s
temperature is high. It can be optimized by a larger PCB
layout.
2. Keep the output loop between the rectifier
diode, output capacitor, and transformer as
short as possible.
3. Keep the clamp loop circuit between D6, C8,
and the transformer as small as possible
4. Place the VCC capacitor close to VCC for
the best decoupling.
5. Keep the feedback trace far away from
noise sources such as the drain of the
power FET.
6. Use single-point connection between the
power GND and signal GND.
MP8008 Rev. 1.0
1/6/2017
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MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
TYPICAL APPLICATION CIRCUIT
VDD 37V-57V
R14
7.5kΩ
R3
24.9kΩ
Q3
C3
T2P
VSS
D11
C4
VIN
MP8008
R10 4.99kΩ
R9B
0.082Ω
U2A
PC817B
RT
SS
GND
RTN
VCC
4.7µF
PDS3100
0.22µF
9.31kΩ
D5
C11
R24
2kΩ
PGND
U2B
C9
NS
R21
10k
Ω
SGND
SGND
GND
R12
C7
R19
NC
VOUT
6.8kΩ
0.082Ω
D4
BAT46W
D7
6.8V
220µF0.1µF
R25
10Ω
COMP
R8 C6 C5
C2C C2D
22µF 22µF
Q1
Si7430
R9A
FB
FTY
C2A C2B
SGND SGND
D91N4148
1µF
R20 4.99Ω
ISENSE
VSS
R6
1kΩ
SGND
0.1µH
Np2
PGND
CLASS
AUX
PGND
1N4148
GATE
PG
28.7Ω
SBR8U60P5
12V@2.1A
L1
D1
Np1
200V
EN
R4
R13A R13B
C8
20k 20k
0.1µF
Ω
Ω
D6
PGND
R23
0.47nF 20Ω
Ns
Q4
D2
PGND
R16
100kΩ
C1A C1B C1C
47µF 2.2µF 2.2µF
9.1V
DET
SMAJ58A
0.1µF
D8
NC
R15
100kΩ
R18
1kΩ
R7
100kΩ
R17
NC
VDD
R5
3kΩ D3
12V
Adapter
C10
T1
R22
D10
NC
NC
Q2
TL431
R1
191kΩ
C12
680pF
220pF
R11
0.1µF 49.9kΩ
R2
49.9kΩ
C13
1000p/2000V
PGND
AGND
AGND
PGND
Figure 10: Typical Application Circuit, VDD = 37V - 57V PoE Input or 12V Adapter, VOUT = 12V@2.1A
MP8008 Rev. 1.0
1/6/2017
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27
MP8008 ― IEEE, 802.3af/at POWER DEVICE WITH FLYBACK CONTROLLER
PACKAGE INFORMATION
QFN-28 (4mmx5mm)
2.50
2.80
3.90
4.10
23
28
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
22
1
0.50
BSC
PIN 1 ID
INDEX AREA
3.50
3.80
4.90
5.10
0.18
0.30
8
15
0.35
0.45
TOP VIEW
14
9
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.25 TYP.
0.80
1.00
0.20 REF
0.00
0.05
DETAIL A
SIDE VIEW
3.90
NOTE:
2.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-220, VARIATION VGHD-3.
5) DRAWING IS NOT TO SCALE.
0.70
0.25
0.50
3.70 4.90
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8008 Rev.1.0
1/6/2017
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