MP8030
Fully Integrated, 802.3af/at/bt-Compliant
PoE PD Interface with
High-Efficiency Flyback/Forward Controller
DESCRIPTION
FEATURES
The MP8030 is a fully integrated, IEEE
802.3af/at/bt-compliant, Power over Ethernet
(PoE), powered device (PD) power supply
converter. The device features a PD interface
and a high-efficiency flyback/forward controller.
•
•
The PD interface has all the functions of IEEE
802.3af/at/bt. It also integrates a 100V hot-swap
MOSFET for ≤51W applications and one
GATE1 driver to enhance efficiency for highpower applications (>51W). The GATE2 driver
supports an external, low on resistance Nchannel MOSFET to prevent high power loss
when the device is powered by an adapter.
The flyback/forward controller is specifically
designed for primary-side regulation (PSR)
flyback applications, as well as secondary-side
regulation
(SSR)
active-clamp
forward
applications. It also can be used in an SSR
flyback topology.
The MP8030 features overload protection
(OLP) with hiccup mode, short-circuit protection
(SCP), over-voltage protection (OVP), and
thermal shutdown.
The MP8030 is available
(5mmx6mm) package.
in
a
QFN-32
•
•
•
•
•
•
•
•
Compliant with 802.3af/at/bt Specifications
Internal Hot-Swap MOSFET for ≤51W
Designs
External FET with GATE1 for >51W
Designs
GATE2 N-Channel MOSFET Driver for
Adapter Supply
Supports Automatic Classification
Automatic Maintain Power Signature
Function
Supports Flexible Topologies with DC/DC
Design:
o Primary-Side Regulation (PSR) for
Flyback Applications
o Secondary-Side Regulation (SSR) for
Flyback Applications
o SSR for Active-Clamp Forward
Applications
EMI Reduction with Frequency Dithering
Ethernet Alliance (EA Gen 2) Certified
Available in a QFN-32 (5mmx6mm)
Package
Optimized Performance with
MPS Inductor MPL-AY Series
APPLICATIONS
•
•
•
•
•
•
IEEE 802.3af/at/bt-Compliant Devices
Security Cameras
Video and VoIP Phones
WLAN Access Points
Internet of Things (IoT) Devices
Pico Base Stations
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
MP8030 Rev. 1.0
1/31/2022
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1
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL APPLICATION
From Adapter
L1
C1
Q2
C7
VOUT
R9
Efficiency vs. Load Current
R7
Q5
Q3
EN
AVIN
PG
SRC
SENSE
VDD
U1
MP8030
GATE
R29
Q1
U2A
R1
GND
R22
PAD
MODE
COMP
CS
AUTOCLS
CLSA
GND
R_MPS
ILIM
DUTY
PRI
CLSB
R15
Q4
C4
BT
TYP2
TYP1
R6
T1
VCC
C3
D1
SSR mode, forward, VOUT = 5V
R10
SYNC
R8
From PSE
D2
FB
U3
R2
R4
R5
U2B
EFFICIENCY (%)
AUX
GATE1
VADP
GATE2
C6
C2
C5
95
90
85
80
75
70
65
60
55
50
Vin=41V
Vin=54V
Vin=57V
0
MP8030 Rev. 1.0
1/31/2022
2
4
6
8
10
LOAD CURRENT (A)
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12
14
2
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ORDERING INFORMATION
Part Number*
MP8030GQJ
Package
QFN-32 (5mmx6mm)
Top Marking
See Below
MSL Rating
2
* For Tape & Reel, add suffix -Z (e.g. MP8030GQJ-Z).
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP8030: Part number
LLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-32 (5mmx6mm)
MP8030 Rev. 1.0
1/31/2022
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3
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
PIN FUNCTIONS
Pin #
1
2
3
4
5
6
7
8
9
10
11, 29
12
13
14
15
16
17
Name
Description
Automatically maintains power signature load resistor connection. The R_MPS pin
generates a 24V output pulse when the maintain power signature function is triggered.
PD internal hot-swap MOSFET current limit configuration. See the Hot-Swap
ILIM
MOSFET and Current Limit section on page 26 for more details.
Automatic maintain power signature output duty setting pin. See the Automatic
DUTY
Maintain Power Signature Function section on page 28 for more details.
PSE power and adapter power priority setting pin. Internally pull PRI up to the internal
PRI
5V power source through a 1MΩ resistor. The PSE power has a higher priority when PRI is
low.
CLSA
Power class signature pin. CLSA is used during the first two class events.
Power class signature pin. CLSB is used during the third class event and all subsequent
CLSB
class events.
AUTOCLS Auto-class function enable pin. Pull AUTOCLS low to enable the auto-class function.
BT
PSE type indicator. BT is an open-drain output.
DC/DC controller loop compensation pin. COMP is the error amplifier (EA) output in
COMP
PSR mode. COMP is internally pulled to 5V through a 10kΩ resistor in SSR mode.
DC/DC controller output voltage feedback pin. Connect one resistor divider from FB to
FB
the sensing winding to regulate the output voltage in PSR mode. In SSR mode, the internal
EA is disabled. FB is only used to provide over-voltage protection (OVP).
PD and DC/DC controller power ground. Pin 11 (GND) is the DC/DC controller’s ground,
and it is the GATE and SYNC drivers’ return pin. Place the components related to the
GND
DC/DC controller close to pin 11. Pin 29 (GND) is the PD interface’s ground. Place the
components related to the PD close to pin 29. Connect pin 11 and pin 29 in the PCB. It is
recommended to use an exposed thermal pad for thermal dissipation.
SYNC
The DC/DC controller’s synchronous MOSFET gate driver pin.
GATE
The DC/DC controller’s main MOSFET gate driver pin.
DC/DC controller internal circuit supply pin. VCC is powered through the internal LDO
from AVIN. Connect a capacitor between this pin and GND to bypass the internal
VCC
regulator. The VCC capacitor must be at minimum 1µF for flyback applications and at
minimum 4.7µF for forward applications. VCC also can be powered from an external power
source to reduce internal LDO loss.
DC/DC controller current sense, PSR VOUT compensation, and frequency dither
CS
setting pin. See the Frequency Dithering section on page 32 and the Output Voltage
Compensation section on page 31 for more details.
DC/DC controller on/off control pin. EN is internally connected to GND through a 2.5MΩ
EN
resistor.
DC/DC controller input power supply pin. Connect a bypass capacitor from the AVIN
AVIN
pin to GND. Connect AVIN to the SRC pin in application.
R_MPS
18,
22, 24
NC
19
MODE
20
21
TYP2
TYP1
MP8030 Rev. 1.0
1/31/2022
No connection. It is recommended to connect these pins to the GND pin.
DC/DC controller PSR/SSR mode and dead-time setting pin. See the Work Mode
Detection section on page 30 for more details.
Allocated PSE power type indicator. TYP2 is an open-drain output.
Allocated PSE power type indicator. TYP1 is an open-drain output.
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4
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
PIN FUNCTIONS (continued)
Pin #
23
25
26
27
28
30
31
32
Name
Description
PD power good indicator. Open-drain output, active high. PG enables the DC/DC
controller.
PD hot-swap MOSFET source pin. It is the power output from the both internal and
SRC
external hot-swap MOSFETs. Connect AVIN and the DC/DC power input to the SRC pin.
PD GATE driver of the external, parallel N-channel MOSFET for the PSE power
GATE1
supply.
SENSE PD external MOSFET current-sense pin. Connect SENSE to VDD if this pin is not used.
VDD
Positive power supply terminal from the PoE input power rail.
GATE2 PD GATE driver of the external N-channel MOSFET for the adapter power supply.
VADP Positive power supply terminal from the adapter.
Auxiliary power input detector pin. Use AUX to configure the adapter’s auxiliary power
AUX
under-voltage lockout (UVLO) threshold. AUX is internally pulled down to GND through a
2MΩ resistor. It is recommended to externally pull AUX to GND if this pin is not used.
MP8030 Rev. 1.0
1/31/2022
PG
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5
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
VDD, SENSE, SRC, TYP1, TYP2, PG, AUX,
VADP, BT, AVIN .........................-0.3V to +100V
R_MPS .........................................-0.3V to +30V
VCC, GATE, SYNC.......................-0.3V to +18V
GATE1 to SRC ............................-0.3V to +6.5V
GATE2 to VADP ..........................-0.3V to +6.5V
SENSE to VDD ...........................-6.5V to +0.3V
FB ........................................... -0.5V to +6.5V (2)
All other pins ................................-0.3V to +6.5V
PG, TYP1, TYP2, BT sinking current .......... 5mA
EN sinking current ............................. 0.5mA (3)
FB sinking current ................................. ±2mA (2)
Continuous power dissipation (TA = 25°C) (4)
QFN-32 (5mmx6mm) ............................. 3.9W (5)
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -55°C to +150°C
QFN-32 (5mmx6mm)
EVL8030-QJ-00A (5)................32.....2.........°C/W
JESD51-7 (7)............................26.....1........ °C/W
Recommended Operating Conditions (6)
Supply voltage (VDD) ........................... 0V to 57V
Adapter supply voltage (VADP) ............. 0V to 57V
VCC, GATE, SYNC voltage ......................... 16V
PG, TYP1, TYP2, BT max sink current ....... 3mA
EN maximum sink curent ..................... 0.4mA (3)
FB maximum sink current…………….... ±1mA (2)
Operating junction temp (TJ). ... -40°C to +125°C
MP8030 Rev. 1.0
1/31/2022
Notes:
1) Exceeding these ratings may damage the device.
2) FB is clamped by an internal circuit. The sink/source current
should be limited. See the Output Voltage Setting section on
page 36 for more details.
3) If EN is pulled above 6.5V externally, the pull-up current
should be limited. Refer to Enable Control (EN) section on
page 29 for more details.
4) The maximum allowable power dissipation is a function of the
maximum junction temperature, TJ (MAX), the junction-toambient thermal resistance, θJA, and the ambient
temperature, TA. The maximum allowable continuous power
dissipation at any ambient temperature is calculated by PD
(MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum
allowable power dissipation can produce an excessive die
temperature, and the regulator may go into thermal shutdown.
Internal thermal shutdown circuitry protects the device from
permanent damage.
5) Measured on EVL8030-QJ-00A, 4-layer, 1oz thick Cu,
160mmx55mm PCB.
6) The device is not guaranteed to function outside of its
operating conditions.
7) The value of θJA given in this table is only valid for comparison
with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD51-7,
and simulated on a specified JEDEC board. They do not
represent the performance obtained in an actual application.
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6
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS
PD interface section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Detection
Detection on
Detection off
Symbol
Bias current
Detection resistance
Classification
Classification stability
time
VCLASS output voltage
Condition
VDET-ON VDD rising
VDET-OFF VDD rising
VDD = 10.1V, not in mark event, measure
IBIAS
ISUPPLY
VDD = 1.5V to 10.1V, calculate with ΔV /
RDET
ΔI
VCLSA/B
From VCL-ON to CLSA or CLSB, stable
voltage output
13V < VDD < 21V, 1mA < ICLASS < 44mA
RCLASS = 578Ω, 13V ≤ VDD ≤ 21V,
measure input current, guaranteed by
VCLSA and VCLSB
RCLASS = 110Ω, 13V ≤ VDD ≤ 21V,
measure input current, guaranteed by
(8),
Min
Typ
Max
Units
1.4
10.1
1
11
V
V
12
μA
25
26.1
kΩ
0.4
1
ms
1.11
1.16
1.21
V
1.8
2
2.4
9.9
10.55
11.3
17.7
18.7
19.8
26.6
28.15
29.7
38.2
40.4
42.6
24.1
VCLSA and VCLSB
Classification current for
both the CLSA and CLSB
pins
ICLASS
RCLASS = 62Ω, 13V ≤ VDD ≤ 21V, measure
input current, guaranteed by VCLSA and
mA
VCLSB
RCLASS = 41.2Ω, 13V ≤ VDD ≤21V,
measure input current, guaranteed by
VCLSA and VCLSB
RCLASS = 28.7Ω, 13V ≤ VDD ≤ 21V,
measure input current, guaranteed by
VCLSA and VCLSB
Auto-class signature
current
Auto-class signature
timing
Long first class event
Classification lower
threshold
Classification lower
threshold hysteresis
Classification upper
threshold
Classification upper
threshold hysteresis
Mark event reset
threshold
Max mark event voltage
Mark event current
MP8030 Rev. 1.0
1/31/2022
IACS
After tACS when the auto-class function is
enabled, generated internally.
1
tACS
Change to IACS, from triggering VCL-ON
76
tLCE
Determine type 3/4 PoE, from triggering
VCL-ON
Regulator turns on, VDD rising
VCL-ON
VCL-L-HYS Low threshold hysteresis
VCL-OFF
Regulator turns off, VDD rising
3
mA
81.5
87
ms
76
81.5
87
ms
12
12.5
13
V
1.3
1.5
1.7
V
21
22
23
V
VCL-H-HYS High threshold hysteresis
0.5
V
VMARK-L
4.5
5
5.5
V
VMARK-H
IMARK
10.5
0.5
11
1.1
11.5
2
V
mA
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
PD interface section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Mark event resistance
Symbol Condition
2-point measurement at 5.5V and
RMARK
10.1V, with ΔV / ΔI
IC supply current during
classification
IIN-CLASS
VDD = 17.5V, CLSA and CLSB floating
Class leakage current
ILEAKAGE
VCLSA = VCLSB = 0V, VDD = 57V, test
both the CLSA and CLSB pins
AUTOCLS low-voltage input
AUTOCLS high-voltage
input
Under-Voltage Lockout (UVLO)
VDD turn-on threshold
VDD-R
VDD turn-off threshold
VDD-F
VDD UVLO hysteresis
VDD-HYS
IC supply current during
IIN
operation
Input leakage current
Hot-Swap MOSFET and Current Limit
Internal MOSFET on
RON
resistance
Leakage current
ISRC-LK
Internal MOSFET inrush
limit
Inrush current termination
Inrush to operation mode
delay
Current foldback threshold
Foldback deglitch time (9)
GATE1 source current
GATE1 sink current
MP8030 Rev. 1.0
1/31/2022
180
VDD rising
VDD falling
37
30
5
ILIMIT
IINRUSH
ITERM
Max
Units
12
kΩ
300
μA
1
μA
0.4
V
V
38.5
31.5
7
40
33
V
V
V
No load and no R_MPS resistor,
disconnect AVIN from SRC
VDD = 29.5V
1
1.5
mA
150
250
μA
ISRC = 500mA
0.35
VDD = 57V, VSRC = 0V, AUX = high, PRI
= high
1
130
ILIM pin voltage threshold
Typ
1.2
ILIM pin detection period
ILIM pin detection current
Internal MOSFET current
limit
Min
(8),
0.9A setting voltage range
1.6A setting voltage range
ILIM = 0V, VSRC drops from VDD, VDD VSRC = 1V
ILIM connected to GND through a
7.15kΩ resistor, VSRC drops from VDD,
VDD - VSRC = 1V
ILIM = 0V, VSRC ramps up from low to
high, VDD - VSRC = 1V
ILIM connected to GND through a
7.15kΩ resistor. VSRC ramps up from
low to high, VDD - VSRC = 1V
1
VSRC falling, VDD - VSRC
VSRC falling to inrush current foldback
VGATE1 - VSRC = 4V
VGATE1 - VSRC = 4V
15
μA
180
0.8
2.2
μs
μA
V
V
0.75
0.9
1.05
A
1.4
1.6
1.8
A
70
130
190
mA
170
230
290
mA
VSRC rising, ITERM / IINRUSH
tDELAY
270
165
Ω
IINRUSH
75%
80
90
100
ms
8.2
10
1
10
30
11.8
V
ms
μA
μA
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8
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
PD interface section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
GATE1 max driving voltage
External MOSFET current
limit
SENSE pin leakage current
PG, BT, TYP1, TYP2
Output low voltage
Leakage current
Maintain Power Signature
Automatic maintain power
signature current enable
threshold
Automatic maintain power
signature current threshold
hysteresis
R_MPS pin output voltage
VDD - VSENSE
Typ
22
26
VSENSE = VDD = 54V
ISINK = 1mA
Logic = high, connect to 57V
0.2
IPORT-MPS Load current falling
Load current rises to disable the
maintain power signature current
1mA to 20mA
Duty cycle
On period
Off period
Duty cycle
On period
Off period
Duty cycle
On period
Type 3/4 PSE, R_MPS
output duty cycle with DUTY
pin shorted to GND
Type 3/4 PSE, R_MPS
output duty cycle with DUTY
pin to GND through a
7.15kΩ resistor
Off period
Duty cycle
On period
Off period
Type 3/4 PSE, R_MPS
output duty cycle with DUTY
pin floating
External FET voltage drop
control threshold
DUTY pin detection current
DUTY pin detection period
23
Max
ADPUV-R
ADPUV-F
V
30
mV
0.1
μA
0.4
1
V
μA
36
mA
10
mA
26
200
235
270
ms
39
190
17%
45
221
52
260
ms
ms
75
115
14
210
25
V
95
165
ms
ms
18
290
36
ms
ms
ms
ms
26
130
6% duty cycle setting voltage range
11.5% duty cycle setting voltage
range
17% duty cycle setting voltage range
Units
24
37%
85
140
6%
16
250
11.5%
31
VDS = VSENSE - VSRC
DUTY pin voltage threshold
MP8030 Rev. 1.0
1/31/2022
Min
6
Type 1/2 PSE, R_MPS
output duty cycle
Adapter Supply
VADP pin UVLO rising
VADP pin UVLO falling
Condition
165
130
1
mV
0.8
μA
μs
V
2.2
V
180
2.5
7.8
6.5
(8),
V
8.3
7
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8.8
7.5
V
V
9
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
PD interface section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
AUX pin high threshold
voltage
AUX pin threshold
hysteresis
VAUX-H
VAUX = 2V
VAUX = 57V
VGATE2 - VADP = 4V
VGATE2 - VADP = 4V
GATE2 to VADP
VADP - VSRC voltage after the
adapter supply is enabled
GATE2 source current
GATE2 sink current
GATE2 max driving voltage
GATE2 turn-on threshold
MP8030 Rev. 1.0
1/31/2022
Min
Typ
Max
Units
1.92
2
2.08
V
VAUX-HYS
AUX leakage current
Power Priority
PRI pin input high voltage
PRI pin input low voltage
PRI pin internal pull up
resistor
Thermal Shutdown
Thermal shutdown
temperature (9)
Thermal shutdown
hysteresis (9)
Condition
(8),
0.15
V
1
2.5
20
μA
μA
μA
μA
V
200
6
0
0.45
V
0.4
V
V
2
1
MΩ
TPD-SD
150
°C
TPD-HYS
20
°C
Pull up to the internal 5V VCC
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10
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS
Controller section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
(8),
Parameter
Symbol Condition
Min
Typ
Max
Units
Power Supply and UVLO
AVIN UVLO rising threshold
AVIN UVLO falling threshold
VCC regulation voltage
VCC dropout voltage
VCC UVLO rising threshold
VCC UVLO falling threshold
VAVIN-R
VAVIN-F
VCC
VCC-DROP
VCC-R
VCC-F
VAVIN rising, start charging to VCC
VAVIN falling
Load = 0mA to 20mA
VAVIN = 8V, IVCC = 10mA
VAVIN > VAVIN-R, VCC rising
VAVIN > VAVIN-R, VCC falling
MODE pin float, VFB = -0.1V, CS =
100mV, COMP = 0V, IQ = IDD ICOMP, GATE and SYNC floating,
test AVIN pin
MODE = 0V, VCOMP = 0V, IQ = IDD ICOMP, GATE and SYNC floating,
test the AVIN pin
4.5
3.8
5.5
4.8
8.5
1.5
5.7
5.3
6.5
5.8
V
V
V
V
V
V
Start switching
Stop switching
1.9
Quiescent current
Enable (EN) Control
EN turn-on threshold
EN turn-on hysteresis
EN high micro-power
threshold
EN low micro-power
threshold
EN input current
EN turn-on delay
Voltage Feedback (FB)
FB reference voltage
FB leakage current
FB OVP threshold
OVP hiccup off time
Minimum diode conduction
time for FB sample
IQ
VEN-R
VEN-HYS
VEN-H
Start internal logic
VEN-L
Stop internal logic
IEN
VREF
IFB
TJ = 25°C
TJ = -40°C to +125°C
VFB = 2V
VCS = 50mV, RCS-GND = 3.3kΩ (11)
VCS = 50mV, RCS-GND = 6.8kΩ (11)
VCS = 50mV, RCS-GND = 12.7kΩ (11)
900
μA
500
μA
2
0.2
2.1
V
V
1.0
V
V
μA
μs
2
500
1.98
1.97
120%
tSAMPLE
6.0
5.6
0.4
VEN = 5V
EN on to GATE output
VFBOVP
Regulation compensation
current into FB
5.4
5
2
2
10
125%
340
2.02
2.03
50
130%
V
V
nA
VREF
ms
0.5
0.6 (10)
μs
2.7
5.4
10.8
μA
μA
μA
0.59
mA/V
-110
μA
Error Amplifier (EA)
EA transconductance
GEA
EA maximum source current
IEA
MP8030 Rev. 1.0
1/31/2022
MODE floating, VFB is ±50mV from
VREF, VCOMP = 1.5V
MODE floating, VCOMP = 1.5V,
VFB = 1.9V
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11
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
Controller section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol Condition
EA maximum sink current
COMP high voltage
IEA
VCOMP
COMP internal pull-up
resistor
Soft Start (SS)
Internal soft-start time
MODE floating, VCOMP = 1.5V,
VFB = 2.1V
MODE floating, VFB = 1.9V
MODE = 0V, float COMP
SSR mode
tSS
MODE floating, test FB from 0V to
2V
MODE = 0V, test COMP from
1.5V to 3.5V
Current Sense (CS)
Maximum CS limit
ILIMIT-MAX
Low threshold current limit
ILIMIT-MIN In PSR mode
SCP limit
Current leading edge
tLEB
blanking time
CS amplifier gain
GCS
CS input bias current
VCS = 160mV
Pulse-Width Modulation (PWM) Switching
Switching frequency
fSW
Minimum foldback frequency
In PSR mode, COMP = 0V
in PFM mode
Mode, Dead Time, Dither, VOUT Compensation Setting (MODE and CS Pin)
MODE pin detection current
IMODE
CS pin detection current
ICS
MODE and CS pin detection
tMODE,
period
tCS
Voltage level 1 range
Voltage level 2 range
MODE, CS pin detection
VMODE,
Voltage level 3 range
threshold voltage (12)
VCS
Voltage level 4 range
Voltage level 5 range
GATE Driver Signal
GATE driver impedance
IGATE
IGATE = -20mA
(sourcing)
GATE driver impedance
IGATE
IGATE = 20mA
(sinking)
GATE source current
VCC = 8.5V, GATE = 10nF, test
capability (9)
gate rising speed
MP8030 Rev. 1.0
1/31/2022
Min
Typ
Max
(8),
Units
110
μA
4
5
V
10
kΩ
15
ms
20
140
33
240
225
160
36
300
180
39
360
250
ns
11
10
50
V/V
nA
250
275
kHz
30
35
90
mV
mV
mV
40
100
kHz
45
110
μs
200
0.15
0.4
0.85
1.5
0.25
0.55
1.1
2.2
μA
μA
V
V
V
V
V
2
Ω
1.7
Ω
2
A
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12
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
Controller section, VDD = 54V, SRC and AVIN are connected together, TJ = -40°C to +125°C
typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol Condition
GATE sink current capability
Min
VCC = 8.5V, GATE = 10nF, test
gate falling speed
(9)
GATE output high voltage
VGATE
GATE output low voltage
Minimum GATE on time
GATE max duty cycle
SYNC Driver Signal
SYNC driver impedance
(sourcing)
SYNC driver impedance
(sinking)
SYNC source current
capability (9)
SYNC sink current capability
VGATE
tON-MIN
DMAX
Typ
Max
1.7
Units
A
VCC 0.05
V
0.05
250
70
V
ns
%
ISYNC
IGATE = -20mA
5
Ω
ISYNC
IGATE = 20mA
2.3
Ω
0.8
A
1.2
A
VCC = 8.5V, SYNC = 10nF, test
the SYNC rising speed
VCC = 8.5V, SYNC = 10nF, test
the SYNC falling speed
(9)
SYNC output high voltage
VSYNC
SYNC output low voltage
Protection
Overload protection hiccup
on time (9)
Overload protection hiccup
off time (9)
Thermal shutdown
temperature (9)
Thermal shutdown
hysteresis (9)
VSYNC
(8),
VCC 0.05
V
0.05
V
4.8
ms
340
ms
TSD
150
°C
THYS
20
°C
Notes:
8)
9)
10)
11)
Guaranteed by over-temperature correlation. Not tested in production.
Guaranteed by characterization. Not tested in production.
It is recommended to make the output diode conduction time longer than 0.7µs.
RCS-GND is the resistance from the CS pin to GND. This includes the current-sense resistor from the MOSFET source to GND and the
resistor from the MOSFET’s source to the CS pin.
12) For different voltage levels, see Table 6 on page 30 and Table 7 on page 32.
MP8030 Rev. 1.0
1/31/2022
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13
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL CHARACTERISTICS
Operation Current Limit vs.
Junction Temperature
300
40
240
36
180
32
120
28
Rising
24
Falling
20
-50
PD Inrush Current Termination
vs. Junction Temperature
75
70
65
-50
2
0
50
100
JUNCTION TEMPERATURE (°C)
1.6
1.2
0.8
ILIM=7.15K
ILIM=GND
0
-50
MP8030 Rev. 1.0
1/31/2022
-50
0
50
100
JUNCTION TEMPERATURE (°C)
150
0
50
100
JUNCTION TEMPERATURE ( C)
150
PD Inrush to Operation Mode
Delay vs. Junction Temperature
95
90
85
80
-50
150
PD Current Limit vs. Junction
Temperature
0.4
ILIM=GND
0
100
80
ILIM=7.15K
60
0
50
100
150
JUNCTION TEMPERATURE (°C)
PD INRUSH TO OPERATION
MODE DELAY (ms)
PD INRUSH CURRENT
TERMINATION (%)
PD INRUSH CURRENT LIMIT
(mA)
44
85
PD CURRENT LIMIT (A)
PD Inrush Current Limit vs.
Junction Temperature
PD SUPPLY CURRENT (mA)
OPERATION CURRENT LIMIT (A)
VDD = 54V, TA = 25°C, unless otherwise noted.
0
50
100
JUNCTION TEMPERATURE (°C)
150
PD Supply Current during
Operation vs. Junction
Temperature
1.5
1
0.5
0
-50
0
50
100
JUNCTION TEMPERATURE (°C)
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14
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL CHARACTERISTICS (continued)
INTERNAL MOSFET ON
RESISTANCE (Ω)
30
28
26
24
22
20
0
50
100
JUNCTION TEMPERATURE (°C)
0.8
0.6
0.4
0.2
Class Voltage vs. Junction
Temperature
1.2
1.16
1.12
-50
13
0
50
100
JUNCTION TEMPERATURE (°C)
-50
0
50
100
JUNCTION TEMPERATURE (°C)
150
1.08
150
22.5
22
21.5
21
Upper_OFF
20.5
-50
0
50
100
JUNCTION TEMPERATURE (°C)
150
5.4
12.5
12
11.5
11
10.5
Lower_ON
Lower_OFF
9.5
Upper_ON
20
Mark Event Reset Threshold vs.
Junction Temperature
CLASS Lower Threshold vs.
Junction Temperature
10
150
CLASS Upper Threshold vs.
Junction Temperature
MARK EVENT RESET
THRESHOLD (V)
CLASS LOWER THRESHOLD (V)
1
0
-50
1.24
CLASS VOLTAGE (V)
Internal MOSFET On Resistance
vs. Junction Temperature
Detection Resistance vs.
Junction Temperature
CLASS UPPER THRESHOLD (V)
DETECTION RESISTANCE (kΩ)
VDD = 54V, TA = 25°C, unless otherwise noted.
5.2
5
4.8
4.6
9
-50
MP8030 Rev. 1.0
1/31/2022
0
50
100
JUNCTION TEMPERATURE (°C)
150
-50
0
50
100
JUNCTION TEMPERATURE (°C)
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15
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL CHARACTERISTICS (continued)
1.2
1.1
1
0.9
-50
VADP UVLO THRESHOLD (V)
9
0
50
100
JUNCTION TEMPERATURE (°C)
150
MARK EVENT RESISTANCE (kΩ)
1.3
Mark Event Current vs. Junction
Temperature
VADP UVLO Threshold vs.
Junction Temperature
8.5
8
7.5
7
Rising
Falling
6.5
6
-50
0
50
100
JUNCTION TEMPERATURE (°C)
9
150
7
6
-50
26
24
22
20
-50
MP8030 Rev. 1.0
1/31/2022
0
50
100
JUNCTION TEMPERATURE (°C)
150
150
AUX UVLO Threshold vs.
Junction Temperature
2
1.9
1.8
Rising
1.7
Falling
1.6
AUTO MPS CURRENT ENABLE
THRESHOLD (mA)
EXTERNAL MOSFET CURRENT
LIMIT (mV)
28
0
50
100
JUNCTION TEMPERATURE (°C)
2.1
-50
External MOSFET Current Limit
vs. Junction Temperature
30
Mark Event Resistance vs.
Junction Temperature
8
2.2
AUX UVLO THRESHOLD (V)
MARK EVENT CURRENT (mA)
VDD = 54V, TA = 25°C, unless otherwise noted.
60
0
50
100
JUNCTION TEMPERATURE (°C)
150
Auto Maintain Power Signature
Current Enable Threshold vs.
Junction Temperature
50
40
30
20
10
0
-50
0
50
100
150
JUNCTION TEMPERATURE (°C)
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16
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VDD = 54V, TA = 25°C, unless otherwise noted.
EN UVLO Threshold vs. Junction
Temperature
VCC Voltage vs. VCC Load Current
2.1
EN UVLO THRESHOLD (V)
VCC VOLTAGE (V)
12
11
10
9
8
7
6
5
4
3
2
2
1.9
1.8
1.7
1.5
0
5
10
15
VCC LOAD CURRENT (mA)
20
-50
6
2.1
5.6
2.05
150
2
VREF (V)
5.2
4.8
1.95
1.9
4.4
1.85
Rising
Falling
1.8
4
-50
0
50
100
JUNCTION TEMPERATURE (℃)
-50
150
270
32
MINIMUM FOLDBACK
FREQUENCY
(kHz)
34
260
250
240
230
220
210
200
MP8030 Rev. 1.0
1/31/2022
0
50
100
JUNCTION TEMPERATURE (℃)
150
PSR mode
280
-50
0
50
100
JUNCTION TEMPERATURE (℃)
Minimum Foldback Frequency vs.
Junction Temperature
Frequency vs. Junction
Temperature
FREQUENCY (kHz)
0
50
100
JUNCTION TEMPERATURE (℃)
Reference Voltage vs. Junction
Temperature
VCC UVLO vs. Junction Temperature
VCC UVLO THRESHOLD (V)
Rising
Falling
1.6
150
30
28
26
24
22
20
-50
0
50
100
JUNCTION TEMPERATURE (℃)
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150
17
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VDD = 54V, TA = 25°C, unless otherwise noted.
Low Threshold Current Limit vs.
Junction Temperature
PSR mode
180
39
170
37
35
160
VLIMIT (mV)
VLIMIT (mV)
Current Limit vs. Junction
Temperature
150
140
130
33
31
29
27
120
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
25
-50
0
50
100
JUNCTION TEMPERATURE (℃)
150
OVP Threshold vs. Junction
Temperature
2.6
2.55
VOVP (V)
2.5
2.45
2.4
2.35
2.3
-50
MP8030 Rev. 1.0
1/31/2022
0
50
100
JUNCTION TEMPERATURE (℃)
150
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18
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 54V, VADP = 48V, VOUT = 5V, IOUT = 14A, TA = 25°C, set in SSR forward mode, unless
otherwise noted.
95
90
85
80
75
70
65
60
55
50
Load Regulation
LOAD REGULATION (%)
EFFICIENCY (%)
Efficiency vs. Load Current
Vin=41V
Vin=54V
Vin=57V
1
0.5
0
Vin=41V
Vin=54V
Vin=57V
-0.5
-1
0
2
4
6
8
10
LOAD CURRENT (A)
12
14
0
2
4
6
8
10
12
LOAD CURRENT (A)
14
Line Regulation
LINE REGULATION (%)
1
0.5
0
Iout=0A
Iout=7A
Iout=14A
-0.5
-1
40
MP8030 Rev. 1.0
1/31/2022
45
50
55
VDD INPUT VOLTAGE (V)
60
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19
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 54V, VADP = 48V, VOUT = 5V, IOUT = 14A, TA = 25°C, set in SSR forward mode, unless
otherwise noted.
Steady State
Steady State
IOUT = 0A
IOUT = 14A
CH1:
VOUT/AC
CH1:
VOUT/AC
CH2: VDD
CH2: VDD
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
Start-Up through VDD
Start-Up through VDD
IOUT = 0A
IOUT = 14A
CH1: VOUT
CH1: VOUT
CH2: VDD
CH2: VDD
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
Shutdown through VDD
Shutdown through VDD
IOUT = 0A
IOUT = 14A
CH1: VOUT
CH1: VOUT
CH2: VDD
CH2: VDD
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
MP8030 Rev. 1.0
1/31/2022
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20
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 54V, VADP = 48V, VOUT = 5V, IOUT = 14A, TA = 25°C, set in SSR forward mode, unless
otherwise noted.
SCP Entry
SCP Entry
IOUT = 0A to short
IOUT = 14A to short
CH1: VOUT
CH1: VOUT
CH2: VDD
CH2: VDD
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
SCP Recovery
SCP Recovery
IOUT = short to 0A
IOUT = short to 14A
CH1: VOUT
CH1: VOUT
CH2: VDD
CH2: VDD
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
PSE Start-Up
PSE Start-Up
IOUT = 0A
IOUT = 14A
CH1: VOUT
CH1: VOUT
CH2: VDD
CH2: VDD
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
MP8030 Rev. 1.0
1/31/2022
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21
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 54V, VADP = 48V, VOUT = 5V, IOUT = 14A, TA = 25°C, set in SSR forward mode, unless
otherwise noted.
Adapter Start-Up
Adapter Start-Up
IOUT = 0A
IOUT = 14A
CH1: VOUT
CH1: VOUT
CH2: VADP
CH2: VADP
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
Adapter Shutdown
Adapter Shutdown
IOUT = 0A
IOUT = 14A
CH1: VOUT
CH1: VOUT
CH2: VADP
CH2: VADP
CH3: VSW
CH3: VSW
CH4: IPRI
CH4: IPRI
Load Transient Response
Load Transient Response
IOUT = 0A to 7A, IRAMP = 25mA/μs
IOUT = 7A to 14A, IRAMP = 25mA/μs
CH1:
VOUT/AC
CH1:
VOUT/AC
CH4: IOUT
CH4: IOUT
MP8030 Rev. 1.0
1/31/2022
MonolithicPower.com
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22
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 54V, VADP = 48V, VOUT = 5V, IOUT = 14A, TA = 25°C, set in SSR forward mode, unless
otherwise noted.
Level (dBμV)
Frequency (Hz)
MP8030 Rev. 1.0
1/31/2022
Radiated Emissions Results
Level (dBμV/m)
Conducted Emissions Results
Frequency (Hz)
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23
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
FUNCTIONAL BLOCK DIAGRAM
VDD
DUTY
SENSE
VADP
GATE2
GATE1
Drive
Drive
SRC
ILIM
TYP1
RDET
Maintain Power
Signature
R_MPS
DET
TYP2
AUX
VAUX-H
SENSE, ILIM
Control Logic and
Gate Driver
PRI
CLSA
PG
BT
Classification
14.5V to 20.5V
CLSB
GND
AUTOCLS
AVIN
EN
VIN UVLO
Regulator
Enable Control
VCC
VCC UVLO
Driver
GATE
Oscillator and Slope
Compensation
VCC
Dither
PWM
Logic
PFM
Driver
SYNC
5V
MODE
PWM
MODE Dead
Time
10kΩ
Comparator
OCP
Protection
Cycle-by-Cycle Hiccup Mode
MODE
PSR Low
Threhsold
COMP
SS in SSR
2V
SS
FB
FB Sample and
Hold
36mV
-
MODE
+
+
-
GND
+
Current-Sense
Amplifier
CS
+
-
+
2.5V
OCP
OVP
OLP
PSR Mode VOUT
Compensation
Current
4.8ms
OLP
OLP, SCP, OVP Lead to Hiccup
Protection
+
50µs
Timer
0.16V
-
SCP
+
-
0.3V
+
-
Dither and
Compensation
Figure 1: Functional Block Diagram
MP8030 Rev. 1.0
1/31/2022
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24
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
OPERATION
The MP8030 is a fully integrated, IEEE
802.3af/at/bt-compliant, Power over Ethernet
(PoE) powered device (PD) power supply
converter. It includes a PD interface and highefficiency flyback/forward controller.
PD INTERFACE
The MP8030 PD interface has all the functions
of IEEE 802.3af/at/bt, including detection,
classification, input current control, a 100V hotswap MOSFET, and an automatic maintain
power signature function.
PD
Class
0
1
2
3
4
5
6
7
8
Classification
PSE distributes power to PDs based on the
classification results. Classification mode is
active when the input voltage is between 14.5V
and 20.5V. The MP8030 PD presents different
currents in classification mode (see Table 1).
Table 1: Different Classification Power Rating and Setting with PD
Power
Class Cycle with
CLSA
CLSB
CLSA
Rating (W)
Max Power
Signature
Signature
Resistor (Ω)
0.44 to 12.95
1
0
0
578
0.44 to 3.84
1
1
1
110
3.84 to 6.49
1
2
2
62
6.49 to 12.95
1
3
3
41.2
12.95 to 25.5
2, 3
4
4
28.7
25.5 to 40
4
4
0
28.7
40 to 51
4
4
1
28.7
51 to 62
5
4
2
28.7
62 to 71.3
5
4
3
28.7
IEEE802.3bt supports an 8-level class power
rating, with up to 5 classification cycle
operations. These classification cycles have the
below functions:
•
All PSEs perform one cycle classification for
the class 0, class 1, class 2, and class 3
PDs.
•
Type 2 PSEs perform 2-cycle classification
if a class 4 signature is detected during the
first class cycle.
•
Detection
The MP8030 PD integrates an internal
detection resistor. When the PSE applies two
safe voltages (between 2.7V and 10.1V) to the
MP8030, the MP8030 PD will typically shows a
25kΩ resistance between the VDD and GND
pins.
Type 3 and type 4 PSEs start their third
cycle classification if a class 4 signature is
detected during the first and second class
cycle. Based on the third classification
result, type 3 and type 4 PSEs follow one of
the operations listed below:
If the third classification result is a class 4
signature, classification stops and there is a
class 4 PD.
CLSB
Resistor (Ω)
578
110
62
41.2
28.7
578
110
62
41.2
If the third classification result is class 2 or
class 3 signature, the type 4 PSE performs
a fourth and fifth cycle classification.
The MP8030 PD performs a class signature
signal with the CLSA pin in the first and second
class cycles. The MP8030 PD performs a class
signature signal with the CLSB pin in the
remaining class cycles, unless VDD drops to its
mark event reset threshold.
Both CLSA and CLSB use the same 1.16V
output voltage for classification. The maximum
output current is limited for protection.
Auto-Class Function
IEEE802.3bt also supports an auto-class
function that allows the PD to communicate its
effective maximum power consumption to the
PSE. When MP8030 PD auto-class function is
enabled (by pulling the AUTOCLS pin low), the
PD switches the class current to class 0 within
If the third classification result is a class 0 or
class 1 signature, the devices continues to
the fourth cycle classification.
MP8030 Rev. 1.0
1/31/2022
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
76ms to 87ms. After the first long time
classification function works, this class 0
classification current lasts until the first class is
complete.
is triggered. If VSRC is below VDD by less than
10V, GATE1 turns on to charge the bulk
capacitor. The MP8030 PD turns off the
external MOSFET under light-load conditions.
The auto-class function can indicate to a type 3
or 4 PSE that it supports the auto-class
function.
The internal MOSFET and external MOSFET
have different current limit control loops. The
internal MOSFET current limit is configured by
the ILIM pin, while the external MOSFET
current limit is configured by a resistor (RSENSE)
between the VDD and SENSE pins. To reduce
additional power loss and cost, the external
MOSFET current limit can be disabled by
removing RSENSE (connecting the SENSE pin to
the VDD pin). It is recommended for RSENSE to
be 18mΩ. When an external RSENSE is used, it is
recommended to connect the ILIM pin to GND
for the lowest total current limit.
Under-Voltage Lockout (UVLO) and the
Power Supply Voltage
The MP8030 PD integrates one under-voltage
lockout (UVLO) circuit with a large hysteresis.
The UVLO block ensures that the PD starts up
when VDD exceeds 40V and shuts down when
VDD drops below 30V.
The MP8030 PD also has an inrush current limit
during start-up. This current is about 1/7 of the
steady state current limit configured by the ILIM
pin.
Figure 2 shows the internal and external
MOSFET start-up sequence.
Hot-Swap MOSFET and Current Limit
The MP8030 PD interface integrates one 100V
MOSFET for output disconnect.
PSE Power On
VDD > UVLO_R?
When the PD voltage is powered by the PSE,
and VDD exceeds the rising UVLO threshold, the
hot-swap MOSFET starts passing a limited
current (IINRUSH) to charge the DC/DC
converter’s input bulk capacitor. The inrush
current limit function works until it drops below
75% of the inrush current limit, and then the
current limit changes to the normal current limit
threshold.
To meet the different power ratings, the
MP8030 PD supports a configurable current
limit with the ILIM pin. The ILIM pin sources a
current after VDD rises to the UVLO threshold.
This current detects the configured current limit
level. Table 2 shows the ILIM configurations.
Table 2: ILIM Configurations
ILIM to GND Resistance (kΩ) Current Limit
(A)
Min
Typ
Max
0
1.4
0.9
0
7.15
9.09
1.6
5.76
The GATE1 pin can drive one external Nchannel MOSFET, which is connected in
parallel with the internal 0.35Ω MOSFET.
GATE1 turns on the external MOSFET after
tDELAY (about 90ms) completes. If VDD - VSRC
exceeds 10V after this delay, GATE1 does not
turn on because over-current protection (OCP)
MP8030 Rev. 1.0
1/31/2022
Yes
No
Inrush Current
90ms
Delay
VVDD - VSRC < 10V
Yes
Current < 75% of Inrush
Limit?
Both are OK
Yes
Change to Steady
State Current Limit
Drive GATE1
Supply Load
Together
Figure 2: Internal MOSFET and External MOSFET
Start-Up Sequence
The internal and external MOSFETs have fastoff current protection if there is a short-circuit
event. After GATE1 turns off, the internal
MOSFET recovers if VIN - VSRC < 10V.
If an overload event occurs when both the
internal MOSFET and external MOSFET are
connected, the current limit function can work in
a few ways, described below:
•
If the internal MOSFET triggers a current
limit first, the internal current is limited, and
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
additional current goes through the external
MOSFET. If the external MOSFET also
reaches its current limit, the external
MOSFET pulls GATE1 low and VSRC drops.
If VDD - VSRC exceeds 10V for 1ms, the
external MOSFET turns off, and the internal
MOSFET current limit switches to the inrush
limit threshold. At the same time, PG pulls
low to disable the DC/DC controller, then
works in a new start cycle with the inrush
current limit. During this over-current
condition, PG recovers without a 90ms
delay after the inrush completes.
•
•
PSE Power On
VDD > UVLO_R?
No
Yes
Inrush Current
90ms Timer
Current < 75% of
inrush limit?
Timer ran out?
If the internal MOSFET or external
MOSFET triggers the fast-off current limit,
the MP8030 PD quickly turns off the related
MOSFET then restarts with a delay.
Power Good (PG) and Delay
The MP8030 PD has one PG output to enable
the DC/DC controller after the inrush period
finishes and the PSE is ready to provide high
power. PG is an open-drain output with up to a
100V voltage rating.
PG is in high impedance when the device
meets the below conditions:
•
The device has changed to the steady
current limit, which means that the inrush
period is complete.
•
The 90ms delay (tDELAY) from UVLO has
completed.
Then a wall power adapter is detected on AUX,
and VADP exceeds its UVLO threshold (see
Figure 3).
The PG signal resets when VDD UVLO_F is
triggered, if over-temperature protection (OTP)
occurs, or if VDD - VSRC > 10V for more than
1ms. The 90ms timer only works after VDD
UVLO is triggered.
MP8030 Rev. 1.0
1/31/2022
Yes
Yes
Change to steady
state current limit
Both are OK
PG rises to high
If the external MOSFET triggers the current
limit first, GATE1 pulls low. Additional
current passes through the internal
MOSFET and finally triggers the internal
current limit. VSRC drops after both current
limits are triggered and finally runs into
current foldback mode (inrush current limit).
At the same time, PG is pulled low.
No
VDD - VSRC >10V
BT and TYP1/2 act
based on PSE type
VDD - VSS <
UVLO_F?
No
for 1ms?
Yes
Yes
PG and GATE1 drops
VDD - VSRC <
PG, BT, and TYP1/2
signals reset
PSE Power Off
10V
Yes
Drive GATE1
Figure 3: PG Logic
PSE and Allocated Power Indicators
IEEE802.3bt supports 4 different PSE power
supplies. The BT, TYP1, and TYP2 pins
indicate the PSE-allocated power type. Table 3
on page 28 lists the detailed power level
indicators. Note that the indicator only shows
high when it is in logic high and pulled up to a
high voltage through an external pull-up
resistor.
The TYP1, TYP2, and BT signals are active
after tDELAY (about 90ms). The outputs become
inactive (high impedance) when the input
voltage (VDD) falls below its UVLO threshold, or
if OTP is triggered. The BT, TYP1, and TYP2
signals are latched in the MP8030 PD after
start-up and do not reset until VDD drops to its
mark event reset threshold.
The TYP1 and TPY2 pins go low if an adapter
is detected. BT is high under this condition.
Table 4 on page 28 shows demotion cases.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
PSE Type
Type 1
Type 2
Type 2
Type 3
Type 4
Type 4
PD Class
Class 0
Class 1
Class 2
Class 3
Table 3: PSE and Allocated Power Indicator
PSE Allocated Power Number of Class Cycles
12.95W
3.84W
1
6.49W
12.95W
Class 4
25.5W
Class 0
Class 1
Class 2
Class 3
Class 4
Class 5
Class 6
Class 7
Class 8
12.95W
3.84W
6.49W
12.95W
25.5W
40W
51W
62W
71.3W
PSE Type
PD Class
Type 2
Type 3
Type 4
Type 3
Type 4
Type 3
Type 4
Class 4
Classes
4–8
Classes
5–8
Classes
7–8
TYP1
TYP2
High
High
High
2
High
High
Low
1
Low
High
High
2, 3
Low
High
Low
4
Low
Low
High
5
Low
Low
Low
BT
TYP1
TYP2
Table 4: Power Demotion Cases
PSE Allocated Power Number of Class Cycles
12.95
1
High
High
High
12.95
1
Low
High
High
25.5
2, 3
Low
High
Low
51
4
Low
Low
High
Automatic
Maintain
Power
Signature
Function
To maintain the PSE power supply, the
MP8030 supports an automatic maintain power
signature and the current is configured by a
resistor on the R_MPS pin.
The MP8030 also has one DUTY pin to
configure the R_MPS pin’s duty cycle, which
can compensate the effects of the long cable
and bulk bus capacitors. After VDD reaches the
UVLO rising threshold, the DUTY pin sources
one pulse current to detect the maintain power
signature function duty cycle setting. Table 5
shows the DUTY pin’s configuration options.
The DUTY signal resets after VDD falls to its
UVLO falling threshold.
Table 5: DUTY Configurations
DUTY to GND Resistance (kΩ) R_MPS Duty
Cycle (%)
Min
Typ
Max
0
0
1.4
6
5.76
7.15
9.09
11.5
17.4
Float
Float
17
MP8030 Rev. 1.0
1/31/2022
BT
With type 1 and type 2 PSE inputs, the MP8030
generates a voltage on the R_MPS pin with a
fixed 37% duty cycle.
Wall Adapter Power Supply
For applications where an auxiliary power
source, such as a wall adapter, is used to
power the device, the MP8030 PD features wall
power adapter detection. Once the adapter
voltage (VADP) exceeds about 8.3V, the MP8030
PD enables wall adapter detection.
The resistor divider connected from VADP to
AUX can detect the adapter status. Once the
AUX voltage exceeds the internal reference
voltage, the MP8030 PD switches the power
source from the PSE to the adapter if the
adapter has higher priority.
GATE2 drives the external N-channel MOSFET
and provides a smooth switch between the PSE
and auxiliary wall adapter with less power loss
compared to a traditional diode input. After the
adapter supply is enabled, the PG signal is
pulled high, the TYP1/TYP2 pins output low,
and the BT pin stays high.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
When PRI is high, setting AUX high disables
the DET, CLS, and maintain power signature
functions. When PRI is low, setting AUX high
cannot disable the DET, CLS, and maintain
power signature functions.
If an adapter has a higher priority and replaces
the PSE power supply, BT and TYP1/2 are
updated once the AUX and ADP_UV signals
are working. If the PSE has a higher priority and
replaces the adapter supply, the MP8030 PD
changes the BT and TYP1/2 statuses to Hi-Z. If
PSE UVLO occurs, the statuses change to
indicate the latest PSE power type after inrush
is complete and the 90ms timer has finished.
Power Priority
The adapter is available when both AUX and
VADP exceed their UVLO thresholds. The
MP8030 PD can source a current from the
adapter or PSE if both the adapter and PSE are
connected. This is determined by the PRI and
AUX pin settings.
The PRI pin is internally pulled up to the
internal VCC. If the PRI pin is floating (the
adapter has higher priority) and VADP/AUX
exceed their UVLO thresholds, the MP8030 PD
disables the PSE power supply, and enables
the adapter power source. If AUX is below its
falling threshold, the MP8030 PD supplies
power via the PSE, even PRI pin is floating.
If the PRI pin is connected to GND, PSE has
the higher priority. Regardless of the AUX
signal, PSE outputs power, unless VDD is below
its UVLO threshold.
If PSE has a higher priority and the adapter is
connected before PSE plug-in, a reverse block
MOSFET (QREV) must be added to reversely
block the power from the adapter during PoE
detection and classification (see Figure 4). At
the same time, the output downstream DC/DC
controller should lower the power rating so that
the inrush current charges the MP8030 bus
capacitor (CBUS). If CBUS is not charged quickly,
the current limit may not be met, and the device
may fail to start up.
MP8030 Rev. 1.0
1/31/2022
QADP
From
Adapter
From
PSE
QPSE
VOUT
QREV
RSENSE
CBUS
RADP1
VADP GATE2
GATE1
AUX
SRC
RAPD2
SENSE
VDD
MP8030
PRI
Figure 4: Reverse Block Solution
DC/DC CONTROLLER
Start-Up and Power Supply
The MP8030 DC/DC controller features a highvoltage internal start-up circuit. When the
voltage between AVIN and GND exceeds 5.5V,
the capacitor at VCC is charged through the
internal LDO. Normally VCC is regulated to 8.5V
(if AVIN is high enough), and the VCC UVLO
threshold is typically 5.7V. In addition to VCC
UVLO, the DC/DC controller has an EN UVLO
threshold that is typically 2V. When VCC
exceeds 5.7V and the EN pin is high, the
DC/DC controller starts working.
VCC can be powered from the transformer
auxiliary winding to save IC power loss after the
DC/DC controller starts switching. The auxiliary
power exceeds the VCC regulation voltage to
override the internal LDO. There is one internal
reverse blocking circuit, which means that VCC
can exceed AVIN if VCC has biased power. The
VCC power should stay below 16V due to the
pin’s voltage rating.
If AVIN is below 8.5V and VCC cannot be
regulated to 8.5V, the internal high-voltage VCC
LDO has a 1.5V voltage drop. This means the
DC/DC controller can work when the input is as
low as 8V.
Enable (EN) Control
The EN pin enables and disables the MP8030
DC/DC controller. When the EN voltage
exceeds 1V, the controller starts up some of the
internal circuits. This is called micro-power
mode. If the EN voltage exceeds the turn-on
threshold (2V), the controller enables all
functions and starts the GATE/SYNC driver
signal. The GATE/SYNC signal can be disabled
when the EN voltage drops to about 1.8V, but
micro-power mode is disabled only after the EN
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
voltage falls below 0.4V. After shutdown, the
controller sinks a current (typically less than
1µA) from the input power.
The MODE pin can set the device to PSR or
SSR mode, and it can also configure the dead
time between the GATE and SYNC pins.
One internal Zener diode on the EN pin clamps
the EN voltage when the voltage divider
exceeds 6.5V. Use an external pull-up resistor
and ensure that the Zener diode is clamped to
have a current below 0.4mA flowing into EN.
The MODE pin detection current lasts about
200µs. Generally, it is sufficient to place one
resistor from MODE to GND. In a noisy
environment, the device may require a filtering
capacitor placed from MODE to GND. The
capacitance should be below 100pF so that the
MODE pin voltage can rise to a steady state
before the DC/DC controller detects VMODE.
Work Mode Detection
Once enabled, the DC/DC controller outputs a
40µA current to the MODE pin to detect the
resistor setting. If the MODE pin voltage
exceeds 2.2V, the DC/DC controller works in
primary-side regulation (PSR) mode, and the
internal EA is enabled. If the MODE pin is
connected to GND through a resistor, the
DC/DC controller works in secondary-side
regulation (SSR) mode, and the internal EA is
disabled. Meanwhile, COMP is pulled up to the
internal 5V power source through a 10kΩ
resistor (see Table 6).
Table 6: MODE Pin Configurations
MODE to GND
Resistance (kΩ)
Typ
Min
Max
(1%)
Work
Mode
Dead Time
(ns)
0
7.32
16
32.4
64.9
SSR
SSR
SSR
SSR
PSR
100
150
200
300
150
0
7.5
16.9
32.4
Float
3.3
8.2
18.7
33
Float
In PSR mode, the VOUT feedback signal is
detected by auxiliary winding from the FB pin,
and the DC/DC controller reduces the
frequency accordingly, but the frequency stays
above 30kHz under light loads. In SSR mode,
the VOUT feedback signal is detected through
the COMP pin, and the DC/DC controller
maintains a fixed frequency. Meanwhile, the
peak current can be regulated via the COMP
voltage until power save mode (PSM) is
triggered.
After the DC/DC controller is enabled, the
device does not start switching for 500µs. The
mode,
dead
time,
dither,
and
VOUT
compensation settings can be detected by the
DC/DC controller during this period.
MP8030 Rev. 1.0
1/31/2022
PWM Operation
The MP8030 DC/DC controller can be set in
flyback and forward topologies. In a flyback
topology, the external N-channel MOSFET
turns on at the beginning of each cycle, forcing
the current in the transformer to increase. The
current through the MOSFET can be sensed.
When the sum of the current-sense (CS) signal
and the slope compensation signal rises above
the voltage set by the COMP pin, the external
MOSFET turns off. The transformer current
then transmits energy from primary-side
winding to secondary-side winding, and the
output capacitor is charged through the
Schottky diode.
The transformer primary-side current is
controlled by the COMP voltage, which itself is
controlled by the output feedback voltage. Thus,
the output voltage controls the transformer
current to satisfy the load. In forward topologies,
the energy is transferred from primary to
secondary winding when the primary-side Nchannel MOSFET is turned on, and the
primary-side peak current is controlled by the
COMP voltage. The COMP voltage is controlled
by the external TL431 and optocoupler
feedback.
Voltage Control
There are multiple methods to control the
voltage. These methods are described in
greater detail below.
Primary-Side Regulation (PSR) Mode
Unlike traditional flybacks with opto-isolator
feedback, the MP8030 DC/DC controller can
detect the auxiliary winding voltage from the FB
pin during the secondary-side output diode
conduction period.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
Assume that the secondary winding is the
master, and the auxiliary winding is the slave.
When the secondary-side diode conducts, the
FB voltage can be calculated with Equation (1):
VFB =
NA
RFBL
(VOUT + VDOF )
NS
RFBH + RFBL
(1)
Where VDOF is the output diode forward-drop
voltage, VOUT is the output voltage, NA and NS
are the turns of the auxiliary winding and the
secondary-side output winding, respectively,
and RFBH and RFBL are the resistor dividers for
FB sampling.
Figure 5 shows the discontinuous conduction
mode (DCM) condition for FB sampling.
tCON
VSW
VIN
Blank Time
FB Sample
FB Sample
Blank Time
VFB
>0.7µs
IPEAK
IPRI
ISEC
Figure 5: DCM Condition FB Sample
Figure 6 shows the continuous conduction
mode (CCM) condition for FB sampling.
tCON
VSW
VIN
Blank Time
FB Sample
Next Clock
Blank Time
FB Sample
VFB
IPRI
ISEC
Figure 6: CCM Condition FB Sample
The DC/DC controller regulates the primaryside MOSFET switching to keep the VCS current
signal above 36mV (typically), and starts
sampling the auxiliary winding voltage after the
power MOSFET turns off. A 300ns blanking
MP8030 Rev. 1.0
1/31/2022
time is added to prevent spike ringing due to
the leakage inductance. To guarantee that
there is a sufficiently long FB sample period,
the output diode current conduction time (tCON)
under light loads (before the diode current
drops to 0A in each cycle) should be longer
than 600ns. Generally, design the transformer
and insure that tCON is longer than 700ns and
VCS_PK = 33mV. The DC/DC controller GATE
signal also provides a 1.2µs minimum off time,
though it is limited by a maximum 70% duty
cycle. This guarantees that there is a sufficient
FB sample time when the DC/DC controller
works with a high duty cycle.
During the FB sense period, the FB signal is
sent into the negative input of the EA, and this
value is held after the sense window elapses.
The EA output is generated on the COMP pin
and controls the transformer peak current to
match the output regulation requirement.
Secondary-Side Regulation (SSR) Mode
The MP8030 DC/DC controller can also be set
for traditional SSR mode. In SSR mode, the
VOUT signal is fed back to the COMP pin
through one optocoupler. All the PSR FB
voltage detection functions are disabled, and
FB should be connected to GND.
Under light loads, the DC/DC controller
maintains a fixed frequency. In SSR mode, the
peak current drops low following the COMP
voltage, until the PSM threshold is triggered.
The 36mV minimum current limit does not work
in SSR mode.
In SSR mode, the DC/DC controller can support
both flyback and forward topologies, while the
device can only support a flyback topology in
PSR mode.
Output Voltage Compensation
In PSR mode, the auxiliary winding waveform
reflects the secondary-side winding voltage, but
output voltage (VOUT) differs from the output
winding voltage due to output diode voltage
drop, as well as power winding resistance. The
dropout voltage varies when the conducted
current changes.
The resistance from the CS pin to GND can set
the compensation gain of the dropout voltage
when the current varies. The current-sense
signal is filtered internally, and then controls the
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
current sinking from the FB pin based on the
average voltage from the CS pin. There are 3
types of different current gains, from the
average CS voltage to the FB sinking current
(see Table 7). The FB sinking current leads to a
voltage drop on the FB high-side feedback
resistor so that it compensates VOUT (see Figure
7).
From AUX
Winding
VIN
IREG is set by VSENSE and
RREG+RSENSE
EA
+
VREF
RFBL
-
RFBH
COMP
GATE
Current
Mirror
+
CS
-
RREG
Rcs
Figure 7: Output Voltage Compensation
In SSR mode, this voltage compensation
function is disabled.
Frequency Dithering
The DC/DC controller integrates one frequency
dithering circuit to minimize EMI emissions.
During steady state, the frequency is fixed
internally, but frequency dithering circuit is
added to the configured frequency with 1.5kHz
modulation. In PSR mode, the frequency
dithering is fixed at ±6% of the switching
frequency. In SSR mode, the frequency
dithering can be configured to be ±3%, ±6%, or
±9%, based on the resistor connected from the
CS pin to GND.
Table 7 lists the dithering and
compensation configuration options.
VOUT
Table 7: CS Pin Configurations
Min
Typ
(1%)
Max
Dither
Range
(kHz)
IFB / VCS
Ratio
(uA/mV)
SSR
Mode
Dither
Range
(kHz)
0
3
6.2
12.7
24.9
0
3.3
6.8
12.7
25.5
1.3
3.6
7.5
13
28
0
±15
±15
±15
±15
0
0.054
0.108
0.216
0
0
±7.5
±15
±22.5
±22.5
CS to GND
Resistance (kΩ)
PSR Mode
The CS pin detection current lasts about 200µs
after start-up. Generally, it is sufficient to
connect a resistor between the CS and GND
MP8030 Rev. 1.0
1/31/2022
pins. In noisy environments, a capacitor may be
required between CS and GND to provide
filtering.
Current Sense and Over-Current Protection
(OCP)
The MP8030 DC/DC controller is a peak current
mode flyback/forward controller. The current
through the external MOSFET can be sensed
through a sensing resistor, which is connected
in series with the MOSFET’s source. The
sensed voltage on the CS pin is then amplified
and fed to the high-speed current comparator
for current control mode. The current
comparator takes this sensed voltage (plus the
slope compensation) as one of its inputs, then
compares it with the COMP voltage. When the
amplified current signal exceeds the COMP
voltage, the comparator outputs low, turning off
the power MOSFET.
If the voltage on the CS pin exceeds the current
limit threshold voltage (typically 160mV), the
DC/DC controller turns off the GATE output for
that cycle until the internal oscillator starts the
next cycle and senses the current again. The
DC/DC controller limits the current of the
MOSFET cycle-by-cycle.
Error Amplifier (EA)
In PSR mode, the DC/DC controller senses the
FB voltage during the flyback period with an FB
signal pulse. Then the FB signal is held and fed
to the error amplifier (EA). The EA regulates the
COMP voltage based on the FB signal. The
COMP voltage controls the transformer’s peak
current to regulate the output voltage.
In SSR mode, the internal EA is disabled, and
the COMP pin is pulled up by an internal
resistor. The external optocoupler can be
connected to the COMP pin for the VOUT signal
feedback.
Light-Load Control
Under light-load conditions in PSR mode, the
COMP voltage decreases to regulate the lower
transformer peak current. If the sensed peak
current signal is below 36mV, the DC/DC
controller does not decrease the transformer
current and it decreases the frequency. As a
result, the transferred energy decreases and
the output voltage is regulated.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
The DC/DC controller limits the minimum
frequency above 30kHz under light loads in
PSR mode. This can help detect VOUT with a
minimum frequency and prevent audible noise.
This minimum frequency requires a load to
maintain VOUT; otherwise, VOUT can rise and
trigger over-voltage-protection (OVP).
If the peak current cannot be limited by the
160mV CS voltage in every cycle due to
minimum gate on time, the current may run
away and the transformer may saturate. If the
monitored CS voltage reaches 300mV, the part
turns off GATE and initiates hiccup protection
immediately with a 340ms off time.
Under light loads in SSR mode, the DC/DC
controller maintains a fixed frequency and
COMP continues to drop until it reaches the
PSM threshold.
If the short circuit is removed, VOUT recovers
after the next restart cycle with a 340ms delay.
Over-Voltage Protection (OVP)
The DC/DC controller features OVP. If the
voltage at FB exceeds 125% of VREF, the
DC/DC controller shuts off the gate driving
signal and enters hiccup mode immediately.
The DC/DC controller restarts after 340ms and
resumes normal operation if the fault is
removed.
To avoid the mistriggering due to the oscillation
of the leakage inductance and the parasitic
capacitance, OVP sampling has a blanking time.
Overload Protection (OLP)
The DC/DC controller limits the peak current
cycle-by-cycle under over-current protection
(OCP) conditions. If the load continues
increasing after triggering OCP, VOUT decreases
and the peak current triggers OCP every cycle.
The DC/DC controller sets overload detection
by monitoring the CS pin voltage. Once the
internal soft start finishes, overload protection
(OLP) is enabled. If an OCP signal is detected
and lasts for longer than 4.8ms, the DC/DC
controller turns off the GATE driver. After a
340ms delay, the DC/DC controller restarts with
a new start-up cycle. During OLP, a one-shot
timer is activated for 50µs after one OCP pulse.
That means if there is one OCP pulse in a 50µs
period, the DC/DC controller registers this as an
OCP condition. If this condition is removed
within 4.75ms, the DC/DC controller returns to
normal operation.
Short-Circuit Protection (SCP)
When the output is shorted to ground, the part
works in OCP mode and the current is limited
cycle-by-cycle. In this scenario the part may
trigger OLP.
MP8030 Rev. 1.0
1/31/2022
Soft Start (SS)
The DC/DC controller provides soft start (SS)
by charging an internal capacitor with a current
source. During soft start, the SS signal controls
the voltage of the internal capacitor and ramps
up slowly. The SS capacitor is discharged
completely in the event of a commanded
shutdown, thermal shutdown, or a protection.
In PSR mode, the SS signal clamps the FB
reference voltage. The FB reference’s soft-start
time is typically 15ms, with a voltage between
0V and 2V.
In SSR mode, the SS signal clamps the COMP
voltage until COMP rises up to match the
switching current. The SS signal continuously
ramps up with the same rate. Generally, COMP
takes about 20ms to ramp from 1.5V to 3.5V.
Minimum On Time
The transformer parasitic capacitance and gate
driver signal induce a current spike on the CS
resistor when the power switch turns on. The
DC/DC controller includes a 250ns leading
edge blanking period to avoid falsely
terminating the switching pulse. During this
blanking period, the current-sense comparator
is disabled, and the gate driver cannot switch
off.
Gate Driver
The DC/DC controller integrates one highcurrent gate driver for the primary-side Nchannel MOSFET. The high-current gate driver
provides a strong driving capability and benefits
for MOSFET selection. If the external MOFET’s
QG is low and the switching speed is low due to
EMI, it is recommended to have a minimum 5Ω
resistance.
The DC/DC controller also integrates one
SYNC driver pin, which can be used to turn the
second switch off when it is high, or turn the
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
second switch on when it is low. Figure 8 on
page 34 shows the phase and dead time
relationship between GATE and SYNC.
R
NP
0.7μs SENSE
NS
33mV
(2)
Where VDOF is the output rectifier diode’s
forward-drop voltage.
50%
GATE
tD
tD
SYNC 50%
Figure 8: GATE and SYNC Driver
If the IC turns off due to UVLO or a different
protection, both the GATE and SYNC pins
maintain a low voltage level.
Transformer Inductance Consideration
In PSR mode, the DC/DC controller samples
VOUT during the flyback time. The secondary
diode conduction time with a minimum peak
current (controlled by a 33mV minimum CS
limit) should be longer than 0.7µs. The
transformer inductance should also be
sufficiently high. The transformer’s primary
inductance can be calculated with Equation (2):
MP8030 Rev. 1.0
1/31/2022
LPRI (VOUT + VDOF )
In SSR mode, there is no limit for inductance,
but it is recommended to set the peak current
high enough to avoid triggering PSM logic if the
device is designed for CCM mode. This is
because PSM may result in a higher output
voltage ripple, especially in sync mode forward
topologies.
Over-Temperature Protection (OTP)
Thermal shutdown is implemented to prevent
the chip from thermal runaway. The MP8030
has a separate temperature monitoring circuit
for the PD and DC/DC power controller. The
two thermal protections do not affect one other.
Once the temperature drops below its recovery
threshold, the thermal shutdown condition is
removed, and the MP8030 is enabled.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
APPLICATION INFORMATION
Selecting a TVS Diode
To limit the input transient voltage within the
absolute maximum ratings, a TVS diode should
be placed across the rectified voltage (between
VDD and GND). It is recommended to use a
SMAJ58A or a diode with an equivalent
protection
voltage
for
general
indoor
applications. The outdoor transient levels (or
special
applications)
require
additional
protection.
Selecting the PD Input Capacitor
A 0.05μF to 0.12μF input bypass capacitor
must be placed from VDD to GND for IEEE
802.3bt standard specifications. A 0.1μF, 100V
ceramic capacitor is recommended.
Selecting the Classification Resistors (RCLSA
and RCLSB)
Connect a resistor from CLSA and CLSB to
GND to configure the classification current
according to the IEEE 802.3bt standard. The
assigned class power should correspond to the
maximum average power drawn by the PD
during operation. To select RCLSA and RCLSB,
see Table 1 on page 25.
Wall Power Adapter Detection Circuit
The MP8030 PD features wall power adapter
detection. Once the input voltage (between
VADP and GND) exceeds about 8.3V, the PD
enables wall adapter detection. Then the
resistor divider from VADP to the AUX pin can
configure the threshold to switch from the PoE
to an adapter (see Figure 9).
From
Adapter
RADP1
VADP
AUX
RADP2
MP8030
Figure 9: Wall Adapter Threshold Setting
PG Pin Setting
The PG pin is an active high, open-drain output
that requires an external pull-up resistor. The
PG pin’s maximum sinking current should be
limited below 3mA, so a 20kΩ to 100kΩ pull-up
resistor should be place between SRC and PG.
Connect PG to the DC/DC controller’s
MP8030 Rev. 1.0
1/31/2022
downstream EN pin to enable the downstream
DC/DC converter.
PG is in high impedance if all of the following
conditions are met:
•
The steady current limit changes, which
means the inrush period is complete.
•
tDELAY (about 90ms) from UVLO is complete.
Then wall power adapter is detected on AUX,
and VADP exceeds its UVLO threshold.
BT, TYP1, TYP2 Indicator Connection
The BT, TYP1, and TYP2 pins are active low,
open-drain outputs that indicate the PSE type
or the presence of a wall adapter. Optocouplers
can interface these pins to circuitry on the
secondary side of the converter. Design the
optocoupler interface for the BT, TYP1, and
TYP2 signals (see Figure 10).
VDD
RBTT
VOUT
RBTT_OUT
VBTT_OUT
BT
or TYP1
or TYP2
Figure 10: BT, TYP1, and TYP2 Interface
BT, TYP1, and TYP2 should have maximum
sinking currents at 3mA, and RBTT should
exceed 20kΩ to match the maximum 57V input.
The BT, TYP1, and TYP2 devices each light
separate LEDs. These three LEDs indicate the
PSE type. When lighting an LED from VDD to
BT/TYP1/TYP2, the resistance can be higher to
match the LED’s maximum current and reduce
power loss.
Configurable Current Limit
After the MP8030’s VDD exceeds its UVLO
threshold, the ILIM pin sources a current that
detects the configurable current limit. By
connecting ILIM to GND through a resistor (or
shorting ILIM to GND), the MP8030’s current
limit can be configured (see Table 2 on page
26).
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
The MP8030 PD also has an inrush current limit
function after start-up. This limit is about 1/7 of
the steady state current limit.
Selecting the PoE Power MOSFET
The MP8030 PD internal hot-swap MOSFET
has a maximum 1.6A current limit. For type 1–3
PDs (≤51W), the internal hot-swap MOSFET
can support the application. For type 4 PDs
(>51W), an external MOSFET must be placed
in parallel with the internal hot-swap MOSFET.
The GATE1 pin can drive one external Nchannel MOSFET. The MOSFET should be
selected to meet the following specifications:
•
•
•
•
using the same guidelines for the
MOSFET.
Output Voltage Setting
For the MP8030 DC/DC controller, there are
two feedback modes (PSR and SSR).
In PSR mode, the converter detects the
auxiliary winding voltage from the FB pin. RFBH
and RFBL comprise the resistor divider used for
feedback sampling (see Figure 11).
GND
NA
FB
The voltage rating should be 100V at
minimum
for
high-voltage
surge
environments.
On resistance RDS(ON): RDS(ON) should be
below 200mΩ for power dissipation
considerations and for light-load shutdown
functions.
A
100mΩ
RDS(ON)
is
recommended.
Gate charge (QG): QG is recommended to
be as small as possible to satisfy faster
response times under overload conditions. It
is recommended for QG to be below 15nC
(VGATE = 4.5V).
The gate threshold voltage should be below
4V to fully drive the GATE1 and GATE2
voltages.
SENSE Pin Setting
The external parallel MOSFET current limit is
configured by a resistor (RSENSE) between the
VDD and SENSE pins. It is recommended for
RSENSE to be 18mΩ. The total current limit can
be calculated with Equation (3):
IIN _ LIM = IINNER +
26mV
RSENSE
(3)
PSE
RFBH
RFBL
Figure 11: Feedback in PSR mode
When the primary-side power MOSFET turns
off, the auxiliary winding voltage is proportional
to the output winding. VOUT can be estimated
with Equation (4):
VOUT =
VREF (RFBH + RFBL ) NS
− VDOF (4)
RFBL
NA
Where NS is transformer’s secondary-side
winding turns, NA is transformer’s auxiliary
winding turns, VDOF is the output rectifier diode’s
forward-drop voltage, and VREF is the reference
voltage on the FB pin.
When the main power MOSFET turns on, the
auxiliary winding voltage is negative, and the
FB voltage is limited at about -0.7V. The current
flowing out of the FB pin can be estimated with
Equation (5):
IFB =
1
RFBH
(
VIN NA
− 0.7)
NP
(5)
Where IIN_LIM is the MP8030 PD total current
limit, and IINNER is the MP8030 PD internal hotswap MOSFET current limit. When the external
MOSFET is connected, it is recommended to
set IINNER to 0.9A.
RFBH should be high enough to limit the FB
negative current below 1mA. However, due to
FB parasitic capacitance, RFBH should be not
too high. It is recommended for RFBH to be
between 49.9kΩ and 100kΩ.
Selecting the Adapter’s MOSFET
The MP8030 PD’s GATE2 pin is designed to
drive one external N-channel MOSFET for the
adapter supply. Select the adapter MOSFET
In SSR mode, the output voltage is set by an
external TL431 regulator. If the TL431’s
reference voltage is 2.5V, and the expected
output voltage is 12V, then the upper and lower
MP8030 Rev. 1.0
1/31/2022
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
resistor divider ratio is 3.8. Then TL431
generates an amplified signal and controls the
MP8030 DC/DC controller’s COMP pin through
an optocoupler, such as PC357. COMP
controls the current, and then VOUT is regulated
based on the feedback signal.
Work Mode Setting
Once enabled, the MP8030 DC/DC controller
outputs a 40µA current to the MODE pin to
detect the MODE resistance. If the MODE pin’s
voltage exceeds 2.2V, the MP8030 DC/DC
controller works in PSR mode or SSR mode.
The MODE pin can also configure the dead
time between the GATE and SYNC pins (see
Table 6 on page 30).
VCC Power Supply Setting
The VCC voltage is regulated by the internal
LDO from AVIN. VCC is typically regulated to
8.5V. It is recommended to place a decoupling
capacitor between VCC and GND
In flyback mode, the VCC capacitor is
recommended to be 1µF at minimum. VCC can
also be powered from transformer auxiliary
winding to reduce high-voltage LDO power loss
(se Figure 12).
GND
RVCC DVCC
CVCC
Figure 12: Flyback VCC from NA Winding
The auxiliary winding supply voltage can be
calculated with Equation (6):
NA
(VOUT + VDOF ) − VDVCCF
NS
VCC
LVCC
NA
DVCC
CVCC
Figure 13: Forward VCC from NA Winding
The auxiliary winding supply voltage can be
calculated with Equation (7):
VCC =
NA
VOUT
NS
(7)
VCC should be below 16V.
VOUT
Compensation
and
Frequency
Dithering Setting
The CS pin can be used to set VOUT
compensation as well as the frequency
dithering function. Once enabled, the MP8030
DC/DC controller outputs a 100µA current to
the CS pin to detect the CS resistance. The
MP8030 DC/DC controller determines the
compensation type and the frequency dithering
type based on the resistance (see Table 7 on
page 32).
The VOUT compensation function is only enabled
in PSR mode.
NA
VCC
VCC =
GND
(6)
Where VDVCCF is the diode (DVCC) voltage drop
from auxiliary winding.
In forward mode, the VCC capacitor is
recommend to be 4.7µF at minimum. VCC can
also be powered from transformer auxiliary
winding (see Figure 13).
Current-Sense Resistor Setting
The MP8030 DC/DC controller is a peak current
mode flyback/forward controller. The current
through the external MOSFET can be sensed
through a current-sense resistor. If the sensed
voltage on the CS pin exceeds the current limit
threshold voltage (typically 160mV), the
MP8030 DC/DC controller turns off the GATE
output for that cycle.
To avoid reaching the current limit, the voltage
across the current-sense resistor (RCS) should
be less than 80% of the current limit voltage
(about 160mV). RCS can be estimated with
Equation (8):
RCS =
0.8 160mV
IPEAK
(8)
Where IPEAK is the primary-side peak current.
MP8030 Rev. 1.0
1/31/2022
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
Selecting the Power MOSFET
The MP8030 DC/DC controller is capable of
driving a wide variety of N-channel power
MOSFETS. The critical parameters when
selecting a MOSFET are the maximum drain-tosource voltage (VDS(MAX)), maximum current
(ID(MAX)), on resistance (RDS(ON)), total gate
charge (QG), and turn-on threshold (VTH).
In flyback applications, the off-state voltage
across the MOSFET (which determines when
the MOSFET shuts down) can be calculated
with Equation (9):
VMOSFET = VIN + N VOUT
(9)
Considering the voltage spike when the device
turns off, VDS(MAX) should be greater than 1.5
times VMOSFET.
In forward applications, the off-state voltage
across the MOSFET is calculated with:
VMOSFET
D VIN
=
+ VIN
1− D
(10)
Where D is the duty cycle. Generally, the
maximum duty cycle is limited at 70%.
The maximum current through the power
MOSFET occurs when the input voltage is at its
minimum and the output power is at its
maximum. The current rating of the MOSFET
should be greater than 1.5 times IRMS.
The on resistance of the MOSFET determines
the conduction loss. This resistance should be
low.
QG determines the commutation time. A high
QG leads to high switching loss, while a low QG
may cause a fast turn-on/off speed that affects
the spike and kick.
Consider the turn-on threshold voltage (VTH).
GATE is powered by VCC, so VTH must be below
VCC.
Selecting the Flyback Transformer
The transformer in a flyback converter
determines the converter’s duty cycle, peak
current, efficiency, MOSFET, and output diode
rating. A good transformer should consider the
winding
ratio,
primary-side
inductance,
saturation current, leakage inductance, current
rating, and core selection.
MP8030 Rev. 1.0
1/31/2022
The transformer winding ratio determines the
duty cycle. Calculate the duty cycle with
Equation (11):
D=
N VOUT
N VOUT + VIN
(11)
Where N is the transformer primary winding to
output winding ratio, and D is the duty cycle.
Typically, a duty cycle of about 45% is
recommended for most applications.
The primary-side inductance affects the input
current ripple ratio factor. A high inductance
results in a large transformer size and high cost;
a low inductance results in high switching peak
current and RMS current, which reduces
efficiency. Choose a primary-side inductance to
make the current ripple ratio factor about 30%
to 50% of the input current. Estimate the
primary-side inductance with Equation (12):
LP =
VIN D2
2 n IIN fSW
(12)
Where n is the current ripple ratio, IIN is the
input current, and LP is the primary inductance.
Calculate LP based on the minimum input
voltage condition.
The transformer should have a high saturation
current to support the switching peak current;
otherwise,
the
transformer
inductance
decreases sharply. The CS resistor can be
used to limit the switching peak current.
The energy stored in the leakage inductance
cannot couple to the secondary side, causing a
high spike when the MOSFET turns off. This
decreases efficiency and increases MOSFET
stress. Normally, the transformer leakage
inductance can be controlled below 3% of the
transformer inductance.
The current rating counts the maximum RMS
current, which flows through each winding. The
current density should be controlled; otherwise,
it can cause a high resistive power loss.
Diode Conduction Time Setting (For PSR
Flyback)
In PSR mode, the MP8030 DC/DC controller
starts sampling the auxiliary winding voltage
after the primary power MOSFET turns off.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
A blanking time is added in the MP8030 DC/DC
controller to prevent spike ringing due to the
leakage inductance. To guarantee a sufficiently
long FB sample period, the output diode current
conduction time (tCON) under light loads should
be longer than 600ns. Design the transformer
and ensure that tCON is longer than 700ns when
VCS_PK = 33mV. This relationship can be
calculated with Equation (13):
33mV LP NS
700ns
RCS NP (VOUT + VDOF )
(13)
Where VDOF is the output diode’s forward-drop
voltage.
Selecting the RCD Snubber for Flyback
Applications
The transformer leakage inductance causes
spikes and excessive ringing on the MOSFET
drain’s voltage waveform. An RCD snubber
circuit limits the MOSFET voltage spike (see
Figure 14).
RSN
NP
PGND
Figure 14: RCD Snubber Circuit
The power dissipation in the snubber circuit can
be estimated with Equation (14):
PSN =
1
LK IPEAK 2 fSW
2
RSN
VDIODE =
VIN
+ VOUT
N
(17)
The average current rating must exceed the
maximum expected load current, and the peak
current rating must exceed the output winding
peak current.
The transformer winding ratio determines the
duty cycle (D). D can be estimated with
Equation (18):
D=
(15)
Where VSN is the expected snubber voltage on
the snubber capacitor (CSN).
CSN can be designed to achieve an appropriate
voltage ripple on the snubber, estimated with
Equation (16):
MP8030 Rev. 1.0
1/31/2022
Selecting Output Diode for Flyback
Applications
The flyback output rectifier diode supplies
current to the output capacitor when the
primary-side MOSFET is off. A Schottky diode
reduces losses due to the diode’s forward
voltage and recovery time. The diode should be
rated for a reverse voltage 1.5 times greater
than VDIODE. VDIODE can be calculated with
Equation (17):
(14)
Where LK is the leakage inductance and IPEAK is
the peak switching current. Since RSN
consumes the leakage inductance power loss,
RSN can be calculated with Equation (15)
VSN2
=
PSN
Generally, a 15% ripple is recommended.
Selecting the Forward Transformer
The forward transformer transfers energy to
output when the power MOSFET turns on. This
transformer’s key parameters are the winding
ratio, primary winding turns, current rating, and
core selection.
AGND
MOSFET
GATE
(16)
NS
DSN
MP8030
VSN
RSN CSN fSW
It is recommended to use an RC snubber circuit
for the output diode.
T1
CSN
VSN =
VOUT N
VIN
(18)
Where N is the transformer’s primary winding to
output winding ratio. A duty cycle of about 45%
is recommended for most applications.
When the power MOSFET turns on, the
transformer transfers energy to the output. At
the same time, the input voltage generates a
primary-side current in the transformer. There
should be sufficient primary winding to ensure
that the transformer does not saturate. The
peak exciting current is calculated with
Equation (19):
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
IEXC =
VOUT N
2 LP fSW
(19)
Where IEXC is the peak primary-side current,
and LP is the primary inductance. Use IEXC to
calculate the primary winding. There should be
sufficient margins for extreme conditions, such
as load transient response and OCP.
The current rating is based on the maximum
RMS current, which flows through each
winding. The current density should be
controlled; otherwise, it can cause a high
resistive power loss.
Selecting the Forward SYNC MOSFET
The MP8030 DC/DC controller supports activeclamp forward applications. The active clamp Pchannel MOSFET must have same maximum
voltage as the main switch power MOSFET,
and its maximum current should exceed the
peak primary-side current and RMS current.
Selecting the Forward Output MOSFET
The forward output MOSFET requires two
diodes to conduct the current. If higher
efficiency is required, the diodes must be
replaced by MOSFETs (see Figure 15).
L
QF
NS
VOUT
COUT
QR
Figure 15: Forward Output MOSFET
The MOSFET voltage rating should exceed the
maximum VDS voltage. The maximum VDS
voltage for QR (VR) can be calculated with
Equation (20):
VR =
D VIN
N (1 − D)
(20)
Where N is the transformer primary winding to
output winding ratio, and D is the primary
MOSFET duty cycle. A margin is typically
required.
The maximum VDS voltage for QF (VF) can be
estimated with Equation (21):
VF =
MP8030 Rev. 1.0
1/31/2022
VIN
N
(21)
The MOSFET current rating should exceed its
maximum RMS current and peak current. The
QR RMS current can be estimated with
Equation (22)
IR = IOUT D 1 +
1 IPP 2
(
)
3 IOUT
(22)
Where IPP is the L peak-to-peak current.
The QF RMS current can be calculated with
Equation (23):
IF = IOUT 1 − D 1 +
1 IPP 2
(
)
3 IOUT
(23)
The QR MOSFET’s gate driving voltage is equal
to VF, and the QF MOSFET’s gate driving
voltage is equal to VR. If the driving voltage
exceeds the MOSFETs’ maximum gate voltage,
a clamp circuit is required. The MOSFET’s turnon resistance determines the conduction loss,
while QG determines the driver circuit loss.
These values should be low enough to increase
efficiency with a lower rising temperature.
Selecting the Forward Output Inductor
Optimized Performance with MPS Inductor
MPL-AY Series
A forward output inductor is required to supply
constant current to the output load while the
main power MOSFET turns on. A larger-value
inductor results in less ripple current and a
lower output voltage ripple. However, a largervalue inductor has a larger physical size, higher
series resistance, and lower saturation current.
A good rule for determining the inductance is to
allow the peak-to-peak ripple current in the
inductor to be approximately 30% to 50% of the
maximum output current. The inductance value
can be estimated with Equation (24):
L=
VOUT
V N
(1 − OUT
)
fSW IL
VIN
(24)
Where VOUT is the output voltage, VIN is the
input voltage, fSW is the switching frequency,
and ΔIL is the peak-to-peak inductor ripple
current. Choose an inductor that does not
saturate under the maximum inductor peak
current.
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
MPS inductors are optimized and tested for use
with our complete line of integrated circuits.
capacitors, the capacitance dominates the
output voltage ripple at the switching frequency.
Table
8
lists
our
power
inductor
recommendations. Select a part number based
on your design requirements.
In flyback mode, the output voltage ripple can
be calculated with Equation (27):
VOUT =
Table 8: Power Inductor Selection
Part Number
Inductor Value Manufacturer
MPL-AY
MPL-AY1265-2R2
1µH to 10µH
2.2μH
MPS
MPS
Visit MonolithicPower.com under Products >
Inductors for more information.
Selecting the Input Capacitor
An input capacitor is required to supply the AC
ripple current to the inductor while limiting noise
at the input source. A low-ESR capacitor is
required to minimize the noise at the IC.
Ceramic capacitors are recommended, though
tantalum or low-ESR electrolytic capacitors are
sufficient. For ceramic capacitors, the
capacitance dominates the input voltage ripple
at the switching frequency.
In flyback mode, the input voltage ripple can be
calculated with Equation (25):
VIN = IIN
VIN
fSW CIN (N VOUT + VIN )
(25)
Where ΔVIN is the input voltage ripple, IIN is the
input current, and CIN is the input capacitor.
In forward mode, the input voltage ripple can be
estimated with Equation (26):
V N
IIN
VIN =
(1 − OUT
)
fSW CIN
VIN
(26)
Note that this equation ignores the primary-side
current, which makes current ripple smaller.
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. For the best results, use ceramic
capacitors or low-ESR capacitors to minimize
the output voltage ripple. For ceramic
MP8030 Rev. 1.0
1/31/2022
N VOUT
I
OUT
(VIN + N VOUT ) fSW COUT
(27)
If the output voltage ripple is too high, a π filter
is required. Choose the inductor to be between
0.1μH to 0.47μH to achieve an optimal output
voltage ripple and system stability.
In forward mode, the output voltage ripple can
be estimated with Equation (28):
VOUT =
VOUT
V N
(1 − OUT
) (28)
8 fSW L COUT
VIN
2
Design Example
Table 9 is a forward design example following
the application guidelines for the specifications
below.
Table 9: Forward Design Example
PoE Input
VOUT
IOUT
41V to 57V
5V
14A
The detailed application schematic is shown in
Figure 19 on page 44. The typical performance
and circuit waveforms are shown in the Typical
Performance Characteristics section on page
19. For more device applications, refer to the
related evaluation board datasheet.
Table 9 is a flyback design example following
the application guidelines for the specifications
below.
Table 10: Flyback Design Example
PoE Input
VOUT
IOUT
41V to 57V
12V
6A
The detailed application schematic is shown in
Figure 20 on page 44. For more device
applications, refer to the related evaluation
board datasheet.
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41
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
PCB Layout Guidelines
An efficient PCB layout for the PoE front-end
and high-frequency switching power supply are
critical for stable operation. A suboptimal layout
may result in reduced performance, excessive
EMI, resistive loss, and system instability. For
the best results, refer to Figure 16, Figure 17
(on page 43), and Figure 18 (on page 43), and
follow the guidelines below.
4. The VCC capacitor must be placed close to
the VCC and GND pins for the best
decoupling.
The PD Interface Circuit
All component placements must follow the
power flow from RJ-45, the Ethernet
transformer, the diode bridges, the TVS diode
to 0.1μF capacitor, and the DC/DC converter’s
input bulk capacitor.
Figure 16 shows the recommended forward
layout, which is based on the Typical
Application section on page 2. For more details,
refer to the related evaluation board datasheet.
5. Route the COMP feedback trace far away
from noisy sources, such as the switching
node.
6. Use a single-point connection between
power GND and signal GND.
D2
R10
C6
Top Layer
Bottom Layer
Vias
L1
Q3
C5
T1
GND
Q5
VADP
Q2
R9
VDD
Q1
C2
D1
GND
VO
C4
C3
VOGND
U1
Q4
R7
R8
U3
R5
R4
R15
R6
2. Place the current-sense resistor (RSENSE) as
close to VDD pin as possible.
C1
R22
1. Ensure that all power connections are as
short as possible with wide traces.
C7
U2
3. Use a Kelvin connection between RSENSE
and the SENSE pin for an accurate current
limit.
4. Place the PoE input capacitor as close to
the VDD pin as possible.
5. Place the adapter’s input capacitor as close
to the VADP pin as possible.
6. Place the SRC capacitor as close to the
SRC pin as possible.
7. Place a wide copper plane and vias under
the MP8030, PoE power MOSFET and
adapter MOSFET to improve thermal
performance.
Forward Toplogy
1. Keep the input loop between the input
capacitor, transformer, MOSFET, CS
resistor, and GND plane as short as
possible for minimal noise and ringing.
2. Keep the active-clamp loop between the
input capacitor, transformer, C5, and Q3 as
short as possible for minimal noise and
ringing.
3. Keep the output high-frequency current loop
between the transformers, Q4, and Q5 as
short as possible .
MP8030 Rev. 1.0
1/31/2022
R29 R2 R1
Figure 16: Recommended PCB Layout for
Forward Topology
Flyback Topology
1. Keep the input loop between the input bulk
capacitor, transformer, MOSFET, CS
resistor, and GND plane as short as
possible for minimal noise and ringing.
2. Keep the output loop between the rectifier
MOSFET, output capacitor, and transformer
as short as possible.
3. The clamp loop circuit between DSN, CSN,
and the transformer should be as small as
possible.
4. The VCC capacitor must be placed close to
the VCC and GND pin for the best
decoupling.
5. Route the feedback trace far away from
noisy sources, such as the switching node.
6. Place the COMP components close to the
COMP pin.
7. Use a single-point connection between
power GND and signal GND.
Figure 17 on page 43 shows a recommended
flyback layout. For more details, refer to the
related evaluation board datasheet.
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42
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
T1
C16
R22
Q1
VOUT
D2
C2
VDD
C3
T1
C1
C16
R9
C7
R10
R7
R2
R1
GND
D2
VOGND
VOUT
VADP
GATE2
GATE1
SRC
PG
EN
AVIN
R5
R4
R15
C5
R8
Figure 17: Recommended PCB Layout for
Flyback Topology
R6
R15
AUX
SENSE
VDD
BT
TYP2
TYP1
R_MPS
ILIM
DUTY
PRI
U1
MP8030
CLSA
CLSB
R28
C28
R7
R8
R6
Q2
R12
D1
AUTOCLS
CO MP
MODE
GND
C4
2
C3
1
Q3
VADP
Q2
U1
2
R12
1
GND
Figure 18 shows the recommended schematic
for a flyback layout.
Q4
R9
C7
D1
Bottom Layer
Vias
R10
C1
VDD
Top Layer
Q3
VADP
Q4
C2
SYNC
VCC
C4
Q1
GATE
CS
FB
R22
R1
R4
R5
R28
R2
C28
C5
Figure 18: Recommended Flyback Layout
MP8030 Rev. 1.0
1/31/2022
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43
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
TYPICAL APPLICATION CIRCUITS
R12
Q6
Si2392
C1A
47µF
R9A
200kΩ
R9B
PGND
VSS
C31
200kΩ
25
16
23
SYNC
31
VCC
NS
6
NA
1
C4A
PGND
R18
R21
10Ω
19
VOGND
VOUT
R29 4.02kΩ
D4
PGND
C15
1µF
SPGND
1kΩ
U3
TLV431
C14
1000pF/2000V
R28
4.7nF
D9
BAV99
PGND
PGND
PGND
R1
61.9kΩ
C10
BAV70
C4B
1µF
3.3nF
U2A
PC357
R31
20K
1mH
R24
20kΩ
U2B
Optocoupler
C28
NC
PGND
SPGND
R22B
0.043Ω
VCC L4
100kΩ
PGND
41.2Ω
C2C
470µF
C29 1nF
PGND
R5
C2B
47µF
D8
8.2V
C27
GN D
MODE
R22A
0.043Ω
29
9
7
6
5
11
R50 10Ω
PGND
R23
PGND
220pF
FDMS86250
C32 6.8kΩ
10pF
PGND PGND
R4
28.7Ω
C2A
47µF
R19
10
FB
COMP
CLSB
GN D
CLSA
PRI
AUTOCLS
DUTY
4
Q1
2.4MΩ
ILIM
3
C30
470pF
Q4
BSC022N04LS
VCC
15
CS
VOUT
R51
10Ω
C13
D7
8.2V
PGND
GATE
R_MPS
2
Q9
MMBT3904
1kΩ
Q8
MMBT3904
7, 8, 9
EFD20
14
13
MP8030
VOUT
R26
4.7µF
U1
BT
TYP2
TYP1
1N4148W
1N4148W
5
PGND
PGND
8
20
21
C12
220pF
D5
12
VCC
AUX
R25
1kΩ
1, 2
R10
10kΩ
D2
1N4148
VADP
32
NP
C5B
100nF
47nF
Q3
SI2325
17
AVIN
VDD
MPL-AY1265-2R2
D6
100Ω
C5A
PGND
1uF
PGND
EN
SRC
PG
30
26
GATE2
GATE1
SENSE
28
PGND
5V/71W
L1
10, 11, 12
R49
C1C
2.2µF
C6
1µF
PGND
27
C1B
2.2µF
Q5
D1
SMAJ58A
0.018Ω
BSC022N04LS
C3
0.1µF
T1
3, 4
VDD
R2
20kΩ
SPGND
PGND
SPGND
Figure 19: Typical SSR Forward Application Circuit (VIN = 41V to 57V, VOUT = 5V, IOUT = 14A)
R12
VDD
D1
SMAJ58A
C3 0.018Ω
0.1µF
R9A
200kΩ
C31
1µF
R9B
PGND
PGND
R10A
C1A
C1B
C1C
47µF
2.2µF
2.2µF
R10B
15kΩ
15kΩ
200kΩ
EN
SENSE
VDD
NS2
820pF
R24
D2
SS1200
PGND
4.99kΩ
15nF
R25
10Ω
1N4148W
D7
Q5
MMBT3906
R26
680Ω
MMSZ4700
12V/6A
L1
0.22µH
Q4
BSC070N10NS5
C10 R27
PGND
SYNC
VCC
VADP
NA
C4A
NS1
VOUT
C2A
C2B
C2E
C2J
C2G
22µF
22µF
220µF
220µF
0.1µF
VCC
AUX
PGND
1µF PGND
U1
BT
TYP2
TYP1
AUTOCLS
0Ω
2MΩ
R19
MODE
COMP
PAD
C32
NC
CLSA
R18
VCC R21
Q1
FDMS86250
1nF
EFD25
SGND
4.99Ω
SGND
SGND
SGND
VOGND
CS
CLSB
R_MPS
ILIM
DUTY
PRI
GN D
GATE
MP8030
GN D
PGND
PGND
NP
C9
1N4148W
C8
D6
AVIN
PG
SRC
GATE1
GATE2
PGND
15Ω
C7
0.1µF
D5
R23
T1
Q6
Si2392
6.8kΩ
R22B
10pF
FB
R22A
0.047Ω
0.047Ω
PGND
PGND PGND
PGND
R1
24.9kΩ
PGND
PGND
R4
28.7Ω
R5
41.2Ω
PGND
R2
6.34kΩ
R28
6.8kΩ
R20
D4
VCC
C4B
100Ω
1N4148W
C14
1µF
PGND
C5
15nF
1nF/2000V
C28
1nF
PGND
PGND
PGND
SGND
PGND
Figure 20: Typical PSR Flyback Application Circuit (VIN = 41V to 57V, VOUT = 12V, IOUT = 6A)
MP8030 Rev. 1.0
1/31/2022
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44
MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
PACKAGE INFORMATION
QFN-32 (5mmx6mm)
PIN 1 ID
0.30x45°TYP.
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD
FLASH.
3) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP8030 Rev. 1.0
1/31/2022
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
CARRIER INFORMATION
Part Number
Package
Description
Quantity/
Reel
Quantity/
Tube
Quantity/
Tray
Reel
Diameter
Carrier
Tape
Width
Carrier
Tape
Pitch
MP8030GQJ-Z
QFN-32
(5mmx6mm)
5000
N/A
N/A
13in
12mm
8mm
MP8030 Rev. 1.0
1/31/2022
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MP8030 – 802.3AF/AT/BT DEVICE WITH FLYBACK/FORWARD CONTROLLER
REVISION HISTORY
Revision #
1.0
Revision Date
1/31/2022
Description
Initial Release
Pages Updated
-
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP8030 Rev. 1.0
1/31/2022
MonolithicPower.com
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