MP8046DF-LF-P

MP8046 28V, 5A Dual Channel Power Half-Bridge The Future of Analog IC Technology FEATURES DESCRIPTION The MP8046 is a configurable full-bridge or dual channel half-bridge that can be configured as the output stage of a Class-D audio amplifier. Each channel can be driven independently as stereo single ended audio amplifiers, or driven complementary in a bridge tied load (BTL) audio amplifier configuration. The MP8046 features a low current shutdown mode, standby mode, input under voltage protection, current limit, thermal shutdown and fault flag signal output. Both channels of the driver interface with standard logic signals. The MP8046 is available in a 20-pin TSSOP (with Exposed Pad) package. • • • • • • • • • • • ±5A Peak Current Output Up to 600kHz Switching Frequency Protected Integrated 165mΩ Power Switches 30ns Switch Dead Time All Switches Current Limited Internal Under Voltage Protection Internal Thermal Protection 2.4mA Operating Current Fault Output Flag Stereo Single Ended Output Power: 20W/Channel at 24V, 4Ω Load Bridge Tied Load Output Power: 40W at 24V, 8Ω Load APPLICATIONS • • • Class D Audio Drivers Full or Half-Bridge Regulators Motor Drivers DC-DC Switching “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VCC VDD + GND D2 1N4148 CN1 U1 1 2 PWM1 STBY 3 4 5 PWM2 NC VDR1 AGND1 BST1 PWM1 PGND1 STBY PWM2 OUT1 MP8046 VDD1 20 19 18 17 VCC D5 CN2 16 OUT1 FAULT SHDN 6 7 8 9 10 MP8046 Rev. 0.92 4/29/2010 FAULT NC SHDN VDD2 AGND2 OUT2 NC VDR2 PGND2 BST2 15 14 VCC OUT2 13 12 11 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 1 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE ORDERING INFORMATION Part Number* MP8046DF Package TSSOP20F Top Marking Free Air Temperature (TA) MP8046DF –40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP8046DF–Z). For RoHS compliant packaging, add suffix –LF (e.g. MP8046DF–LF–Z) PACKAGE REFERENCE TOP VIEW NC 1 20 VDR1 AGND1 2 19 BST1 PWM1 3 18 PGND1 STBY 4 17 OUT1 PWM2 5 16 VDD1 FAULT 6 15 NC SHDN 7 14 VDD2 AGND2 8 13 OUT2 NC 9 12 PGND2 VDR2 10 11 BST2 EXPOSED PAD ABSOLUTE MAXIMUM RATINGS (1) VDD1/2 Supply Voltage ............................... 31V OUT1/2 Pin Voltage ............ –0.3V to VDD + 0.3V OUT1/2 to BST1/2 .........................–0.3V to +6V Voltage at All Other Pins................–0.3V to +6V Continuous Power Dissipation (TA = +25°C) (2) ………………………………………………....3.1W Storage Temperature.............. –55°C to +150°C Junction Temperature.............................150°C Lead Temperature .................................260°C Recommended Operating Conditions (3) VDD1/2 Supply Voltage ...................7.5V to 28V Peak Output Current ......................5A Maximum Operating Junct. Temp (TJ)...... -40°C to +125°C MP8046 Rev. 0.92 4/29/2010 Thermal Resistance (4) θJA θJC TSSOP20F..............................40 ....... 6 .... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on approximately 1” square of 1 oz copper. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 2 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE ELECTRICAL CHARACTERISTICS VDD1 = VDD2 = 20V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Parameters Symbol Condition Min Typ Max Units VDD Operating Current ILOAD = 0A, PWM1 = PWM2 = 0V 2.4 2.6 mA VDD Shutdown Current VSHDN = 0V 5.0 15 µA VDD Operating Threshold, Low 5.7 VDD Operating Threshold, High 6.79 1.0 STBY Threshold, Low 1.0 SHDN Threshold, Low SHDN Threshold, High PWM1,2 Threshold, Low PWM1,2 Threshold, High PWM Input Bias Current 1.0 Dead Time (5) PWM to OUT Delay Time Rising PWM to OUT Delay Time Falling VDD = 7.5V, High-Side and LowSide VPWM = 5, Sinking VPWM = 0, Sourcing VPWM = 0 to 2V, 50% Duty Cycle VDD = 7.5V, VPWM = 2V, CBST = 100nF, fSW = 3.3kHz VPWM = 0V to 5V VPWM = 0V to 2V, High or Low Pulse IOUT= ±100mA VPWM = 0V to 5V VPWM = 5 to 0V Thermal Shutdown Temperature (5) TJ Rising, Hysteresis = 20°C OUT Current Limit (5) OUT Switching Frequency OUT Maximum Duty Cycle (6) OUT Rise/Fall Time (5) PWM Pulse Width V 7.2 1.2 1.87 STBY Threshold, High OUT On Resistance (5) 5.9 V V 2.2 1.2 V V 1.87 2.2 V 1.69 1.83 1 2.2 V V µA 0.165 Ω 5 5 A A MHz 0.6 99.5 % 10 ns 200 ns 30 46 47 150 55 55 ns ns ns °C Notes: 5) Not production tested. 6) OUT drives low for 1.5µs every 300µs to charge the BST to SW capacitor. MP8046 Rev. 0.92 4/29/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 3 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE PIN FUNCTIONS Pin # 1 2 3 4 5 Name Description NC No Connect. AGND1 Analog Ground 1. Driver Logic Input 1. Drive PWM1 with the signal that controls the MP8046 OUT1. Drive PWM PWM1 high to turn on the high side switch; drive PWM low to turn on the low-side switch. Standby Input. Default low (internal pull-down). If driven high, the output of drivers is STBY determined by the PWM1/2. If driven low, the output of both drivers is high impedance. Driver Logic Input 2. Drive PWM2 with the signal that controls the MP8046 OUT2. Drive PWM PWM2 high to turn on the high-side switch; drive PWM low to turn on the low-side switch. Fault Output. A low output at FAULT indicates that the MP8046 has detected an over temperature or over current condition. This output is open drain. 6 FAULT 7 SHDN Shutdown Input. When low, both channels will be shut off. AGND2 Analog Ground 2. NC No Connect. Gate Drive Supply Bypass 2. The voltage at VDR2 is supplied from an internal regulator from VDR2 VDD2. VDR2 powers the internal circuitry and internal MOSFET gate drive for the OUT2 stage. Bypass VDR2 to PGND with a 0.1μF to 10µF capacitor. Bootstrap Supply 2. BST2 powers the high-side gate of the OUT2 stage. Connect a 0.1μF or BST2 greater capacitor between BST2 and OUT2. PGND2 Power Ground 2. Connect the exposed pad on bottom side to the ground plane. Switched Output 2. Connect the output LC filter to OUT2. OUT2 is valid approximately 100µs OUT2 after VDD2 goes high. Power Supply Input 2. Connect VDD2 to the positive side of the input power supply. Bypass VDD2 VDD2 to PGND as close to the IC as possible. NC No Connect. Power Supply Input 1. Connect VDD1 to the positive side of the input power supply. Bypass VDD1 VDD1 to PGND as close to the IC as possible. Switched Output 1. Connect the output LC filter to OUT1. OUT1 is valid approximately 100µs OUT1 after VDD1 goes high. PGND1 Power Ground 1. Connect the exposed pad on bottom side to the ground plane. Bootstrap Supply 1. BST1 powers the high-side gate of the OUT1 stage. Connect a 0.1µF or BST1 greater capacitor between BST1 and OUT1. Gate Drive Supply Bypass 1. The voltage at VDR1 is supplied from an internal regulator from VDR1 VDD1. VDR1 powers the internal circuitry and internal MOSFET gate drive for the OUT1 stage. Bypass VDR1 to PGND with a 0.1µF to 10µF capacitor. 8 9 10 11 12 13 14 15 16 17 18 19 20 MP8046 Rev. 0.92 4/29/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 4 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE TYPICAL PERFORMANCE CHARACTERISTICS VDD1 = VDD2 = 20V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Normal Switch Waveform Short Circuit Negative Current Short Circuit Positive Current IL 5A/div. VSW 10V/div. IL 5A/div. VOUT1 10V/div. VSW 10V/div. VFAULT 2V/div. VOUT2 10V/div. VFAULT 2V/div. Input/Output Waveform Negative Pulse Input/Output Waveform Positive Pulse VOUT1 10V/div. VOUT1 10V/div. VPWM1 2V/div. VPWM1 2V/div. Output Rise-Time VOUT1 5V/div. 100ns/div. 100ns/div. 5ns/div. Output Fall-Time +5 100 +4 +3 1 f=1KHz 0.1 VOUT1 5V/div. +2 +1 0 -1 -2 -3 -4 0.01 5ns/div. MP8046 Rev. 0.92 4/29/2010 AMPLITUDE (dBr) THD+N (%) 10 0.01 0.1 1 POUT (W) 10 30 -5 10 100 1K 10K 20K FREQUENCY (Hz) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 5 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD1 = VDD2 = 20V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Start-up Shut-down VDD 10V/div. VPWM1 5V/div. IL 5A/div. VDD 10V/div. VOUT1 10V/div. VOUT1 10V/div. VSTBY 2V/div. VPWM1 5V/div. IL 5A/div. 50ms/div. Standby VOUT1 10V/div. 50ms/div. Standby VSTBY 2V/div. VOUT1 10V/div. MP8046 Rev. 0.92 4/29/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 6 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE OPERATION The MP8046 is a high voltage, dual channel power half- bridge that can be configured as the output of a Class D amplifier. The output is in phase with the input, and the dead time is optimized for symmetrical performance, regardless of load conditions. When shutdown pin ( SHDN ) is low, both channels 1 and 2 will be shut off. When the standby pin ( STBY ) is pulled low, it causes the outputs of both channels to go into high impedance. However, when the voltage across the BST1/2 and OUT1/2 pins drops sufficiently low, the bottom MOSFET is turned on to refresh the external bootstrap capacitor. For a bootstrap capacitor of 100nF, the refresh time is approximately 300ns. Thermal monitoring is also integrated into the MP8046. If the die temperature rises above 150°C, both switches are turned off. The temperature must fall below 130°C before normal operation resumes. To enhance the robustness of the device under short circuit condition, a capacitor can be connected to the FAULT pin, as shown in figure 1. The time constant of the RC is selected to be greater than 50ms for the FAULT node to reach 1V. Under short circuit condition, the FAULT node will be reset to zero and the part will be place in standby mode until the voltage at the STBY pin is above 1V. In order to prevent erratic operation, two under voltage lockout (UVLO) circuits are used. One of them is to ensure that the supply for the bottom gate drive circuit is sufficiently high and the other is for the top gate driver. Fault Protection To protect the power MOSFETs, two layers of protection are provided. The first is the current limit, wherein if the current through either the top or the bottom MOSFET exceeds an internally preset value of 5A, that particular MOSFET is immediately shut down and the complementary MOSFET is turned on. If this fails to reset the current and there is an indication that the current is going to runaway, the current foldback will kick in. This ensures that the current is reset close to zero before resuming operation. Figure 1— Fault Protection Circuit Fault Output The MP8046 includes an open drain, active low fault indicator output ( FAULT ). A fault will be indicated if the current limit is tripped or the thermal shutdown is tripped. A fault on any channel causes the FAULT pin to be pulled low. However, only that fault channel has its output set to high impedance. Do not apply more than 6V to the FAULT pin. MP8046 Rev. 0.92 4/29/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 7 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE BLOCK DIAGRAM BST1 VDD1 HIGH-SIDE DRIVER PWM1 LOGIC CONTROL VDD1 VDR1 OVER CURRENT SENSE REGULATOR OUT1 AGND1 LOW-SIDE DRIVER SHDN FAULT HANDLING & CONTROL STBY PGND1 THERMAL SHUTDOWN FAULT BST2 VDD2 HIGH-SIDE DRIVER PWM2 LOGIC CONTROL VDD2 VDR2 REGULATOR OVER CURRENT SENSE OUT2 AGND2 LOW-SIDE DRIVER PGND2 Figure 2—Function Block Diagram MP8046 Rev. 0.92 4/29/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 8 MP8046 –28V, 5A DUAL CHANNEL POWER HALF-BRIDGE PACKAGE INFORMATION TSSOP20F 0.0256(0.650)TYP 0.004(0.090) 0.010(0.250) GATE PLANE 0.105 (2.67) 0.118 (3.00) pad width 0.169 0.177 0.244 0.260 (4.300) (4.500) (6.200) (6.600) 0.004(0.090) 0o -8o 0.018(0.450) 0.030(0.750) DETAIL "A" 0.039(1.000)REF 0.030(0.750) PIN 1 IDENT. SEE DETAIL "B" 0.150 (3.80) 0.165 (4.19) pad length 0.030(0.750) SEE DETAIL "A" 0.075(0.190) 0.012(0.300) 0.252 (6.400) 0.260 (6.600) 0.032(0.800) 0.041(1.050) 0.047(1.200) max 0.007(0.190) 0.012(0.300) 0.002(0.050) 0.006(0.150) 0.004(0.090) 0.008(0.200) 0.004(0.090) 0.006(0.160) SEATING PLANE 0.007(0.190) 0.010(0.250) DETAIL "B" NOTE: 1) Control dimension is in inches. Dimension in bracket is millimeters. NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8046 Rev. 0.92 4/29/2010 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. 9