MP86905
TM
Intelli-Phase Solution with
Integrated HS-/LS-FETs and Driver
DESCRIPTION
FEATURES
The MP86905 is a monolithic half-bridge with
built-in internal power MOSFETs and gate
drivers. The MP86905 achieves 50A of
continuous output current over a wide input
supply range.
The MP86905 is a monolithic IC approach to
drive up to 50A of current per-phase. The
integration of drivers and MOSFETs results in
high efficiency due to optimal dead time and
parasitic inductance reduction. The MP86905
can operate with a range from 100kHz to 2MHz.
Wide 4.5V to 16V Operating Input Range
50A Output Current
Current Sense with Accu-SenseTM
Temperature Sense
Accepts Tri-State PWM Signal
Current-Limit Protection
Over-Temperature Protection (OTP)
Fault Reporting
Available in an FC-QFN (4mmx4mm)
Package
APPLICATIONS
The MP86905 offers many features to simplify
system design. The MP86905 works with
controllers with tri-state PWM signal and comes
with an accurate current sense to monitor the
inductor current and temperature sense to
report junction temperature.
Server Core Voltage
Graphic Card Core Regulators
Power Modules
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
The MP86905 is ideal for server applications
where efficiency and small size are a premium.
The MP86905 is available in a small FC-QFN
(4mmx4mm) package.
TYPICAL APPLICATION
3.3V
VDRV
VDD
MP86905
Intelli-Phase
VIN
VIN
AGND
BST
PWM
EN
SYNC
CS
VTEMP
FAULT#
MP86905 Rev. 1.1
8/31/2020
PWM
SW
VOUT
EN
SYNC
CS
PGND
VTEMP
FAULT#
PGND
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
1
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
ORDERING INFORMATION
Part Number
MP86905GR
Package
QFN-23 (4mmx4mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP86905GR–Z)
TOP MARKING
M P S Y WW
M 8 6 9 0 5
L L L L L L
MPS: MPS prefix
Y: Year code
WW: Week code
M86905: First six digits of the part number
LLLLLL: Lot number
PACKAGE REFERENCE
VDRV
AGND
VDD
SYNC
VTEMP
CS
EN
20
19
18
17
16
1
15
PWM
2
14
VIN
13
PGND
3
6
7
8
9
10
11
12
PGND
PGND
PGND
5
PGND
4
PGND
SW
21
PGND
SW
22
PGND
VIN
23
PGND
BST
FAULT#
TOP VIEW
QFN-23 (4mmx4mm)
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
2
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ....................................18V
VSW (DC) ............................... -0.3V to VIN + 0.3V
VSW (25ns)......................................... -3V to 25V
VIN-VSW (10ns) ................................... -5V to 32V
VBST-VSW (25ns) ..............................................5V
VBST .....................................................VSW + 4V
All other pins ...................... -0.3V to VDD + 0.3V
Instantaneous current .................................90A
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +150°C
Thermal Resistance (3)
θJB θJC_TOP
QFN-23 (4mmx4mm) ...........2..........24..... C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
3) θJB is the thermal resistance from the junction to board around
the PGND soldering point.
θJC_TOP is the themal resistance from the junction to the top of
the package.
Recommended Operating Conditions (2)
Supply voltage (VIN) ....................... 4.5V to 16V
Driver voltage (VDRV) ................... 3.0V to 3.6V
Logic voltage (VDD) ....................... 3.0V to 3.6V
Operating junction temp. (TJ). .. -40°C to +125°C
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
3
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
ELECTRICAL CHARACTERISTICS
VIN = 12V, VDRV = VDD = EN = 3.3V, TA = 25°C for typical value and TJ = -40°C to 125°C for max
and min values, unless otherwise noted.
Parameter
Symbol
IIN shutdown
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
IVIN Off
Condition
Min
Max
Units
40
μA
2.5
3.0
V
600
660
mV
EN = low
15
μA
PWM = low
80
μA
EN = low
PWM = low
4
2.8
250
2.75
45
5
2.9
380
2.9
μA
mA
V
mV
V
400
440
mV
EN = low
540
IVDRV quiescent current
IVDD quiescent current
VDD voltage UVLO rising
VDD voltage UVLO hysteresis
VDRV voltage UVLO rising
120
VDRV voltage UVLO hysteresis
360
High-side current limit(4)
ILIM_FLT
Low-side current limit(4)
Cycle-by-cycle up to four
cycles
Negative current limit,
cycle-by-cycle, no fault
report
Negative current limit low-side off
time(4)
High-side current limit shutdown
counter(4)
EN input low threshold voltage
EN input high threshold voltage
Dead time rising(4)
SYNC internal pull-down resistor
SYNC logic high voltage
SYNC logic low voltage
RSYNC
PWM high-to-SW rising delay(4)
PWM low-to-SW falling delay(4)
tRising
tFalling
tLT
tTL
tHT
tTH
PWM tri-state to SW Hi-Z delay(4)
MP86905 Rev. 1.1
8/31/2020
75
A
-30
A
40
ns
4
times
0.95
1.0
1.05
V
1.15
1.2
3
6
1.25
V
ns
ns
Positive inductor current
Negative inductor
current
Dead time falling(4)
Typ
35
ns
100
kΩ
V
V
2
0.8
15
15
40
20
40
20
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
ns
ns
ns
ns
ns
ns
4
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VDRV = VDD = EN = 3.3V, TA = 25°C for typical value and TJ = -40°C to 125°C for max
and min values, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
-2
20
0
2
ns
%
width(4)
Minimum PWM pulse
CS sense gain accuracy
15A ≤ IOUT ≤ 50A
10
-100
μA/A
μA
V
mV/°C
mV
Over-temperature shutdown and
fault flag(4)
160
°C
Over-temperature threshold
hysteresis(4)
30
°C
VPWM = 3.3V, VEN = 3.3V
660
μA
VPWM = 0V, VEN = 3.3V
-550
μA
V
V
V
V
CS sense gain
CS offset
CS voltage range(4)
VTEMP sense gain(4)
VTEMP sense offset(4)
PWM input current
9.7
IOUT = 0A
-5
0.7
VCS
5
2.1
TJ = 25°C
IPWM
PWM logic high voltage
PWM tri-state region
PWM logic low voltage
FAULT# pull-down
2.35
1.10
1.90
0.80
0.3
Sink 5mA
NOTE:
4) Guaranteed by design or characterization data, not tested in production.
PWM TIMING DIAGRAM
PWM
SW
Hi-Z
tRising
tFalling
tLT
tHT
tTH
MP86905 Rev. 1.1
8/31/2020
Hi-Z
tTL
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
5
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
PIN FUNCTIONS
Pin #
Name
1
BST
2, 14
VIN
Supply voltage. Place CIN close to the device to support the switching current and
reduce voltage spikes at input.
3, 4
SW
Phase node.
5 - 13
PGND
15
PWM
16
17
18
19
EN
CS
VTEMP
SYNC
20
VDD
21
AGND
Analog ground. Connect AGND to PGND on the VDD capacitor.
22
VDRV
Driver voltage. Connect VDRV to a 3.3V supply and decouple with a 1µF to 4.7µF
ceramic capacitor close to VDRV to PGND.
23
FAULT#
Fault report. FAULT# is an open drain, active low. FAULT# pulls low when SW
short detection, HS current limit, or over-temperature is triggered. During a cycle-bycycle high-side current limit event, FAULT# is kept high until the fourth cycle.
MP86905 Rev. 1.1
8/31/2020
Description
Bootstrap. BST requires a 0.1µF to 1µF capacitor to drive the high-side power
switch’s gate above the supply voltage. Connect the capacitor between BST and
SW to form a floating supply across the power switch driver.
Power ground.
Pulse width modulation input. Leave PWM floating or drive PWM to mid-state to
enter diode emulation mode.
Enable. Pull EN low to disable the device and place SW in a high impedance state.
Current sense output.
Junction temperature sense output.
Diode emulation mode. Pull SYNC low to enable diode emulation mode.
Internal circuitry voltage. Connect VDD to VDRV through a 2.2Ω resistor and
decouple with a 1µF capacitor to AGND.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
6
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VDD = VDRV = 3.3V, TA = 25˚C, unless otherwise noted.
VDD UVLO
VDRV UVLO
3.0
3.0
2.9
2.8
SYNC HI
2.0
VDD Rising
2.8
2.7
2.6
VDD Falling
1.8
2.6
2.4
VDRV Falling
2.2
2.0
2.5
0
50
100
0
PWM HI
PWM_LO THRESHOLD (V)
PWM Rising
2.1
PWM Falling
1.7
50
100
150
0
SYNC Falling
1.2
-50
0
50
100
1.5
1.3
1.3
PWM Rising
0.9
PWM Falling
0.7
0
50
100
TEMPERATURE (oC)
TEMPERATURE (oC)
150
EN Rising
1.1
EN Falling
0.9
0.7
0.5
-50
150
100
EN HI
1.5
1.1
50
TEMPERATURE (oC)
0.5
1.5
-50
1.4
PWM LO
2.5
1.9
1.6
TEMPERATURE (oC)
TEMPERATURE (oC)
2.3
SYNC Rising
1.0
-50
150
EN_HI THRESHOLD (V)
-50
PWM_HI THRESHOLD (V)
SYNC_HI THRESHOLD (V)
VDRV UVLO THRESHOLD (V)
VDD UVLO THRESHOLD (V)
VDRV Rising
150
-50
0
50
100
150
TEMPERATURE (oC)
100%
99%
98%
97%
96%
95%
94%
93%
92%
91%
90%
89%
88%
87%
86%
85%
84%
83%
82%
81%
80%
10
9
VOUT=1.8V
8
7
6
VOUT=1.2V
5
4
LOSS (W)
EFFICIENCY
DEVICE EFFICIENCY & LOSS
VIN=12V; L=220nH; FSW =500KHz
3
2
1
0
0
5
10
15
20
25
30
35
40
OUTPUT CURRENT (A)
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
7
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VDD = VDRV = 3.3V, TA = 25˚C, unless otherwise noted.
HS CURRENT LIMIT
PWM
2V/div.
FAULT#
2V/div.
IL
25A/div.
SW
5V/div.
4s/div.
CS OUTPUT WAVEFORM
IOUT=20A
CS OUTPUT WAVEFORM
IOUT=0A
VCS
100mV/div.
SW
5V/div.
SW
5V/div.
400ns/div.
MP86905 Rev. 1.1
8/31/2020
400ns/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
8
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
BLOCK DIAGRAM
VDD
RDY
UVLO
VDRV
BST
VIN
VIN
VDRV
VDD
6K
PWM
HS Current Limit
5K
HS Current
Limit
VIN
SW
Level
Shift
HSFET
SW
HS ON
Control
Logic
EN
Inductor Current
Crossed Zero
SYNC
ZCD
SW
PGND
VDRV
LSFET
LS ON
Negative
Current Limit
AGND
FAULT#
Temperature
Sense
Current
Sense
VTEMP
CS
Negative
Current Limit
SW
PGND
SW
PGND
PGND
Figure 1: Functional Block Diagram
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
9
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
ICS IL GCS
APPLICATION INFORMATION
Operation
The MP86905 is a 50A, monolithic, half-bridge
driver with integrated MOSFETs and is ideally
suited for multi-phase buck regulators.
An external 3.3V supply is required to supply
both VDD and VDRV. When EN transitions
from low to high, and the VDD and VDRV
signals are both sufficiently high, operation
begins.
PWM
The PWM input is capable of a tri-state input.
When the PWM input signal is within the tristate threshold window for 50ns (tHT or tLT), the
HS-FET is turned off immediately, and the LSFET enters diode emulation mode, which is on
until zero-current detection. The tri-state PWM
input can come from a forced middle voltage
PWM signal or made by floating the PWM input
so the internal current source charges the
signal to a middle voltage. Please refer to the
PWM timing diagram on page 5 for the
propagation delay definition from PWM to the
SW node.
Diode Emulation Mode
In diode emulation mode, when PWM is either
low or in a tri-state input, the LS-FET is turned
on whenever the inductor current is positive.
The LS-FET turns off if the inductor current is
negative or after the inductor current crosses
zero current. Diode emulation mode can be
enabled by pulling SYNC low, driving PWM to
middle-state, or floating PWM.
Current Sense (CS)
CS is a bi-directional current source
proportional to the inductor current. The current
sense gain is 9.7μA/A (GCS). Generally, there is
a resistor (RCS) connected from CS to an
external voltage which is capable of sinking
small currents to provide enough of a voltage
level shift to meet the CS operating voltage.
The CS voltage range of 0.7V to 2.1V is
required to keep CS’s output current linearly
proportional to the inductor current.
(2)
Where VCM is a reference voltage connected to
RCS.
Intelli-Phase’s current sense output can be
used by the controller to accurately monitor the
output current. The cycle-by-cycle current
information from CS can be used for phasecurrent balancing, over-current protection, and
active voltage positioning (output-voltage
droop).
Positive and Negative Inductor Current Limit
When HS-FET over-current is detected for four
consecutive cycles, the HS-FET latches off, and
FAULT# is asserted low. The LS-FET is turned
on until zero-current detection, and then is
turned off. Recycling VIN, VDD/VDRV, or
toggling EN releases the latch and restarts the
device.
When the LS-FET detects a -30A current, the
MP86905 turns off the LS-FET for 40ns to limit
the negative current. The LS-FET’s negative
current limit will not trigger a fault report.
Over-Temperature Protection (OTP)
When the junction temperature reaches the
over-temperature threshold, the HS-FET is
latched off, FAULT# is asserted low, and the
LS-FET is turned on until zero-current
detection.
Temperature Sense Output (VTEMP)
VTEMP reports the junction temperature.
VTEMP is a voltage proportional to the junction
temperature. The VTEMP output voltage is
10mV/°C (GVTEMP) with a -100mV offset
(VTEMP_Offset) and can be calculated with
Equation (3):
VTEMP TJUNCTION GVTEMP VTEMP _ Offset (3)
For example, if the junction temperature is
100°C, then VTEMP is 0.9V. VTEMP = 0V for
junction temperatures below 10°C. In multiphase operation, VTEMP of every Intelli-Phase
can be connected to the temperature monitor
pin of the controller (see Figure 2).
A proper reference voltage, VCM, and RCS
values can be determined with Equation (1) and
Equation (2):
0.7V ICS R CS VCM 2.1V
MP86905 Rev. 1.1
8/31/2020
(1)
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
10
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
Fault Report (FAULT#)
FAULT# is an open-drain, active-low signal that
reports faults from the Intelli-Phase. When any
fault occurs, FAULT# is pulled low.
2) Over-temperature fault at TJ > 160°C: Once
the fault occurs, the MP86905 latches off to
turn off the HS-FET. The LS-FET turns off
when the inductor current reaches zero.
FAULT# monitors three fault events:
3) SW to PGND shorted: Once the fault
occurs, the part latches off to turn off the
HS-FET.
1) Over-current limit: To trip the over-current
fault, the current limit must be exceeded
four consecutive times. Once the fault
occurs, the MP86905 latches off to turn off
the HS-FET. The LS-FET turns off when
the inductor current reaches zero.
The fault latch can be released by recycling
VIN, VDD, or toggling EN.
Intelli-Phase
Power Stage
VIN
IntelliPhase
VIN
L2
VOUT
VTEMP
Multi-Phase
Controller
COUT
PWM
PWM2
Temperature
ADC
VIN
IntelliPhase
VIN
L1
VTEMP
PWM
PWM1
Figure 2: Multi-Phase Temperature Sense Utilization
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
11
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 3 and
follow the guidelines below.
7. Place more PGND vias close to the PGND
pin/pad to minimize both parasitic
resistance/impedance
and
thermal
resistance.
1. Place the input MLCC capacitors as close
to VIN and PGND as possible.
8. Place a BST capacitor and a VDRV
capacitor as close to the MP86905 pins as
possible. VDRV and BST capacitors size
0402 are recommended.
2. Place the major MLCC capacitors on the
same layer as the MP86905.
9. Use a trace width 20 mils or higher to route
the path.
3. Place as many VIN and PGND vias
underneath the package as possible.
10. Avoid the via for the BST driving path. It is
recommended to use a bootstrap capacitor
0.1µF to 1µF in a size 0402 package.
4. Place the vias between the VIN or PGND
long pads.
5. Place a VIN copper plane on the second
inner layer to form the PCB stack as VIN on
top, GND on the second layer, and VIN on
the third layer to reduce parasitic
impedance from the input MLCC cap to the
MP86905.
11. Place the VDD decoupling capacitor (size
0402) close to the device.
12. Connect AGND and PGND at the point of
the VDD capacitor's ground connection.
13. Keep the CS signal trace away from high
current paths like SW and PWM.
6. Ensure that the copper plane on the inner
layer at least covers the VIN vias
underneath the package and input MLCC
capacitors.
RVDD
21
20
19
18
17
EN
SYNC
VTEMP
22
CS
VDD
23
AGND
FAULT#
CVDD
VDRV
CVDRV
16
VIN
CBST
BST
VIN
1
15
PWM
2
14
VIN
13
PGND
SW
3
SW
4
5
6
7
8
9
10
11
12
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SW
PGND
INDUCTOR
8mm
CIN
CIN
PGND
20.6 mm
Figure 3: Example of PCB Layout (Placement & Top Layer PCB)
Input Capacitor: 1206 package (top side) and 0805 package (bottom side)
Inductor: 10x8 package
VDD/BST/VDRV capacitor: 0402 package
Via size: 20/10 mils
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
12
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
PACKAGE INFORMATION
QFN-23 (4mmx4mm)
PIN 1 ID
0.15x45°TYP.
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
0.15x45°
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
13
MP86905 – INTELLI-PHASE SOLUTION W/ INTEGRATED MOSFETS AND DRIVERS
Revision History
Revision
#
Revision
Date
1.1
5/21/2020
Description
Correct/add the “Vin-Vsw (10ns) …………. -5V to 32V”
on absMax rating.
Pages
Updated
P3
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP86905 Rev. 1.1
8/31/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
14
工商网监
湘ICP备2023018690号
