MP86920
Intelli-PhaseTM Solution
with Integrated HS-/LS-FETs and Driver
in LGA (4mmx5mm) Package
DESCRIPTION
FEATURES
The MP86920 is a monolithic half-bridge driver
with built-in internal power MOSFETs and gate
drivers. It achieves 20A of continuous output
current across a wide input supply range.
The integrated driver and MOSFETS result in
high efficiency due to an optimal dead time and
reduced parasitic inductance.
This device works with tri-state output
controllers, and can operate between 100kHz
and 2MHz. It also comes with a generalpurpose current sense and temperature sense.
The MP86920 is well-suited for server and
telecom applications where efficiency and small
size are a premium. It is available in an LGA-27
(4mmx5mm) package.
Wide 4.5V to 16V Operating Input Range
20A Output Current
Accepts Tri-State PWM Signals
Built-In Switch for Bootstrap
Current Sense
Temperature Sense
Current Limit Protection
Over-Temperature Protection (OTP)
Fault Reporting
Used for Multi-Phase Operation
Available in an LGA-27 (4mmx5mm)
Package
APPLICATIONS
Server and Telecom Voltage Regulators
Graphics Card Core Regulators
Power Modules
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
TYPICAL APPLICATION
VDRV
VDD
AGND
MP86920 Rev. 1.0
12/22/2020
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1
MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
ORDERING INFORMATION
Part Number*
Package
Top Marking
MSL Rating
MP86920GLV
LGA-27 (4mmx5mm)
See Below
3
* For Tape & Reel, add suffix –Z (e.g. MP86920GLV–Z).
TOP MARKING
MPS: MPS prefix
Y: Year code
WW: Week code
M86920: Part number
LLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
LGA-27 (4mmx5mm)
MP86920 Rev. 1.0
12/22/2020
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2
MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
PIN FUNCTIONS
Pin #
1
2, 23
3
4
5, 24, 27
6, 7, 13, 14,
15, 26
8, 9, 10, 11,
12
Name
Description
TMON/FLT Single-pin temperature sense and fault reporting.
Analog ground. Connect AGND to the PGND plane at the VDD decoupling
AGND
capacitor.
3.3V supply for internal circuitry. Decouple VDD with 1µF (or higher) ceramic
VDD
capacitor connected to AGND.
Driver voltage. Connect VDRV to a 3.3V supply. Decouple this pin with a 1μF to
VDRV
4.7μF ceramic capacitor.
NC
No connection.
Power ground. Place multiple vias on the inner solid ground layers to minimize
PGND
parasitic impedance and thermal resistance.
SW
16, 17, 18
VIN
19
PHASE
20
BST
21
PWM
22
EN
25
CS
MP86920 Rev. 1.0
12/22/2020
Switch output.
Supply voltage. Place an input capacitor (CIN) on VIN. Place the capacitor close to
the device to support the switching current and reduce voltage spikes at the input.
Switching node for bootstrap capacitor connection. The PHASE pin is internally
connected to SW.
Bootstrap. BST requires a 0.1µF to 1µF capacitor to drive the power switch’s gate
above the supply voltage. Connect the capacitor between the PHASE and BST pins
to form a floating supply across the power switch driver.
Pulse-width modulation input. Float the PWM pin or drive it to a middle-state
voltage to enable diode emulation mode.
Enable. Pull EN low to disable the device and place SW in a high-impedance state.
Current-sense output. Connect an external resistor to the CS pin to adjust the
voltage proportional to the inductor current.
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
θJB θJC_TOP
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (3)
Supply voltage (VIN) .................................... 18V
VSW (DC) .................................-0.3V to VIN + 0.3V
VSW (25ns) ............................................-5V to +25V
VIN - VPHASE (DC) .............................-0.3V to +25V
VIN - VPHASE (10ns) ..............................-5V to +32V
VBST - VPHASE (25ns)............................................ 5V
VBST .................................................. VPHASE + 4V
VDD, VDRV ....................................-0.3V to +4V
All other pins ...................... -0.3V to VDD + 0.3V
Instantaneous current ................................. 45A
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +150°C
LGA-27 (4mmx5mm) ........... 4.3..... 18.7 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
3) θJB is the thermal resistance from the junction to board around
the PGND soldering point.
θJC_TOP is the thermal resistance from the junction to the top of
the package.
ESD Ratings
Human body model (HBM) ..................... Class 1
Charged device model (CDM)...........Class C2B
Recommended Operating Conditions (2)
Supply voltage (VIN) ........................ 4.5V to 16V
Driver voltage (VDRV) .................... 3.0V to 3.6V
Logic voltage (VDD) ........................ 3.0V to 3.6V
Operating junction temp (TJ). ... -40°C to +125°C
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
ELECTRICAL CHARACTERISTICS
VIN = 12V, VDRV = VDD = EN = 3.3V, TA = 25°C for typical values, TJ = -40°C to +125°C for
maximum and minimum values, unless otherwise noted.
Parameter
VIN under-voltage lockout rising
threshold
VIN under-voltage lockout
threshold hysteresis
VIN quiescent current in standby
mode
IVDRV quiescent current in active
mode
IVDRV quiescent current in standby
mode
VDD voltage UVLO rising
threshold
VDD voltage UVLO hysteresis
High-side current limit (4)
High-side current limit shutdown
counter (4)
Low-side current limit (4)
Low-side off time with negative
current limit (4)
Dead time rising (4)
Symbol
PWM tri-state to SW Hi-Z delay (4)
Min
QUIESCENT
PWM = Hi-Z, EN = low,
VIN = 4.5V to 16V
PWM = low, no switching,
EN = high
IDRV_STBY
EN = low
IIN STBY
IDRV_
2.4
ILIM_FLT
Positive inductor current
Negative inductor current
-2
CS offset
ISW = 0A
SW = Hi-Z
-7
-2
0.8
(4)
MP86920 Rev. 1.0
12/22/2020
Units
4.1
4.5
V
2.7
mV
5
μA
3.5
mA
30
μA
2.95
V
200
50
mV
A
4
times
-15
A
40
ns
3
8
40
ns
ns
ns
V
V
ns
ns
ns
ns
ns
ns
ns
%
μA/A
μA
μA
V
mV/°C
mV
V
V
V
0.8
tRISING
tFALLING
tLT
tTL
tTH
tHT
5A ≤ ISW ≤ 20A
TMON/FLT sense voltage range
Max
2.30
Minimum SW pulse width (4)
CS sense gain accuracy
CS sense gain
CS common mode voltage range
TMON/FLT sense gain (4)
TMON/FLT sense offset (4)
Typ
380
Dead time falling (4)
EN input high voltage
EN input low voltage
PWM high to SW rising delay (4)
PWM low to SW falling delay (4)
Condition
VCS_COM
TJ = 25°C
TJ = 150°C
TJ = 100°C
TJ = 25°C
20
20
50
50
50
50
30
0
10
0
0
8
800
1.8
1.4
0.8
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+2
7
2
2
5
MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VDRV = VDD = EN = 3.3V, TA = 25°C for typical values, TJ = -40°C to +125°C for
maximum and minimum values, unless otherwise noted.
Parameter
Over-temperature shutdown (4)
TMON/FLT if a fault occurs (4)
Symbol
Condition
Min
3.0
Pull-up, EN = high
Pull-down
PWM resistor
PWM logic high voltage
PWM tri-state region
PWM logic low voltage
Typ
160
3.3
6
5
Max
2.4
1.1
1.9
0.7
Units
°C
V
kΩ
kΩ
V
V
V
Note:
4) Guaranteed by design. Not tested in production. The parameter is tested during parameters characterization.
PWM TIMING CHART
PWM
SW
Hi-Z
tRISING
tFALLING
tLT
tHT
tTH
MP86920 Rev. 1.0
12/22/2020
Hi-Z
tTL
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
98
96
94
92
90
88
86
84
82
80
Vout=1.8V
Vout=1.0V
0
5
10
15
LOAD CURRENT (A)
4
3.5
3
2.5
2
1.5
1
0.5
0
20
CASE TEMPERATURE RISE (℃)
Efficiency vs. Load Current
VIN = 12V, fSW = 800kHz, 150nH
POWER LOSS (W)
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
Case Temperature Rise vs.
Load Current
25
20
15
10
5
0
0
EN High Threshold vs.
Temperature
3
2.3
1.7
EN_HI_rising
1.6
EN_HI_falling
1.5
1.4
1.3
1.2
1.1
1
-50
0
50
100
TEMPERATURE (°C)
150
PWM HIGH THRESHOLD (V)
EN HIGH THRESHOLD (V)
1
1.5
2
2.5
LOAD CURRENT (A)
PWM High Threshold vs.
Temperature
1.8
2.2
2.1
2
PWM_HI_Falling
1.8
-50
VDD UVLO THRESHOLD (V)
1.3
1.1
0.9
PWM_LO_Rising
PWM_LO_Falling
0.5
-50
MP86920 Rev. 1.0
12/22/2020
0
50
100
TEMPERATURE ( C)
0
50
100
TEMPERATURE ( C)
150
VDD UVLO Threshold vs.
Temperature
1.5
0.7
PWM_HI_Rising
1.9
PWM Low Threshold vs.
Temperature
PWM LOW THRESHOLD (V)
0.5
150
3
2.9
2.8
2.7
VDD rising
2.6
VDD falling
2.5
-50
0
50
100
TEMPERATURE ( C)
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150
7
MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Switching
Dead Time with SW Ringing
VIN = 12V, L = 150nH, load = 10A
CH1: VSW
CH1: VSW
IOUT Output
IOUT Output
Load = 0A
Load = 10A
CH3: VCS
CH3: VCS
CH1: VSW
CH1: VSW
HS Current Limit
CH4: VFAULT
CH2: IL
CH3: PWM
CH1: VSW
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
FUNCTIONAL BLOCK DIAGRAM
VDRV
VDD
RDY
BST
VIN
VIN
UVLO
VDD
HS Current
Limit
PWM
Level
Shift
HS Current
Limit
HS-FET
VIN
SW
SW
HS On
Inductor
Current
Crossed Zero
Control
Logic
EN
ZCD
SW
PGND
VDRV
PHASE
LS On
Negative
Current Limit
AGND
Temperature
Sense and
Fault Reporting
TMON/FLT
Current
Sense
LS-FET
Negative
Current Limit
SW
PGND
SW
PGND
CS
PGND
Figure 1: Functional Block Diagram
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
OPERATION
The MP86920 is a 20A, monolithic half-bridge
driver with MOSFETs. It is well-suited for multiphase buck regulators. When the VIN, VDD
signals are sufficiently high, operation begins.
PWM
The PWM input pin is capable of tri-state input.
When the PWM input signal is within the tristate threshold window for about 50ns (tHT or
tLT), the high-side MOSFET (HS-FET) turns off
immediately. The low-side MOSFET (LS-FET)
enters diode emulation mode, and stays on until
zero-current detection (ZCD).
The tri-state PWM input is enabled by forcing a
middle-voltage PWM signal, or by floating the
PWM input. The internal current source charges
the signal to a middle voltage. See the PWM
Timing Diagram on page 6 to define the
propagation delay from PWM to the SW node.
Diode Emulation Mode
When PWM is in tri-state input in diode
emulation mode, the LS-FET turns on when the
inductor current is positive. The LS-FET turns
off if the inductor current reaches 0A. Diode
emulation mode can be enabled by floating the
PWM pin or driving it to a middle state.
Positive and Negative Inductor Current Limit
If an over-current (OC) condition is detected on
the HS-FET for four consecutive cycles, the
HS-FET latches off, and TMON/FLT is pulled to
3.3V. The LS-FET turns on, and stays on until
ZCD. To release the latch and restart the
device, cycle the power on VIN or VDD, or
toggle EN.
If the LS-FET detects a -15A current, the part
turns off the LS-FET for 40ns to limit the
negative current. The LS-FET’s negative
current limit does not trigger a fault report.
Over-Temperature Protection (OTP)
If the junction temperature reaches the overtemperature (OT) threshold, the HS-FET
latches off, and TMON/FLT is pulled to 3.3V.
The LS-FET turns on, and stays on until ZCD.
MP86920 Rev. 1.0
12/22/2020
Temperature-Sense Output with Fault
Indicator (TMON/FLT)
The TMON/FLT pin can sense the junction
temperature or indicate if certain faults have
occurred.
Junction Temperature Sense
When VDD exceeds its under-voltage lockout
(UVLO) threshold and the part is in active
mode, the TMON/FLT pin has an output voltage
that is proportional to the junction temperature.
The gain is 8mV/°C, and it has a 800mV offset
at 25°C (e.g. the voltage is 0.8V when TJ =
25°C, and 1.4V when TJ = 100°C).
Fault Function
If a fault occurs, the TMON/FLT pin is pulled to
VDD to report the fault, regardless of the
temperature. TMON/FLT monitors three fault
events, described below:
1. Over-current limit: The current limit fault
condition must remain for four consecutive
cycles to trigger this fault. If this fault occurs,
the part latches off to turn off the HS-FET.
The LS-FET turns on and stays on until the
current reaches 0A.
2. Over-temperature fault when TJ > 160°C: If
an over-temperature fault occurs, the part
latches off, and the HS-FET turns off. The
LS-FET turns on and stays on until the
current reaches 0A.
3. SW-to-PGND short: If a short fault occurs,
the part latches off to turn off the HS-FET.
The fault latch is not reset by entering standby
mode. The fault latch is released by cycling the
power on VIN or VDD.
Current Sense (CS)
The CS pin is a bidirectional current source that
is proportional to the inductor current. The
current-sense gain is 10μA/A. If required, a
resistor can be used to configure the voltage
gain proportional to the inductor current
The CS voltage must range between 0.8V and
2.0V to keep CS’s output current linearly
proportional to the inductor current. In general,
there is a resistor (RCS) connected from the CS
pin to an external voltage that is capable of
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
sinking small currents. This provides a sufficient
voltage level to meet the required operating
voltage range.
Choose a value for RCS such that VCS stays
within its operating range. This relationship can
be calculated with Equation (1):
Figure 2 shows the typical circuit diagram for
the CS pin connection to achieve a differential
voltage source proportional to the inductor
current.
0.8V ICS RCS VCM 2.0V
VIN
ICS
Intelli-Phase TM
IL
VIN
CS
SW
GND
PWM
VCS
RCS
PWM
VCM
(1)
Where VCM is the reference voltage connected
to RCS, and ICS is the current on the CS pin,
estimated with Equation (2):
ICS IL GCS
(2)
The Intelli-Phase’sTM current-sense output can
be used by the controller to accurately monitor
the output current. The cycle-by-cycle current
information from the CS pin can be used for
phase
current
balancing,
over-current
protection, and active voltage positioning
(output voltage droop).
Figure 2: Typical Circuit Diagram for CS Pin
Connection
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
APPLICATION INFORMATION
PCB Layout Guidelines
An efficient layout is critical for stable operation.
For the best results, refer to Figure 3 and follow
the guidelines below:
1. Place the MLCC input capacitors as close to
VIN and PGND as possible.
2. Place as many VIN and PGND vias
underneath the package as possible. Place
these vias between the VIN or PGND long
pads.
3. Place a VIN copper plane on the second
inner layer to form the PCB stack
(positive/negative/positive)
to
reduce
parasitic impedance from the MLCC input
capacitor to the MP86950. Ensure that the
copper plane on the inner layer covers the
VIN vias and MLCC input capacitors.
4. Place more PGND vias close to the PGND
pin/pad to minimize parasitic resistance,
parasitic impedance, and thermal resistance.
5. Place the BST capacitor, BST resistor, and
VDRV capacitor as close to the MP86950’s
pins as possible. For BST routing, use a
trace width greater than 20mils. Avoid
placing vias on the BST driving path.
6. Place the VDD decoupling capacitor close
to the device.
7. Route the CS signal trace away from high
voltages and current slew rate nodes (such
as SW, PWM, the VIN vias, and the PGND
vias).
Figure 3: Recommended PCB Layout
Input Capacitor: 0402 Package (Top Side) and 0805 Package (Bottom Sides)
BST/VDRV/VDD Capacitor/Resistor: 0402 Package
Via Size: 10/20mils
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
PACKAGE INFORMATION
LGA-27 (4mmx5mm)
PIN 1 ID
MARKING
PIN 1 ID
0.30X45° TYP
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
RECOMMENDED LAND PATTERN
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
3) JEDEC REFERENCE IS MO-303.
4) DRAWING IS NOT TO SCALE.
RECOMMENDED STENCIL DESIGN
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
CARRIER INFORMATION
Pin1
1
1
ABCD
1
1
ABCD
ABCD
ABCD
Feed Direction
Part Number
Package
Description
Quantity/
Reel
Quantity/
Tube
Quantity/
Tray
Reel
Diameter
Carrier
Tape
Width
Carrier
Tape
Pitch
MP86920GLV–Z
LGA-27
(4mmx5mm)
5000
N/A
N/A
13in
12mm
8mm
MP86920 Rev. 1.0
12/22/2020
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MP86920 – 16V, INTELLI-PHASETM SOLUTION IN LGA-27 (4mmx5mm) PACKAGE
REVISION HISTORY
Revision #
1.0
Revision Date
12/22/2020
Description
Initial Release
Pages Updated
-
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP86920 Rev. 1.0
12/22/2020
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