MP86956GMJ-Z

TM MP86956 Intelli-Phase Solution (Integrated HS/LSFETs and Driver) in LGA and TLGA (5x6mm) DESCRIPTION FEATURES The MP86956 is a monolithic half-bridge with built-in internal power MOSFETs and gate drivers. The MP86956 achieves 70A of continuous output current over a wide input supply range.          The MP86956 takes a monolithic IC approach that drives up to 70A of current per phase. The integration of drivers and MOSFETs results in high efficiency due to an optimal dead time and parasitic inductance reduction. The MP86956 can operate from 100kHz to 3MHz. The MP86956 offers many features to simplify system design. The MP86956 works with controllers with a tri-state PWM signal and comes with an accurate current sense to monitor the inductor current and temperature sense to report the junction temperature. The MP86956 is ideal for server applications where efficiency and small size are a premium. The MP86956 is available in LGA and TLGA (5mmx6mm) packages. Wide 3V to 16V Operating Input Range 70A Output Current Current Sense: Accu-SenseTM Temperature Sense Accepts Tri-State PWM Signal Current-Limit Protection Over-Temperature Protection (OTP) Fault Reporting Available in LGA and TLGA (5mmx6mm) Packages APPLICATIONS    Server Core Voltage Graphic Card Core Regulators Power Modules All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 1 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA ORDERING INFORMATION Part Number* MP86956GMJ MP86956GMJT Package LGA-41 (5mmx6mm) TLGA-41 (5mmx6mm) Top Marking See Below * For Tape & Reel, add suffix –Z (e.g.: MP86956GMJ–Z, MP86956GMJT–Z). TOP MARKING (MP86956GMJ) MPS: MPS prefix YY: Year code WW: Week code MP86956: Part number LLLLLLL: Lot number TOP MARKING (MP86956GMJT) MPS: MPS prefix YY: Year code WW: Week code MP86956: Part number LLLLLLL: Lot number T: Thin PACKAGE REFERENCE TOP VIEW LGA-41 (5mmx6mm), TLGA-41 (5mmx6mm) MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 2 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA PIN FUNCTIONS Pin # 1, 6, 31, 37, 39, 41 2 Pin Name 3 VDD 4 VDRV 5, 7 - 9, 20 - 24, 40 10 - 19 NC AGND PGND SW 25 - 30 VIN 32 PHASE 33 BST 34 PWM 35 EN 36 TOUT/FLT 38 IOUT Descriptions No connection. Analog ground. Supply voltage for internal circuitry. Connect VDD to VDRV through a 2.2Ω resistor. Decouple VDD with a 1µF capacitor to AGND. Connect AGND and PGND at the VDD capacitor. Driver voltage. Connect VDRV to a 3.3V supply. Decouple VDRV with a 1µF to a 4.7µF ceramic capacitor. Power ground. Phase node. Input supply voltage. Place input ceramic capacitors (CIN) close to the device to support the switching current with minimal parasitic inductance. Switching node for the bootstrap capacitor connection. PHASE pin is connected to SW internally. Bootstrap. BST requires a 0.1µF to 0.22µF capacitor to drive the power switch’s gate above the supply voltage. Connect the capacitor between SW and BST to form a floating supply across the power switch driver. Pulse-width modulation input. Leave PWM floating or drive PWM to a midstate level to put SW in a high impedance state. Enable. Pull EN low to disable the MP86956 and place SW in a high impedance state. Single-pin temperature sense and fault reporting. TOUT/FLT is pulled up to the VDD voltage when a fault occurs. Current sense output. Use an external resistor to adjust the voltage proportional to the inductor current. ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (3) Supply voltage (VIN) ...................................... 18V VIN to VPHASE (DC) ............................... -0.3V to 25V VIN to VPHASE (10ns) ................................ -5V to 32V VSW to PGND (DC) ................... -0.3V to VIN + 0.3V VSW to PGND (25ns) ............................... -5V to 25V VBST................................................... VPHASE + 4V VDD, VDRV ......................................... -0.3V to +4V All other pins ...................... -0.3V to VDD + 0.3V Instantaneous current ................................ 125A Junction temperature ................................ 150°C Lead temperature...................................... 260°C Storage temperature .................-65°C to +150°C LGA-41 (5mmx6mm) ........... 2.2 ..... 8.7 .... °C/W TLGA-41 (5mmx6mm) ......... 2.2 ..... 2.0 .... °C/W θJB θJC_TOP NOTES: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) θJB: Thermal resistance from the junction to board around the PGND soldering point. θJC_TOP: Thermal resistance from the junction to the top of the package. Recommended Operating Conditions (2) Supply voltage (VIN) ......................... 3.0V to 16V Driver voltage (VDRV) .................... 3.0V to 3.6V Logic voltage (VDD) ........................ 3.0V to 3.6V Operating junction temp. (TJ). ...-40°C to +125°C MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 3 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA ELECTRICAL CHARACTERISTICS VIN = 12V, VDRV = VDD = EN = 3.3V, TA = 25°C for typical value, TJ = -40°C to 125°C for max and min values, unless otherwise noted. Parameter IIN shutdown VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold hysteresis IVDRV quiescent current IVDD quiescent current VDD voltage UVLO rising VDD voltage UVLO hysteresis High-side current limit (4) Symbol Condition EN = low Min PWM = low PWM = low ILIM_FLT Cycle-by-cycle up to 8 cycles Negative current limit, cycleby-cycle, no fault report Positive inductor current Negative inductor current Dead time at SW is falling (4) (4) Minimum PWM pulse width (4) IOUT sense gain accuracy (4) IOUT sense gain IOUT pin voltage range MP86956 Rev. 1.3 7/21/2020 2.5 3.0 V mV 350 2.95 A 200 ns 8 Times 2 6 28 ns ns ns V V ns ns ns ns ns ns ns % μA/A 0.8 tRising tFalling tLT tTL tHT tTH 20A ≤ ISW ≤ 70A -2 GIOUT ISW = 0A, VIOUT = 1.2V, TJ = 25°C SW = Hi-Z, VIOUT = 1.2V VIOUT μA mA V mV A -35 2.30 IOUT sense offset (4) Units μA 250 3 2.75 300 110 Negative current limit low-side off time (4) High-side current limit shutdown counter (4) Dead time at SW is rising (4) PWM tri-state to SW Hi-Z delay Max 180 450 Low-side current limit (4) EN input high threshold voltage EN input low threshold voltage PWM high to SW rising delay (4) PWM low to SW falling delay (4) Typ 90 20 20 40 30 40 30 30 0 5 +2 -2 0 2 μA -1 0.7 0 1 2.1 μA V www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 4 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VDRV = VDD = EN = 3.3V, TA = 25°C for typical value and TJ= -40°C to 125°C for max and min values, unless otherwise noted. Parameter TOUT/FLT sense gain (4) TOUT/FLT sense offset(4) Over-temperature shutdown and fault flag (4) TOUT/FLT when fault (4) Symbol Condition Min TJ = 25°C 3.0 Pull up, EN = high Pull down, EN = high PWM resistor PWM logic high voltage PWM tri-state region PWM logic low voltage Typ 8 800 Max Units mV/°C mV 160 °C 3.3 6 5 V kΩ kΩ V V V 2.30 1.10 1.8 0.80 NOTE: 4) Guaranteed by design or characterization data, not tested in production. PWM TIMING DIAGRAM MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 5 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA TYPICAL CHARACTERISTICS VDD UVLO Efficiency and Loss   18 96% 16 94% 14 92% 12 90% 10 MP86956 (1.2V) 88% 8 MP86956 (1.8V) 86% 6 84% 4 82% 2 80% 3 VDD UVLO THRESHOLD (v) 98% LOSS (W) EFFICIENCY VIN = 12V, L = 150nH, FSW = 500kHz  2.9 2.8 2.7 2.6 2.4 2.3 0 -50 0 5 10 15 20 25 30 35 40 45 50 55 60 OUTPUT CURRENT (A) 50 100 150 PWM_LO 2 1.5 1.9 PWM_LO THRESHOLD (v) EN_Hi THRESHOLD (v) 0 TEMPERATURE (℃) EN_HI   VDD rising VDD falling 2.5 1.8 1.7 1.6 EN_Hi rising 1.5 EN_Hi falling 1.4 1.3 1.2 -50 0 50 100 150 TEMPERATURE (℃) 1.3 1.1 0.9 PWM_Lo rising 0.7 PWM_Lo falling 0.5 -50 0 50 100 TEMPERATURE (℃) 150 PWM_HI    PWM_Hi THRESHOLD (v) 2.3 PWM_Hi rising 2.2 PWM_Hi falling 2.1 2 1.9 1.8 -50 0 50 100 150 TEMPERATURE (℃) MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 6 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA TYPICAL PERFORMANCE CHARACTERISTICS Switching Dead Time @ SW Ringing VIN = 12V, L = 150nH, Load = 30A Load = 30A . CH1: VSW 4V/div. CH1: VSW 1V/div. 100ns/div. 2ns/div. IOUT Output IOUT Output Load = 0A Load = 30A CH4: VIOUT 200mV/div. CH4: VIOUT 200mV/div. CH1: VSW 5V/div. CH1: VSW 5V/div. 400ns/div. 400ns/div. HS Current Limit CH4: VFAULT 5V/div. CH3:PWM 5V/div. CH2: IL 25A/div. CH1: VSW 4V/div. 1μs/div. MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 7 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA BLOCK DIAGRAM Figure 1: Functional Block Diagram MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 8 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA APPLICATION INFORMATION Operation The MP86956 is a 70A, monolithic, half-bridge driver with MOSFETs ideally suited for multiphase buck regulators. An external 3.3V supply is required to supply both VDD and VDRV. When EN transitions from low to high and the VDRV signals are sufficiently high, operation begins. Pulse-Width Modulation (PWM) The pulse-width modulation (PWM) input pin is capable of tri-state input. When the PWM input signal is within the tri-state threshold window for a typical 50ns (THT or TLT), the high-side MOSFET (HS-FET) turns off immediately, and the low-side MOSFET (LS-FET) enters diode emulation mode, which is on until zero-current detection (ZCD). The tri-state PWM input can come from a forced mid-voltage PWM signal or made by floating the PWM input. The internal current source charges the signal to a middle voltage. Refer to the PWM timing diagram on page 5 for the propagation delay definition from PWM to SW node. Diode Emulation Mode In diode emulation mode, when PWM is low or in a tri-state input, the LS-FET is turned on whenever the inductor current is positive. The LS-FET turns off if the inductor current is negative or after the inductor current crosses the zero current. Diode emulation mode can be enabled by driving PWM to a middle state or by floating PWM. Current Sense IOUT is a bidirectional current source pin proportional to the inductor current. The current sensing gain is 5μA/A. A resistor is used to program the voltage gain proportional to the inductor current, if needed. The IOUT output has two states (see Table 1). In disable mode (EN = low), the current sense circuit is disabled, and IOUT is in Hi-Z (high impedance) state. Table 1: IOUT Output States PWM EN IOUT PWM High Active x Low Hi-Z MP86956 Rev. 1.3 7/21/2020 An IOUT voltage range of 0.7 - 2.1V is required to achieve an accurate IOUT current output of up to +350μA/-200μA (i.e.: +70A/-40A). Generally, there is a resistor (RIOUT) connected from IOUT to an external voltage that is capable of sinking small currents to provide enough voltage level to meet the required operating voltage range. A proper reference voltage, VCM, and RIOUT values can be determined with Equation (1) and Equation (2): 0.7V  IIOUT  RIOUT  VCM  2.1V (1) IIOUT  ISW  GIOUT (2) Where VCM is a reference voltage connected to RIOUT. Intelli-Phase’s current sense output can be used by the controller to monitor the output current accurately. The cycle-by-cycle current information from IOUT can be used for phasecurrent balancing, over-current protection, and active-voltage positioning (output voltage droop). Positive and Negative Inductor Current Limit When HS-FET over-current is detected, the HSFET turns off for that PWM cycle. If there are eight consecutive cycles of an HS-FET current limit event, the HS-FET latches off, TOUT/FLT pulls high to VDD, and the LS-FET turns on until ZCD. Toggle EN or recycle VIN or VDD to release the latch and restart the device. When the LS-FET detects a -35A valley current, the MP86956 turns off the LS-FET and turns on the HS-FET for 200ns to limit the negative current. The LS-FET negative current limit will not trigger a fault report. Temperature Sense indicator (TOUT/FLT) Output with Fault TOUT/FLT is a pin with two functions: junction temperature sense and fault detection. TOUT/FLT is a voltage output proportional to the junction temperature whenever VDD is higher than its UVLO and the part is in active mode. The gain is 8mV/°C and has a +800mV offset at 25°C. For example, 0.8V @ TJ = 25°C and 1.6V @ TJ = 125°C. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 9 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA When any fault occurs, TOUT/FLT is pulled to the VDD voltage to report the fault event regardless of the temperature. 200ns after the fault has occurred, the PWM impedance changes accordingly to indicate the fault type. Table 2 shows the PWM status regarding each fault event. Table 2: PWM Resistance when a Fault Occurs Fault Type PWM HS-FET current limit protection 10kΩ to AGND Over-temperature protection 20kΩ to AGND SW-PGND short protection 1kΩ to VDD TOUT/FLT can monitor three fault events. 1. Over-current limit (HS-FET): To trip the over-current fault, the current limit must be exceeded eight consecutive times. Once a fault occurs, the MP86956 latches off to turn off the HS-FET. The LS-FET turns OFF when the inductor current reaches zero. PWM uses a 10kΩ resistor to AGND to indicate the fault type. 2. Over-temperature fault at TJ > 160°C: Once a fault occurs, the MP86956 latches off to turn off the HS-FET. The LS-FET turns off when the inductor current reaches zero. PWM uses a 20kΩ resistor to AGND to indicate the fault type. 3. SW to PGND shorted: Once a fault occurs, the MP86956 latches off to turn off the HSFET. PWM is pulled high (1kΩ to VDD) to indicate the fault type. The fault latch can be released by toggling EN or by recycling VIN or VDD. For multi-phase operation, connect TOUT/FLT of each Intelli-Phase together (see Figure 3). Intelli-Phase Power Stage Vin IntelliPhase Vin L2 VOUT TOUT/FLT Multi-Phase Controller COUT PWM PWM2 Temperature ADC Vin IntelliPhase Vin L1 TOUT/FLT PWM PWM1 Figure 3: Multi-Phase Temperature Sense Utilization MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 10 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA PCB Layout Guidelines Efficient PCB layout is critical for stable operation. For best results, refer to Figure 4 and follow the guidelines below. 1. Place the input MLCC capacitors as close to VIN and PGND as possible. 2. Place the major MLCC capacitors on the same layer as the MP86956. 3. Place as many VIN and PGND vias underneath the package as possible. 7. Place more PGND vias close to the PGND pin/pad to minimize both parasitic resistance/impedance and thermal resistance. 8. Place BST capacitor and VDRV capacitor as close to the MP86956’s pins as possible. 9. Use a trace width of 20 mils or higher to route the path. 10. Avoid placing vias on the BST driving path. 11. Use a 0.1 - 0.22µF bootstrap capacitor. 4. Place the vias between the VIN or PGND long pads. 12. Place the VDD decoupling capacitor close to the device. 5. Place a VIN copper plane on the second inner layer to form the PCB stack as positive/negative/positive to reduce the parasitic impedance from the input MLCC capacitor to the MP86956. 13. Connect AGND and PGND at the point of the VDD capacitor's ground connection. 14. Keep the IOUT signal trace away from highcurrent path like SW and PWM. 6. Ensure that the copper plane on the inner layer at least covers the VIN vias underneath the package and input MLCC capacitors. Figure 4: Example of PCB Layout (Placement and Top Layer PCB) Input Capacitor: 0805 package (top and bottom sides) and 0402 package (top side) Inductor: 11x8 package VDD/BST/VDRV capacitor: 0402 package Via size: 20/10 mils MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 11 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA PACKAGE INFORMATION LGA-41 (5mmx6mm) PIN 1 ID 0.20x45° T YP. PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW 0.20X45º SIDE VIEW RECOMMENDED LAND PATTERN NOTE: RECOMMENDED STENCIL DESIGN MP86956 Rev. 1.3 7/21/2020 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-303. 4) DRAWING IS NOT TO SCALE. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 12 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA PACKAGE INFORMATION (continued) TLGA-41 (5mmx6mm) PIN 1 ID 0.20x45° T YP. PIN 1 ID MAR KING PIN 1 ID INDEX AR EA BOTTOM VIEW TOP VIEW 0.20X45º SIDE VIEW RECOMMENDED LAND PATTERN NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-303. 4) DRAWING IS NOT TO SCALE. RECOMMENDED STENCIL DESIGN MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 13 MP86956 – INTELLI-PHASE SOLUTION IN 5X6MM LGA AND TLGA Revision History Revision # 1.1 Revision Date  4/27/2020 1.2 07/10/2020 1.3 07/20/2020 Description Remove all TLGA information Update the descriptions for pin 32 Add (VIN to VPHASE) to Absolute Maximum Ratings Update the typical NOCP LS off time to 200ns Update the typical minimum PWM pulse width to 30ns Revise Typical Characteristics for threshold of EN Revise the figure of temperature sense utilization for multi-phase operation Correct the BST capacitor’s capacitance to 0.22uF Update the recommended Land Pattern and Stencil Design Add TLGA information Pages Updated Page1-13 P3 P3 P4 P4 P6 P10 P11 P12 Page1-13 NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP86956 Rev. 1.3 7/21/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 14