MP86957GMJ-P

MP86957 TM Intelli-Phase Solution (Integrated HS/LS-FETs and Driver) in 5mmx6mm LGA DESCRIPTION FEATURES The MP86957 is a monolithic half-bridge with built-in internal power MOSFETs and gate drivers. It achieves 70A of continuous output current over a wide input supply range.         The MP86957 is a monolithic IC approach that can drive up to 70A per phase. Integration of drivers and MOSFETs results in high efficiency due to optimal dead time and parasitic inductance reduction. This small 5mmx6mm LGA device can operate from 100kHz to 3MHz. The MP86957 offers many features to simplify system design. This device works through controllers with a tri-state PWM signal. It also comes with Accu-SenseTM current sense to monitor the inductor current, and temperature sense to report junction temperature. The MP86957 is ideal for server applications where efficiency and small size are at a premium.  Wide 3V to 16V Operating Input Range 70A Output Current Current Sense: Accu-SenseTM Temperature Sense Accepts Tri-State PWM Signal Current Limit Fault Flag Over-Temperature Fault Flag Low-Side Catastrophic Fault Flag and Protection Available in a 5mmx6mm LGA Package APPLICATIONS    Server Core Voltage Graphic Card Core Regulators Power Modules All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are registered trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION 3.3V VDRV VDD MP86957 VIN Intelli-Phase VIN AGND BST PWM EN IOUT TOUT/FLT MP86957 Rev. 1.1 7/10/2020 PWM SW VOUT EN IOUT TOUT/FLT PGND PGND www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 1 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA ORDERING INFORMATION * Part Number MP86957GMJ Package LGA-41 (5mmx6mm) Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP86957GMJ–Z). TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP86957: Part number LLLLLLL: Lot number PACKAGE REFERENCE NC 1 AGND 2 VDD 3 VDRV 4 PGND 5 NC 6 BST PHASE NC VIN 36 EN 37 PWM 38 NC IOUT 39 TOUT/FLT NC TOP VIEW 35 34 33 32 31 30 29 PGND 40 MP86957 Rev. 1.1 7/10/2020 12 13 14 15 16 17 SW 18 VIN 27 VIN 26 VIN 25 VIN 24 PGND 23 PGND 22 PGND 21 PGND 20 PGND 19 SW 11 SW 10 SW 9 SW PGND SW 8 SW PGND SW 7 SW PGND 41 SW NC VIN 28 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 2 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA PIN FUNCTIONS Pin # 1, 6, 31, 37, 39, 41 2 AGND 3 VDD 4 VDRV 5, 7, 8, 9, 20, 21, 22, 23, 24, 40 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 25, 26, 27, 28, 29, 30 Name NC PGND SW VIN Description No connection. Analog ground. Supply voltage for internal circuitry. Connect to the VDRV pin through a 2.2Ω resistor and decouple with a 1µF capacitor to AGND. Connect AGND and PGND at the VDD capacitor. Driver voltage. Connect to 3.3V supply and decouple with a 1µF to 4.7µF ceramic capacitor. Power ground. Phase node. Input supply voltage. Place input ceramic capacitors (CIN) close to the device to support the switching current with minimal parasitic inductance. Switching node for bootstrap capacitor connection. PHASE pin is connected to SW internally. Bootstrap. Requires a 0.1µF to 0.22µF capacitor to drive the power switch’s gate above the supply voltage. Connect the capacitor between PHASE and BST to form a floating supply across the power switch driver. 32 PHASE 33 BST 34 PWM 35 EN 36 TOUT/FLT Single-pin temperature sense and fault reporting. When a fault occurs, the pin is pulled up to the VDD voltage. 38 IOUT Current sense output. Use an external resistor to adjust the voltage proportional to the inductor current. MP86957 Rev. 1.1 7/10/2020 Pulse-width modulation input. Leave PWM floating or drive to mid-state to put SW in high-impedance state. Enable. Pull low to disable the device and place SW in a high-impedance state. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 3 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA θJB θJC_TOP ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (3) Supply voltage (VIN) ..................................... 18V VIN to VPHASE (DC).............................. -0.3V to 25V VIN to VPHASE (10ns) ............................... -5V to 32V VSW to PGND(DC)................... -0.3 V to VIN + 0.3V VSW to PGND(25ns) ............................... -5V to 25V VBST .................................................. VPHASE + 4V VDD, VDRV ........................................ -0.3V to +4V All other pins ........................ -0.3V to VDD + 0.3V Instantaneous current ................................ 95A Junction temperature ................................150°C Lead temperature .....................................260°C Storage temperature ............... -65°C to +150°C LGA- 41 (5mmx6mm) .............2.2 ..... 8.7...C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) θJB: Thermal resistance from junction to board around PGND soldering point. θJC_TOP: Thermal resistance from junction to top of package. Recommended Operating Conditions (2) Supply voltage (VIN) ......................... 3.0V to 16V Driver voltage (VDRV) ....................... 3.0V to 3.6V Logic voltage (VDD).......................... 3.0V to 3.6V Operating junction temp (TJ). .. -40°C to +125°C MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 4 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA ELECTRICAL CHARACTERISTICS VIN = 12V, VDRV = VDD = EN = 3.3V; TA = 25°C for typical value and TJ = -40°C to +125°C for max and min values, unless otherwise noted. Parameter IIN shutdown VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold hysteresis IVDRV quiescent current IVDD quiescent current VDD voltage UVLO rising VDD voltage UVLO hysteresis High-side current limit (4) Symbol Condition EN = low PWM = low PWM = low ILIM_FLT Cycle-by-cycle up to 8 cycles Low-side current limit tolerance (4) Negative current limit low-side off time (4) High-side current limit fault flag counter (4) High-side current limit fault flag clear counter (4) Dead time at SW rising (4) MP86957 Rev. 1.1 7/10/2020 2.5 3.0 V mV 350 2.95 95 A -40 A +15% 200 ns 8 times 4 times 2 ns Positive inductor current 6 ns Negative inductor current 28 ns 20 20 40 30 40 30 30 0 5 V V ns ns ns ns ns ns ns % μA/A 2.30 0.8 tRising tFalling tLT tTL tHT tTH 20A ≤ ISW ≤ 70A GIOUT μA mA V mV +15% -15% (4) Minimum PWM pulse width (4) IOUT sense gain accuracy (4) IOUT sense gain Units μA 250 3 2.75 300 Negative current limit, cycle-by-cycle, no fault report PWM tri-state to SW Hi-Z delay (4) Max 180 -15% Low-side current limit (4) EN input high threshold voltage EN input low threshold voltage PWM high to SW rising delay (4) PWM low to SW falling delay (4) Typ 90 450 High-side current limit tolerance (4) Dead time at SW falling Min -2 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. +2 5 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, VDRV = VDD = EN = 3.3V; TA = 25°C for typical value and TJ = -40°C to +125°C for max and min values, unless otherwise noted. Parameter Symbol ISW = 0A, VIOUT = 1.2V, TJ = 25°C EN = low, VIOUT = 1.2V IOUT sense offset IOUT pin voltage range (4) TOUT/FLT sense gain (4) TOUT/FLT sense offset (4) Over-temperature fault flag (4) Over-temperature fault tolerance (4) Over-temperature fault hysteresis (4) TOUT/FLT when fault (4) Condition VIOUT Min Typ Max Units -2 0 2 μA -1 0.7 0 1 2.1 μA V mV/°C mV °C 8 800 145 TJ = 25°C -10% 3.0 Pull up, EN = high Pull down, EN = high PWM resistor PWM logic high voltage PWM tri-state region PWM logic low voltage +10% 12 3.3 6 5 2.30 1.10 1.80 0.80 °C V kΩ kΩ V V V Note: 4) Guaranteed by design or characterization data, not tested in production. MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 6 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA PWM TIMING DIAGRAM PWM SW Hi-Z tRising tFalling tLT Hi-Z tHT tTH tTL Figure 1: PWM Timing Diagram MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 7 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA TYPICAL CHARACTERISTICS Efficiency and Loss VDD UVLO 18 96% 16 94% 14 92% 12 90% 10 MP86957 (1.2V) 88% 8 MP86957 (1.8V) 86% 6 84% 4 82% 2 80% 3 VDD UVLO THRESHOLD (v) 98% LOSS (W) EFFICIENCY VIN = 12V, L = 150nH, fSW = 500kHz 2.9 2.8 2.7 2.6 2.4 2.3 0 -50 0 5 10 15 20 25 30 35 40 45 50 55 60 OUTPUT CURRENT (A) 0 50 100 150 TEMPERATURE (℃) EN_HI PWM_LO 2 1.5 PWM_LO THRESHOLD (v) EN_Hi THRESHOLD (v) VDD rising VDD falling 2.5 1.9 1.8 1.7 1.6 EN_Hi rising 1.5 EN_Hi falling 1.4 1.3 1.2 1.3 1.1 0.9 PWM_Lo rising 0.7 PWM_Lo falling 0.5 -50 0 50 100 150 TEMPERATURE (℃) -50 0 50 100 TEMPERATURE (℃) 150 PWM_HI PWM_Hi THRESHOLD (v) 2.3 PWM_Hi rising 2.2 PWM_Hi falling 2.1 2 1.9 1.8 -50 0 50 100 150 TEMPERATURE (℃) MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 8 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA TYPICAL PERFORMANCE CHARACTERISTICS Switching Dead Time @ SW Ringing VIN=12V, VOUT=1.8V, L=100nH, fSW=800kHz, Load=30A Load = 30A . CH1: VSW 1V/div. CH1: VSW 4V/div. 100ns/div. 2ns/div. IOUT Output IOUT Output Load = 0A Load = 30A CH3: VIOUT 200mV/div. CH3: VIOUT 200mV/div. CH1: VSW 5V/div. CH1: VSW 5V/div. 400ns/div. MP86957 Rev. 1.1 7/10/2020 400ns/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 9 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA FUNCTIONAL BLOCK DIAGRAM VDD RDY VDRV UVLO BST VIN VIN VDD 6k HS Current Limit PWM 5k Level Shift HS Current Limit HS-FET VIN SW SW HS ON Inductor Current Crossed Zero Control Logic EN ZCD SW PGND VDRV LS ON Negative Current Limit AGND Temperature Sense & Fault Indicator Current Sense TOUT/FLT IOUT LS-FET Negative Current Limit SW PGND SW PGND PGND Figure 2: Functional Block Diagram MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 10 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA OPERATION The MP86957 is a 70A, monolithic half-bridge driver with MOSFETs ideally suited for multiphase buck regulators. An external 3.3V is required to supply both VDD and VDRV. When EN transitions from low to high and the VDD and VDRV signals are sufficiently high, operation begins. MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 11 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA APPLICATION INFORMATION PWM The PWM input pin is capable of tri-state input. When the PWM input signal is within the tri-state threshold window for 40ns (typical), THT or TLT, the high-side MOSFET (HS-FET) turns off immediately and the low-side MOSFET (LS-FET) remains in diode emulation mode until zero current detection. The tri-state PWM input can be from a forced middle voltage PWM signal. Alternately, the PWM input can be floated and the internal current source will charge the signal to a middle voltage. The PWM timing diagram shows the propagation delay definition from PWM to the SW node (see Figure 1). Place a resistor divider (e.g. 1.2kΩ to VDD and 1kΩ to GND) at the PWM pin to anticipate when the controller’s PWM tri-state enters Hi-Z (High impedance) mode. This function prevents the LS-FET from turning on if the TOUT/FLT signal is pulled up after a fault occurs and the controller responds the fault and shuts down by placing PWM to HiZ mode. The PWM pin does not require a resistor divider if the controller’s PWM tri-state is at a middle voltage. Diode Emulation Mode In diode emulation mode, when PWM is at either low or tri-state input, the LS-FET turns on whenever the inductor current is positive. The LS-FET is off if the inductor current is negative or after it has crossed zero current. Diode emulation mode can be enabled by: 1. Driving PWM to middle state 2. Floating the PWM pin Current Sense The IOUT pin is a bi-directional current source proportional to the inductor current. The current sensing gain is 5μA/A, and a resistor is used to program the voltage gain proportional to the inductor current if needed. The IOUT pin output has two states (see Table 1). In disable mode (EN = low), the current sense circuit is disabled and IOUT is in Hi-Z (highimpedance) state. MP86957 Rev. 1.1 7/10/2020 Table 1: IOUT Output States PWM EN IOUT PWM High Active x Low Hi-Z The IOUT pin voltage range of 0.7V to 2.1V is required to get IOUT’s accurate current output. In general, there is a resistor (RIOUT) connected from IOUT to an external voltage, which is capable of sinking a small current to provide enough voltage to meet the required operating voltage range. Determine a proper reference voltage (VCM) and/or RIOUT value using Equation (1) and Equation (2): 0.7V  IIOUT  RIOUT  VCM  2.1V (1) IIOUT  ISW  GIOUT (2) Where VCM is a reference voltage connected to RIOUT. The Intelli-PhaseTM current sense output can be used to accurately monitor the output current. The cycle-by-cycle current information from IOUT can be used for phase current balancing, over-current protection, and active voltage positioning (output voltage droop). Positive and Negative Inductor Current Limit When HS-FET over-current is detected, the HSFET on-pulse is truncated for that PWM cycle. If an HS current limit event is detected for eight consecutive cycles, the TOUT/FLT pin is pulled high to VDD, during which time the driver continues responding to PWM. Once four consecutive normal cycles are detected, TOUT/FLT is cleared. When the LS-FET detects a -40A valley current, the part turns off the LS-FET and turns on the HS-FET for 200ns to limit the negative current. The LS-FET negative current limit will not trigger a fault report. Over-Temperature Fault Flag If the junction temperature rises above 145°C, TOUT/FLT is pulled to VDD, during which time the driver continues responding to PWM. Once the junction temperature falls below 133°C, the fault flag clears. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 12 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA Low-Side Catastrophic Failure Protection If the HS-FET VDS is greater than 0.7V when the HS-FET is on, the low-side catastrophic failure protection is triggered. The MP86957 stops responding to PWM and latches, and TOUT/FLT is pulled high immediately. After 200ns, the PWM impedance becomes 10k to GND. The MPS multiphase controller can detect this impedance and record which phase experiences this failure. This fault latch can be released by toggling EN or recycling VDD/VIN. Temperature Sense Output with Fault Indicator (TOUT/FLT) TOUT/FLT reports junction temperature. It sources a voltage proportional to the junction temperature when VDD is higher than the UVLO threshold. The gain is 8mV/°C, and the offset is +800mV at 25°C. TOUT pins from multi-phase topologies can be tied together to report the highest TMON signals to the controller. TOUT/FLT are pulled to VDD when a fault event is detected. It reports three fault events: HS-FET over-current limit, over-temperature, low-side catastrophic failure. For multiphase operation, connect TOUT/FLT of each Intelli-PhaseTM together (see Figure 3). Intelli-PhaseTM Power Stage VIN VIN IntelliPhase TM L2 VOUT TOUT/FLT Multiphase Controller COUT PWM VIN VIN IntelliPhase TM 1. Place the input MLCC capacitors as close to VIN and PGND as possible. The major MLCC capacitors should be placed on the same layer as the MP86957. 2. Place as many VIN and PGND vias underneath the package as possible, inbetween VIN or PGND long pads. 3. Place a VIN copper plane on the second inner layer to form the PCB stacking in a +//+ pattern to reduce the parasitic impedance from the input MLCC cap to the MP86957. The copper plane on inner layer must at least cover the VIN vias underneath the package and the input MLCC capacitors. 4. Place more PGND vias close to the PGND pin/pad to minimize parasitic resistance and impedance, as well as thermal resistance. 5. Place the BST and VDRV capacitors as close to the device’s pins as possible. Use a ≥20 mil width trace to route the path. Avoid the via for the BST driving path. It is recommended to use 0.1µF to 0.22µF for the bootstrap capacitor. 6. Place the VDD decoupling capacitor close to the device. Connect AGND and PGND at the point of the VDD capacitor’s ground connection. 7. Keep the IOUT signal trace away from highcurrent paths, such as SW and PWM. PWM2 Temperature ADC PCB Layout Guidelines PCB layout plays an important role in achieving stable operation. For optimal performance, refer to Figure 4 and follow the guidelines below: L1 TOUT/FLT PWM PWM1 Figure 3: Multiphase Temperature Sense Utilization MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 13 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA PGND VDRV VDD AGND NC 6 5 4 3 2 1 7 NC PGND IOUT 33 32 31 NC 30 34 SW SW 19 35 PHASE 18 36 BST SW 17 37 PGND 40 SW 16 PWM SW 15 EN SW 14 NC TOUT/FLT SW 13 40 PGND NC 38 41 39 41 12 NC 11 SW 8 9 10 SW PGND PGND SW VIN 29 VIN 29 28 VIN 28 27 VIN 27 26 VIN 26 25 VIN 25 24 24 PGND 23 23 PGND 22 22 PGND 21 21 PGND 20 20 PGND Figure 4: Example of PCB Layout (Placement & Top layer PCB) Input Capacitor: 0805 package (top side & bottom side) & 0402 package (Top side) Inductor: 11x8 package VDD/BST/VDRV Capacitor: 0402 package Via Size: 20/10 mils MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 14 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA PACKAGE INFORMATION LGA-41 (5mmx6mm) MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 15 MP86957 – INTELLI-PHASETM SOLUTION IN 5MMX6MM LGA Revision History Revision # 1.0 1.1 Revision Date 05/08/2019 07/08/2020 Description Initial Release Update the descriptions for pin 32. Add (VIN to VPHASE) to Absolute Maximum Ratings Update recommended operating conditions for VIN from 3.0V to 16V Update the typical dead-time for negative inductor current at SW falling edge to 28ns Update the typical propagation delay from PWM to SW Update the typical minimum PWM pulse width to 30ns Add Typical Characteristics for threshold of EN, PWM and VDD UVLO Update typical performance characteristics Update the application information for PWM section Update Figure 3 Correct the BST capacitor’s capacitance to 0.22μF Update the recommended Land Pattern and Stencil Design Add revision history page Pages Updated 3 4 4 5 5 5 8 9 12 13 13 15 16 NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP86957 Rev. 1.1 7/10/2020 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 16