MP86963DUT-LF-Z

MP86963 High Efficiency, 20A, 27V Intelli-PhaseTM Solution (Integrated HS/LS FETs and Driver) in a 5x5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 DESCRIPTION FEATURES The MP86963 is a monolithic Half Bridge with built-in internal power MOSFETs and gate driver. It achieves 20A continuous output current over a wide input supply range. • • • • • • • • Integrating the Driver and MOSFETs results in high efficiency due to optimal dead time control and parasitic inductance reduction. The MP86963 is a Monolithic IC designed to drive up to 20A per phase. Housed in a very small 5x5mm TQFN Package, this device can be operated from 100kHz to 1MHz operation. The IC is intended to work with 3.3V tri-state output controllers. The MP86963 is ideal for notebook applications where efficiency and small size are a premium. Wide 4.5V to 21V Operating Input Range 20A Output Current Simple Logic Interface (3.3V) Operate from 100kHz to 1MHz Accepts 3-state PWM Input Suitable for single-/multi-phase operation Available in a 5mm x 5mm TQFN Package ROHS6 Compliant APPLICATIONS • • • Power modules Notebook, Core Voltage Graphic Card Core Regulators All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. This Product is Patent Pending. TYPICAL APPLICATION MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 1 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 ORDERING INFORMATION Part Number* Package Top Marking Free Air Temperature(T A) MP86963DUT 5x5 TQFN 86963UT -40C to +85C * For Tape & Reel, add suffix –Z (e.g. MP86963DUT–Z); For RoHS compliant packaging, add suffix –LF (e.g. MP86963DUT–LF–Z) PACKAGE REFERENCE ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) Supply Voltage VIN .......................................27V VSW (DC) ................................-0.3V to VIN +0.3V VSW (20ns) ....................................-3V to VIN +3V VBST......................................................VSW + 6V All Other Pins ................................. -0.3V to +6V Continuous Power Dissipation (TA = +25°C) (2) ............................................................3.8W Junction Temperature .............................. 150C Lead Temperature ................................... 260C Storage Temperature ............... -65C to +150C Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(T J(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. Recommended Operating Conditions θJA θJC 5x5 TQFN .............................. 33 ....... 8 .... C/W (3) Supply Voltage VIN .......................... 4.5V to 21V VCC Driver Voltage………………….4.5V to 5.5V Operating Junct. Temp (TJ) ...... -40C to +125C MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 2 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25C, unless otherwise noted. Parameters ICC Standby IIN (Shutdown) IIN Standby Rise Time Fall Time Minimum On-Time Dead-Time Rising Dead-Time Falling Symbol ICC_Stdby IIN (Off) IIN_Stdby Condition VCC =5V, PWM=EN=LO VCC = 0V VCC =5V, PWM=EN=LO IOUT = 20A IOUT = 20A Min VCC Under Voltage Lockout Threshold Rising VCC Under Voltage Lockout Threshold Hysteresis SYNC Pull-Up Current SYNC Logic High Voltage SYNC Logic Low Voltage EN Input Low Voltage En Input High Voltage PWM Input Input Current ISYNC SYNC=0V Typ 550 1 1 5 3 55 5 10 Max 610 5 Units μA μA μA ns ns ns ns ns 3.7 4.2 V 470 mV -14 μA V V V V 2 0.4 0.4 2 IPWM VPWM=3.3V VPWM=0V VCCIO PWM Low to Tri-State Threshold PWM Tri-State to High Threshold PWM High to Tri-State Threshold PWM Tri-State to Low Threshold 2.9 Tri-State Shutdown Holdoff Time tTSSHD UG/LG Three-State Propagation Delay USW Turn-Off Propagation Delay LSW Turn-Off Propagation Delay USW Turn-On Propagation Delay LSW Turn-On Propagation Delay tPTS tPDUL tPDLL tPDUH tPDLH VCC=5V, Temperature=25°C VCC=5V VCC=5V VCC=5V VCC=5V 370 -370 3.3 1.10 2.25 2.10 0.75 3.6 μA μA V V V V V 100 ns 20 40 25 30 50 ns ns ns ns ns MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 3 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 Figure 1—Timing Diagram PIN FUNCTIONS Pin # 1 2 3 Name NC VCC AGND 4 EN 5 SYNC 6 PWM 7 VCC IO 8 BST 9 Exposed Pad 10–18 Exposed Pad Exposed Pad IN GND SW Description Not Connected. Low-Side Driver Bias Supply. Decouple with a 1µF ceramic capacitor. Signal Ground. Active High On/Off Control. Pulling this Pin Low forces the SW Pin to be in a high impedance state. Leaving this pin Open enables theLower Synchronous Switch. Pulling it Low forces the Lower Switch into Diode Emulation mode. Pulse Width Modulation Control. Accepts three-state input. Force PWM to midstate or open to place SW into high impedance state. Reference voltage that connects to PWM driver supply. Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply voltage. It is connected between SW and BST pins to form a floating supply across the power switch driver. Supply Voltage. CIN is needed to prevent large voltage spikes from appearing at the input. Power Ground. Switch Output. These pins are fused together. MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 4 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VCC = 5V, VOUT = 1.2V, T A = +25ºC, unless otherwise noted. MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 5 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VCC = 5V, VOUT = 1.2V, T A = +25ºC, unless otherwise noted. MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 6 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 EFFICIENCY MEASUREMENT SETUP MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 7 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 BLOCK DIAGRAM Figure 2—Function Block Diagram MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 8 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 OPERATION The MP86963 is a 20A Monolithic Half Bridge driver with MOSFETs ideally suited for single/multi-phase Buck regulators. Once the EN, VIN, VCCIO, VCC and VBST signals are sufficiently high, operation begins. BST voltage has a typical rising UVLO of 2.2V and a falling UVLO of 2.0V. When BST is below the UVLO voltage, the device will be off. MP86963 can work with most PWM controllers. The device accepts PWM signal from 100kHz up to 1MHz. There is an internal resistor divider to put PWM voltage to tri-state region if the PWM pin is open. 3) The recommended external BST cap is 100nF. Do not use a capacitance value lower than 100nF. Place a 1.0Ω resistor between the BST capacitor and BST pin for optimized performance. 4) Do not place via on the pad or on the pin footprint. Doing so may cause soldering issue during the assembling process. Use Figure 3 as a via placement reference. 5) Connect IN, SW and GND to large copper area and use vias to cool the chip to improve thermal performance and long-term reliability. See Figure 4 as an example. Internally, SYNC is tied to VCC through a resistor. By default, the device will operate in synchronous mode. To enter Diode Emulation mode, drive SYNC pin LOW. Startup and Shutdown Sequence MP86963 can work with any startup or shutdown sequencing combination of VIN, VCC, VCCIO and EN. If PWM signal is present, the MP86963 will start working whenever VIN, VCC, VCCIO and EN are ready. On the other hand, if any of these signals is not ready, the MP86963 will stop working. However, it is recommended to turn on and turn off the device through the EN pin. PCB Layout Guideline PCB layout is very important to achieve stable operation. Please follow these guidelines to achieve optimal performance. 1) Keep the path of switching current short and minimize the loop area formed by input capacitor. Keep the connection between SW pin and input power ground as short and wide as possible. 2) Always place some input bypass ceramic capacitors next to the device and on the same layer as the device. Do not put all of the input bypass capacitors on the back side of the device. Use as many vias and input voltage planes as possible to reduce the switching spike. BST capacitor and VCC capacitor should also be as close to the device as possible. Figure 3—Via Placement Guideline Do not put via on the device’s pad footprint or pin footprint to avoid assembly issue. Use as many vias as possible to cool down the device. 6) Place the VCC decouple capacitor close to the IC. Connect AGND and PGND at the point of VCC capacitor's ground connection. Recommended SMT Setting Stencil thickness: 0.12mm EP Pad Opening: (Stencil opening : Real PCB Size) Length: 0.85:1 Width: 1:1 Note: The EP pad for Intelli-Phase are IN, SW and GND pad on the bottom. Solder type: #3 MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 9 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 CVCC RBST CBST Input Capacitors (SW Plane) (Vin Plane) Intelli Phase Inductor (GND Plane) Output Capacitors Figure 4—Copper Area Guideline Use large copper area, many vias and many IN, SW and GND inner layer planes to achieve optimal thermal performance. MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 10 MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN PATENTS PENDING – CONTROLLED DOCUMENT 00000 END OF LIFE, REFER TO MP86901 PACKAGE INFORMATION FCTQFN18L (EXPOSED PAD) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP86963 Rev.1.22 www.MonolithicPower.com 8/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 11