MP86972GLJTH-Z

MP86972 60A, Intelli-Phase SolutionTM with Integrated HS-FETs, LS-FETs, and Driver in a TLGA-35 (3mmx6mm) Package DESCRIPTION FEATURES The MP86972 is a monolithic half-bridge driver with built-in internal power MOSFETs and gate drivers. It achieves 60A of continuous output current across a wide input supply range.          The device can drive up to 60A per phase. The integrated drivers and MOSFETs result in high efficiency due to an optimal dead time and reduced parasitic inductance. The device operates from 100kHz to 3MHz. The MP86972 offers many features to simplify system design, and works with controllers with a tri-state PWM signal. It also comes with an accurate current sense to monitor the inductor current, and temperature sense to report junction temperature. MP86972 is ideal for server applications where efficiency and small size are a premium. The device is available in a TLGA-35 (3mmx6mm) package. Wide 3V to 12V Operating Input Range 60A Output Current Accu-SenseTM Current Sense Temperature Sense Accepts Tri-State PWM Signal Current-Limit Protection Over-Temperature Protection (OTP) Fault Reporting Available in a TLGA (3mmx6mm) Package APPLICATIONS    Server Core Voltages Graphic Card Core Regulators Power Modules All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. TYPICAL APPLICATION VDRV VDD AGND MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 1 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE ORDERING INFORMATION Part Number Package Top Marking MSL Rating MP86972GLJTH* TLGA-35 (3mmx6mm) See Below 3 * For Tape & Reel, add suffix -Z (e.g. MP86972GLJTH-Z). TOP MARKING MP: MPS prefix Y: Year code W: Week code 86972: First five digits of the part number LLL: Lot number TH: Thin package PACKAGE REFERENCE VTEMP/ FLT 1 SW 2 SW 3 CS SYNC PWM 29 AGND 30 VDD BST TOP VIEW 28 27 26 25 31 VIN 32 35 SW VIN 24 VIN 23 VIN 22 VIN SW 4 21 VIN SW 5 20 PGND SW 6 19 PGND SW 7 18 PGND SW 8 17 PGND 9 16 PGND 10 11 12 13 14 15 SW SW VDRV PGND PGND 34 PGND SW SW 33 SW TLGA-35 (3mmx6mm) MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 2 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE PIN FUNCTIONS Pin # 1 Name Description Single-pin temperature sense and fault reporting. If a fault occurs, this pin is pulled VTEMP/FLT up to 3.3V. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 32, 33 SW 13 VDRV Driver voltage. Connect VDRV to a 3.3V supply and decouple it with a 1µF to 4.7µF ceramic capacitor. PGND Power ground. 14, 15, 16, 17, 18, 19, 20, 34 21, 22, 23, 24, 31, 35 VIN 25 PWM 26 SYNC 27 CS 28 AGND 29 VDD 30 BST MP86972 Rev. 1.0 6/28/2021 Phase node. Supply voltage. Place a capacitor (CIN) close to the device to support the switching current and reduce voltage spikes at the input. Pulse-width modulation input. Float the PWM pin or drive it to a middle-state to put SW in a high impedance state. Diode emulation mode and standby mode selection. Float the SYNC pin or drive SYNC to a middle-state to enter standby mode. Pull SYNC high for continuous conduction mode (CCM). Pull SYNC low to enable diode emulation mode. Current-sense output. Use an external resistor to adjust the voltage so that it is proportional to the inductor current. Analog ground. Internal circuitry voltage. Connect VDD to VDRV via a 2.2Ω resistor. Decouple VDD with a 1µF capacitor connected to AGND. Connect AGND and PGND at the VDD capacitor. Bootstrap. BST requires a 0.1µF to 1µF capacitor to drive the power switch’s gate above the supply voltage. Connect the capacitor between the SW and BST pins to form a floating supply across the power switch driver. MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 3 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE θJB θJC_TOP ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (3) VIN to PGND................................. -0.3V to +16V VIN to VSW ..................................... -0.3V to +16V VIN to VSW (10ns) ..........................................22V VSW to PGND ............................... -0.3V to +14V VSW to PGND (25ns) ..................... -10V to +20V VBST .....................................................VSW + 4V VDD, VDRV........................................ -0.3V to +4V All other pins ........................ -0.3V to VDD + 0.3V Instantaneous current ................................95A Junction temperature ............................... 150°C Lead temperature .................................... 260°C Storage temperature ................ -65°C to +150°C TLGA-35 (3mmx6mm)...........2.2.......8.0....°C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) θJB: Thermal resistance from the junction to the board around the PGND soldering point. θJC_TOP: Thermal resistance from the junction to the top of the package. ESD Ratings Human body model (HBM) ........................ ±2kV Charged device model (CDM) ................. ±1.5kV Recommended Operating Conditions (2) Supply voltage (VIN) ........................... 3V to 12V Driver voltage (VDRV) ...................... 3.0V to 3.6V Logic voltage (VDD)......................... 3.0V to 3.6V Operating junction temp (TJ) .... -40°C to +125°C MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 4 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE ELECTRICAL CHARACTERISTICS VIN = 6V, VDRV = VDD = SYNC = 3.3V, TA = 25°C for typical values, TJ = -40°C to +125°C for maximum and minimum values, unless otherwise noted. Parameter Symbol IIN shutdown VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold hysteresis IVDRV quiescent current IIN_OFF Min SYNC = Hi-Z PWM = low ILIM_FLT Cycle by cycle up to 4 cycles Negative current limit, cycle by cycle, no fault report Positive inductor current Dead-time falling (4) Negative inductor current VDD = 3V VDD = 3.6V SYNC logic high voltage VDD = 3V VDD = 3.6V VDD = 3V VDD = 3.6V 180 μA 2.5 2.9 V mV 400 μA 2.9 mA V mV 90 A -30 A 200 ns 4 Times 2 ns 8 ns 35 ns V V 2.4 2.6 tRISING tFALLING 15 15 tLT tTL tHT tTH 40 50 40 50 ns ns ns ns SYNC logic low voltage MP86972 Rev. 1.0 6/28/2021 90 V V V V ns ns SYNC tri-state region (4) Units 3 2.75 250 Negative current limit low-side off time (4) High-side current limit shutdown counter (4) Dead-time rising (4) PWM tri-state to SW Hi-Z delay Max PWM = low Low-side current limit (4) PWM high to SW rising delay (4) PWM low to SW falling delay (4) Typ 450 IVDD quiescent current VDD voltage UVLO rising VDD voltage UVLO hysteresis High-side current limit (4) Condition 1.1 1.3 1.65 1.95 0.6 0.7 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 5 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE ELECTRICAL CHARACTERISTICS (continued) VIN = 6V, VDRV = VDD = SYNC = 3.3V, TA = 25°C for typical values, TJ = -40°C to +125°C for maximum and minimum values, unless otherwise noted. Parameter Symbol Condition Min Typ (4) Minimum PWM pulse width Current-sense gain accuracy (4) Max Units +2 ns % 20 20A ≤ ISW ≤ 60A -2 Current-sense gain μA/A 8 ISW = 0A, VCS = 1.2V, TJ = 25°C SW Hi-Z, VCS = 1.2V -2 +2 μA -1 0.7 +1 2.1 10 -100 μA V mV/°C mV Over-temperature shutdown and fault flag (4) 160 °C VTEMP/FLT if a fault occurs (4) VDD V 6 kΩ 5 1.8 1.8 0.8 kΩ V V V V V 0.8 V Current-sense offset (4) CS voltage range VTEMP/FLT sense gain (4) VTEMP/FLT sense offset (4) VCS TJ = 25°C Pull-up, SYNC= low or high Pull down VDD = 3V VDD = 3.6V VDD = 3V VDD = 3.6V VDD = 3V PWM resistor PWM logic high voltage PWM tri-state region PWM logic low voltage 2.4 2.4 1.1 1.1 VDD = 3.6V Notes: 4) Guaranteed by design or characterization data. Not tested in production. PWM TIMING DIAGRAM PWM SW Hi-Z tRISING tFALLING tLT tHT tTH MP86972 Rev. 1.0 6/28/2021 Hi-Z tTL MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 6 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE TYPICAL CHARACTERISTICS Efficiency VDD UVLO THRESHOLD (V) 96 94 EFFICIENCY (%) VDD UVLO Threshold vs. Temperature VIN = 6V, L = 50nH, fSW = 1MHz 92 90 88 86 84 MP86972 0.8V 82 MP86972 1.2V 80 0 20 40 OUTPUT CURRENT (A) 3 VDD rising 2.9 VDD falling 2.8 2.7 2.6 2.5 2.4 2.3 -50 60 1.3 SYNC_LO rising 1.2 SYNC_LO falling 1.1 1 0.9 0.8 0.7 0.6 -50 0 50 100 TEMPERATURE ( C) PWM_LO falling 1 0.9 0.8 0.7 0.6 -50 MP86972 Rev. 1.0 6/28/2021 0 50 100 TEMPERATURE ( C) 150 SYNC_HI falling 2.3 2.2 2.1 2 1.9 1.8 -50 PWM HIGH THRESHOLD (V) PWM LOW THRESHOLD (V) PWM_LO rising SYNC_HI rising 2.4 150 1.3 1.1 150 2.5 PWM Low Threshold vs. Temperature 1.2 50 100 TEMPERATURE ( C) SYNC High Threshold vs. Temperature SYNC HIGH THRESHOLD (V) SYNC LOW THRESHOLD (V) SYNC Low Threshold vs. Temperature 0 2.5 0 50 100 TEMPERATURE ( C) 150 PWM High Threshold vs. Temperature PWM_HI rising 2.4 PWM_HI falling 2.3 2.2 2.1 2 1.9 1.8 -50 0 50 100 TEMPERATURE ( C) MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 150 7 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE TYPICAL PERFORMANCE CHARACTERISTICS Switching Waveform Dead Time at SW Rising VIN = 6V,L = 50nH, IOUT = 30A IOUT = 30A CH3: VSW 0.3V/div. CH3: VSW 2V/div. 100ns/div. 2.5ns/div. CS Output Waveform CS Output Waveform IOUT = 0A IOUT = 30A CH1: VIOUT 300mV/div. CH1: VIOUT 300mV/div. CH3: VSW 5V/div. CH3: VSW 5V/div. 500ns/div. 500ns/div. High-Side Current Limit CH1: VFAULT 5V/div. CH2: VSW 10V/div. CH2: IL 20A/div CH1: PWM 5V/div. 2µs/div. MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 8 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE FUNCTIONAL BLOCK DIAGRAM VDD RDY UVLO VDRV BST VIN VIN VDD 6kΩ HS Current Limit PWM 5kΩ Level Shift HS Current Limit HS-FET VIN SW SW HS On Inductor Current Crossed Zero Control Logic SYNC ZCD SW PGND VDRV LS On Negative Current Limit AGND Temperature Sense and Fault Indicator Current Sense VTEMP/FLT CS LS-FET Negative Current Limit SW PGND SW PGND PGND Figure 1: Functional Block Diagram MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 9 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE OPERATION The MP86972 is a 60A, monolithic half-bridge driver with MOSFETs. It is well-suited for multiphase buck regulators. An external 3.3V is required to supply both VDD and VDRV. When the VIN and VDD signals are sufficiently high, operation begins. PWM The PWM input pin is capable of tri-state input. If the PWM input signal is within the tri-state threshold window for about 50ns (tHL or tLT), the high-side MOSFET (HS-FET) turns off immediately. The low-side MOSFET (LS-FET) enters diode emulation mode, and stays on until zero-current detection (ZCD). The tri-state PWM input is enabled by forcing a middle-voltage PWM signal, or by floating the PWM input. The internal current source charges the signal to a middle voltage. See the PWM Timing Diagram on page 6 to define the propagation delay from PWM to the SW node. Standby Mode When the SYNC pin is floating or forced to a middle-state voltage for 2µs, the MP86972 enters standby mode. While in standby mode, the MP86972 shuts down, and both the CS and VTEMP/FLT outputs are disabled. The fault (VTEMP/FLT) latch is not be reset by entering standby mode. The CS output has two states (see Table 1). In standby mode, the CS circuit is disabled. It takes the device 40µs to exit standby mode and enter active mode. Table 1: CS Output States PWM SYNC CS PWM High Active PWM Low Active x Hi-Z (or middle) Standby To obtain an accurate CS output up to +480μA/240μA (e.g. +60A/-30A), the CS pin’s voltage must be between 0.7V and 2.1V. Generally, there is a resistor (RCS) connected from the CS pin to an external voltage that is capable of sinking small currents. This provides a sufficient voltage level to meet the required operating voltage range. Choose a value for RCS to determine a proper reference voltage (VCM). The relationship between RCS and VCM can be calculated with Equation (1): 0.7V  ICS  R CS  VCM  2.1V (1) Where VCM is a reference voltage connected to RCS, and ICS can be estimated with Equation (2): ICS  IL  GCS (2) Diode Emulation Mode When PWM is low or in tri-state input in diode emulation mode, the LS-FET turns on when the inductor current is positive. The LS-FET turns off if the inductor current reaches 0A or becomes negative. There are three ways to enable diode emulation mode, listed below: The Intelli-Phase’sTM current-sense output can be used by the controller to accurately monitor the output current. The cycle-by-cycle current information from the CS pin can be used for phase current balancing, over-current protection, and active voltage positioning (output voltage droop).    Positive and Negative Inductor Current limit If an over-current (OC) condition is detected on the HS-FET, the HS-FET turns off for that PWM cycle. If the OC conditions lasts four consecutive cycles, the HS-FET latches off, VTEMP/FLT is pulled up to VDD, and the LS-FET turns on, and stays on until ZCD. To release the latch and restart the device, power must be cycled on VIN or VDD. Pull the SYNC pin low. Drive the PWM pin to s middle-state. Float the PWM pin. Current Sense (CS) CS is a bidirectional current source that is proportional to the inductor current. The currentsense gain is 8μA/A. If required, a resistor can be used to configure the voltage gain proportional to the inductor current. If the LS-FET detects a -30A current, the part turns off the LS-FET for 200ns to limit the MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 10 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE negative current. The LS-FET’s negative current limit does not trigger a fault report. Temperature-Sense Output with Fault Indication (VTEMP/FLT) The VTEMP/FLT pin can sense the junction temperature or indicate if certain faults have occurred. Junction Temperature Sense When VDD exceeds its under-voltage lockout (UVLO) threshold and the part is in active mode, the VTEMP/FLT pin has an output voltage that is proportional to the junction temperature. The gain is 10mV/°C, and it has a -100mV offset at 25°C. For example, the voltage is 0V when TJ < 10°C, 0.15V when TJ = 25°C, and 0.9V when TJ = 100°C. Fault Indication If any fault occurs, VTEMP/FLT is typically pulled up to 3.3V (or a 3.0V minimum) to report the fault event, regardless of the temperature. After the fault occurs for 200ns, the PWM impedance changes according to the fault type. Table 2 lists how the PWM status changes for each fault type. Table 2: PWM Resistance if a Fault Occurs Fault Type PWM Current-limit protection Over-temperature protection SW-to-PGND short protection 10kΩ to AGND 20kΩ to AGND 1kΩ to VDD The three fault events are described below: 1. Over-current limit: The current limit fault condition must remain for eight consecutive cycles to trigger this fault. If this fault occurs, the part latches off to turn off the HS-FET. The LS-FET turns on and stays on until the current reaches 0A. The PWM pin is pulled to GND through a 10kΩ resistor to indicate this fault type. 2. Over-temperature fault when TJ > 160°C: If an over-temperature fault occurs, the part latches off, and the HS-FET turns off. The LS-FET turns on and stays on until the current reaches 0A. The PWM is pulled to GND through a 20kΩ resistor to indicate this fault type. 3. SW-to-PGND short: If a short fault occurs, the part latches off to turn off the HS-FET. The PWM pin is pulled high (1kΩ to VDD) to indicate the fault type. The fault latch is not be reset by entering standby mode. The fault latch can be released by cycling power on VIN or VDD. For multi-phase operation, VTEMP/FLT pins of each together (see Figure 2). connect the Intelli-PhaseTM Intelli-PhaseTM Power Stage VIN Intelli-Phase TM L2 VIN VOUT VTEMP Multi-Phase Controller COUT PWM PWM2 Temperature ADC VIN Intelli-PhaseTM VIN L1 VTEMP PWM PWM1 Figure 2: Multi-Phase Temperature Sense Utilization MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 11 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE APPLICATION INFORMATION 6. Place more PGND vias close to the PGND pin/pad to minimize parasitic resistance, parasitic impedance, and thermal resistance. PCB Layout Guidelines PCB layout is critical for stable operation. For the best results, refer to Figure 3 and follow the guidelines below: 7. Place the BST capacitor and VDRV capacitor as close to the device’s pins as possible, using trace paths at least 20mils wide. 1. Place the input MLCC capacitors as close to the VIN and PGND pins as possible. 8. Avoid using a via for the BST driving path. It is recommended to use a 0.1µF to 1µF bootstrap capacitor. 2. Place the major MLCC capacitors on the same layer as the MP86972. 3. Place as many VIN and PGND vias underneath the package as possible, as well as between the VIN or PGND long pads. 9. Place the VDD decoupling capacitor close to the device. 10. Connect AGND and PGND at the VDD capacitor’s ground connection. 4. Place a VIN copper plane on the second inner layer to form the PCB stack as positive/negative/positive to reduce the parasitic impedance from the input MLCC capacitor. 11. Keep the CS signal trace away from highcurrent paths, such as SW and PWM. 5. Ensure that the inner layer copper planes cover the VIN vias that are beneath the package and input MLCC capacitors. RVD D VDD 29 28 27 26 25 BST 30 31 1 VIN 24 23 2 3 32 35 SW VIN 22 CIN CIN 20 5 19 6 7 33 34 SW PGND 18 8 17 9 16 10 CIN CIN 21 CIN SW OUT 4 11 12 13 14 15 VDR V Figure 3: Recommended PCB Layout (Placement and Top Layer) Input Capacitor: 0603 Package (Top Side and Bottom Side) and 0402 Package (Top Side) Inductor: 6mmx7mm Package VDD/BST/VDRV Capacitor: 0402 Package Via Size: 20/10mils MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 12 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE TYPICAL APPLICATION CIRCUIT VDRV VDD AGND Figure 4: Typical Application Circuit MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 13 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE PACKAGE INFORMATION TLGA-35 (3mmx6mm) PIN 1 ID MARKING PIN 1 ID 0.20X45º TYP PIN 1 ID INDEX AREA TOP VIEW BOTTOM VIEW SIDE VIEW RECOMMENDED LAND PATTERN NOTES: RECOMMENDED STENCIL DESIGN MP86972 Rev. 1.0 6/28/2021 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-303. 4) DRAWING IS NOT TO SCALE. MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 14 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE CARRIER INFORMATION 1 Pin1 1 ABCD 1 1 ABCD ABCD ABCD Feed Direction Part Number Package Description Quantity/ Reel Quantity/ Tube Quantity/ Tray Reel Diameter Carrier Tape Width Carrier Tape Pitch MP86972GLJTH-Z TLGA-35 (3mmx6mm) 5000 N/A N/A 13in 12mm 8mm MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 15 MP86972 – 60A, INTELLI-PHASETM SOLUTION IN TLGA-35 (3MMX6MM) PACKAGE REVISION HISTORY Revision # Revision Date 1.0 06/28/2021 Description Pages Updated Initial Release - Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP86972 Rev. 1.0 6/28/2021 MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 16