MP8720
The Future of Analog IC Technology
26V,10A, High Efficiency, Fast Transient,
Synchronous, Buck Converter
with adjustable CLM
DESCRIPTION
FEATURES
The MP8720 provides a complete power supply
with the highest power density for system
powers, such as DDR memory and USB type-C.
The MP8720 integrates a high-frequency,
synchronous, rectified, step-down, switch-mode
converter (VOUT) with an adjustable current limit
(CLM).
The MP8720 operates at high efficiency over a
wide output current load range based on MPS’s
proprietary switching loss reduction technology
and internal low RDS(ON) power MOSFETs.
Adaptive constant-on-time (COT) control mode
provides fast transient response and eases loop
stabilization. The DC auto-tune loop provides
good load and line regulation.
By setting CLM, the current limit can be
adjusted from 8.5A to 16.5A for different mode
applications.
Full protection features include over-current
limit (OCL), over-voltage protection (OVP),
under-voltage protection (UVP), and thermal
shutdown.
The MP8720 requires a minimal number of
external components and is available in a QFN16 (3mmx3mm) package.
Wide 4.5V to 26V Operating Input Range
Compatible for USB Type-C
10A Continous Output Current
Adjustable Current Limit from 8.5A to 16.5A
Fixed 700KHz Switching Frequency
Adaptive COT for Fast Transient
DC Auto-Tune Loop
Stable with POSCAP and Ceramic Output
Capacitors
Internal Soft Start (SS)
Selectable Pulse Skip or Forced CCM
Output Adjustable from 0.8V to 5.5V
OCL, OVP, UVP, and Thermal Shutdown
Latch-Off Reset via EN or Power Cycle
Available in a QFN-16 (3mmx3mm)
Package
APPLICATIONS
Televisions
Networking Systems
Distributed Power System
Set-Top-Box
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
1
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
ORDERING INFORMATION
Part Number*
MP8720GQ
Package
QFN-16 (3mmx3mm)
Top Marking
See below
* For Tape & Reel, add suffix –Z (e.g. MP8720GQ–Z)
TOP MARKING
BCT: product code of MP8720GQ;
Y: year code;
LLL: lot number;
PACKAGE REFERENCE
TOP VIEW
QFN-16 (3mmx3mm)
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
2
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply voltage (VIN) .................................... 26V
VSW (DC) .................................-1V to VIN + 0.3V
(2)
VSW (25ns).......................... -3.6V to VIN + 4V
VBST ................................................... VSW + 4.5V
All other pins ................................-0.3V to +4.5V
(3)
Continuous power dissipation (TA = +25°C)
QFN-16 (3mmx3mm) ................................. 2.3W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +150°C
QFN-16 (3mmx3mm) ............. 55 ....... 13 ... °C/W
Recommended Operating Conditions
(4)
Supply voltage (VIN) ........................ 4.5V to 24V
Supply voltage (VCC) ..................... 3.15V to 3.5V
Output voltage (VOUT) ...................... 0.8V to 5.5V
Operating junction temp. (TJ). .. -40°C to +125°C
MP8720 Rev. 1.01
8/1/2017
(5)
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) Measured by using differential oscilloscope probe.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
3
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
ELECTRICAL CHARACTERISTICS
VIN = 12V, 3V3 = 3.3V, TJ = 25°C, RMODE = 0Ω, unless otherwise noted.
Parameters
Supply Current
3V3 supply current
3V3 shutdown current
Symbol
I3V3
I3V3
SDN
Condition
Min
VEN = 3V, VFB = 0.65V, no
load
VEN = 0V, no load
Typ
Max
Units
140
230
µA
1
µA
MOSFET
High-side switch on resistance
HSRDS-ON
TJ = 25°C
19
mΩ
Low-side switch on resistance
LSRDS-ON
TJ = 25°C
7
mΩ
VEN = 0V, VSW = 0V
0
Switch leakage
Current Limit
SWLKG
Low-side valley current limit
ILIMIT
CLM = 0Ω
CLM = 90kΩ
CLM = 150kΩ
CLM = float
Switching Frequency and Minimum Off Time
Switching frequency
Fs
Constant on timer
TON
VIN = 5V, VOUT = 1.8V
(6)
Minimum on time
TON MIN
(6)
Minimum off time
TOFF MIN
Protection
OVP threshold
VOVP
UVP-1 threshold
VUVP-1
UVP-1 foldback timer (6)
TUVP-1
UVP-2 threshold
VUVP-2
Reference and Soft Start, Soft Stop
Reference voltage
VREF
Feedback current
IFB
VFB = 0.62V
Soft-start time
TSStart
EN to PG up
MODE
Mode source current
IMODE
Enable and UVLO
En rising threshold
VEN TH
En hysteresis
VEN-HYS
VEN = 2V
Enable input current
IEN
VEN = 0V
VCC under-voltage lockout
VCCVth
threshold rising
VCC under-voltage lockout
VCCHYS
threshold hysteresis
VIN under-voltage lockout
VINVTH
threshold rising
VIN under-voltage lockout
VINHYS
threshold hysteresis
MP8720 Rev. 1.01
8/1/2017
9
430
125
70
8.5
10
13
16.5
700
515
70
240
1
11
600
μA
A
A
A
A
kHz
ns
ns
ns
130
75
30
50
135
80
55
%VREF
%VREF
µs
%VREF
1.8
600
10
2.2
606
50
2.6
mV
nA
ms
9
10
11.4
μA
1.12
1.22
125
1.32
V
mV
45
594
2.9
3.0
5
1
μA
3.1
V
220
4.2
360
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
mV
4.4
V
mV
4
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, 3V3 = 3.3V, TJ = 25°C, RMODE = 0Ω, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Power Good
PG when FB rising (good)
PG_Rising(GOOD)
PG when FB falling (fault)
PG_Falling(Fault)
PG when FB rising (fault)
PG_Rising(Fault)
PG when FB falling (good)
PG_Falling(GOOD)
PG low to high delay
EN low to PG low delay
Power good sink current
capability
Thermal Protection
Thermal shutdown (6)
Thermal shutdown hysteresis
VFB rising, percentage of
VFB
VFB falling, percentage of
VFB
VFB rising, percentage of
VFB
VFB falling, percentage of
VFB
PGTd
PGTd EN low
VPG
TSD
TSD
HYS
95
90
%
115
105
3
Sink 4mA
150
25
1
μs
μs
0.4
V
°C
°C
NOTE:
6) Guaranteed by design.
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
5
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
PIN FUNCTIONS
PIN #
Name
1
VIN
2, 4, 5, 6, 7
PGND
3
3V3
8, 16
NC
9
SW
10
BST
11
CLM
12
PG
13
FB
14
15
MODE
EN
MP8720 Rev. 1.01
8/1/2017
Description
Supply voltage. VIN supplies power for the internal MOSFET and regulator. The
MP8720 operates from a +4.5V to +26V input rail. An input capacitor is needed to
decouple the input rail. Use wide PCB traces and multiple vias to make the connection.
Power ground. Use wide PCB traces and multiple vias to make the connection.
External 3V3 VCC input for control and driver. Place a 1µF decoupling capacitor
close to 3V3 and PGND. It is recommended to form an R-C filter.
No connection. NC can either be connected to VIN, SW, or GND for easy layout.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is connected
to VIN when the HS-FET is on. SW is connected to PGND when the LS-FET is on. Use
wide and short PCB traces to make the connection. SW is noisy, so keep sensitive
traces away from SW.
Bootstrap. A capacitor connected between SW and BST is required to form a floating
supply across the high-side switch driver.
Current limit adjust. There are four settings for the current, which can be set by
connecting CLM to GND with different kinds of resistors.
Power good output. PG is an open-drain signal. PG is high if the output voltage is
within a proper range.
Feedback. An external resistor divider from the output to GND tapped to FB sets the
output voltage. Place the resistor divider as close to FB as possible. Avoid vias on the
FB traces.
Mode. Select MODE for different output ranges and to select DCM or CCM.
Enable. When EN = 1, the regulator turns on; when EN = 0, the regulator turns off.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
6
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 5V, L = 1.5µH, DCR = 10mΩ, FSW = 700kHz, DCM, CLM = 16A, TJ = +25°C, unless
otherwise noted.
Power Loss
Efficiency
100
POWER LOSS(mW)
VOUT=1.2V, FSW=700kHz, L=0.68µH, DCR=3.1mΩ,
RBST=0Ω, COUT=3x22µF, DCM MODE
EFFICIENCY(%)
90
80
VIN=5V
VIN=8.4V
VIN=12V
VIN=19V
70
60
50
1
0.8
0.6
0.4
0.2
0
‐0.2
‐0.4
‐0.6
‐0.8
‐1
0.1
1
LOAD CURRENT(A)
VIN=5V
VIN=8.4V
VIN=12V
VIN=19V
0.01
0.1
1
LOAD CURRENT(A)
10
Load Regulation vs. Load Current
Efficiency
VOUT=1.2V, FSW=700kHz, L=0.68µH, DCR=3.1mΩ,
RBST=0Ω, COUT=3x22µF, DCM MODE
VOUT=5V, FSW=700kHz, L=1.5µH, DCR=10mΩ,
RBST=0Ω, COUT=5x22µF, DCM MODE
100
EFFICIENCY(%)
90
VIN=5V
VIN=8.4V
VIN=12V
VIN=19V
80
VIN=5.5V
70
VIN=8.4V
VIN=12V
60
VIN=19V
50
0.01
POWER LOSS(mW)
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
10
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0.1
1
LOAD CURRENT(A)
10
0.01
0.1
1
LOAD CURRENT(A)
10
Power Loss
Load Regulation
VOUT=5V, FSW=700kHz, L=1.5µH, DCR=10mΩ,
RBST=0Ω, COUT=5x22µF, DCM MODE
VOUT=5V, FSW=700kHz, L=1.5µH, 744323150, COUT=3x47µF,
R9=100kΩ, R10=11.3kΩ, RBST=0Ω, C4=220pF, R4=360kΩ
2
VIN=5.5V
VIN=8.4V
VIN=12V
VIN=19V
1.5
LOAD REGULATION (%)
LOAD REGULATION (%)
0.01
VOUT=1.2V, FSW=700kHz, L=0.68µH, DCR=3.1mΩ,
RBST=0Ω, COUT=3x22µF, DCM MODE
1
0.5
0
Vin=6V
Vin=8.4V
Vin=12V
Vin=19V
‐0.5
‐1
‐1.5
‐2
0.01
MP8720 Rev. 1.01
8/1/2017
0.1
1
LOAD CURRENT(A)
10
0.01
0.1
1
LOAD CURRENT(A)
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
10
7
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 1.5µH, DCR = 10mΩ, FSW = 700kHz, DCM, CLM = 16A, TJ = +25°C, unless
otherwise noted.
2
Line Regulation
Temperature Rise with Load Current
VOUT=5V, FSW=700kHz, L=1.5µH, 744323150, COUT=3x47µF,
R9=100kΩ, R10=11.3kΩ, RBST=0Ω, C4=220pF, R4=360kΩ
VOUT=5V, FSW=700kHz, L=1.5µH, DCR=4.3mΩ,
RBST=0Ω, COUT=4x22µF, DCM MODE
TEMPRATURE RISE (OC)
LINE REGULATION (%)
1.5
1
0.5
0
‐0.5
‐1
Iout=0A
Iout=1A
‐1.5
70
Iout=0.1A
Iout=10A
50
40
30
20
10
VIN=19V
0
‐2
6
8
10
12 14 16 18 20
LOAD CURRENT(A)
22
0
24
1
2
3
4
5
6
7
OUTPUT CURRENT(A)
8
Frequency vs. Load Current
Frequency vs. Input Voltage
VOUT=5V, FSW=700kHz, L=1.5µH, DCM MODE
VOUT=5V, FSW=700kHz, L=1.5µH, DCM MODE
900
800
700
600
500
400
300
200
100
0
VIN=6V
VIN=12V
0
2
FREQUENCY (kHz)
FREQUENCY (kHz)
60
VIN=8.4V
VIN=19V
4
6
LOAD CURRENT(A)
8
10
900
800
700
600
500
400
300
200
100
0
9
10
Iout=2A
Iout=10A
6
8
10
12 14 16 18 20
INPUT VOLTAGE (V)
22
24
Current Limit vs. Temperature
CURRENT LIMIT (A)
18
16
14
12
10
8
CLM=8.5A
CLM=13A
6
‐40
‐20
MP8720 Rev. 1.01
8/1/2017
0
20
40
CLM=10A
CLM=16.5A
60
80
TEMPERATURE (oC)
100 120
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
8
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 1.5µH, DCR = 10mΩ, FSW = 700kHz, DCM, CLM = 16A, TJ = +25°C, unless
otherwise noted.
Input/Output Voltage Ripple
Input/Output Voltage Ripple
IOUT = 0A, DCM
IOUT = 0A, CCM
CH1:
VOUT/AC
50mV/div.
CH1:
VOUT/AC
50mV/div.
CH2:
VIN/AC
200mV/div.
CH2: VIN/AC
100mV/div.
CH3: VSW
20V/div.
CH3: VSW
10V/div.
CH4: IL
2A/div.
CH4: IL
10A/div.
4ms/div.
2µs/div.
Input/Output Voltage Ripple
Input/Output Voltage Ripple
IOUT = 10A, DCM
IOUT = 10A, CCM
CH1:
CH1:
VOUT/AC
50mV/div.
VOUT/AC
50mV/div.
CH2: VIN/AC
1V/div.
CH2:
VIN/AC
500mV/div.
CH3: VSW
20V/div.
CH3: VSW
20V/div.
CH4: IL
10A/div.
CH4: IL
10A/div.
2µs/div.
2µs/div.
Power Good through EN Start-Up
Power Good through EN Start-Up
IOUT = 0A, DCM
IOUT = 10A, DCM
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VEN
5V/div.
CH2: VEN
5V/div.
CH3: VSW
20V/div.
CH4: VPG
5V/div.
CH3: VSW
20V/div.
CH4: VPG
5V/div.
400µs/div.
MP8720 Rev. 1.01
8/1/2017
400µs/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
9
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 1.5µH, DCR = 10mΩ, FSW = 700kHz, DCM, CLM = 16A, TJ = +25°C, unless
otherwise noted.
Power Good through EN Shutdown
Power Good through EN Shutdown
IOUT = 0A, DCM
IOUT = 10A, DCM
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VEN
5V/div.
CH2: VEN
5V/div.
CH3: VSW
10V/div.
CH4: VPG
5V/div.
CH3: VSW
10V/div.
CH4: VPG
5V/div.
2ms/div.
100µs/div.
Transient
Transient
VIN = 19V, L = 1.5µH, COUT = 6 x 22µF, DCM,
IOUT = 1A - 9A @ 2.5A/µs
VIN = 19V, L = 1.5µH, COUT = 6 x 22µF , CCM,
IOUT = 1A - 9A @ 2.5A/µs
CH1:
CH1:
VOUT/AC
200mV/div.
VOUT/AC
200mV/div.
CH4: IL
5A/div.
CH4: IL
5A/div.
400µs/div.
400µs/div.
Short-Circuit Protection through EN Up
Short-Circuit Protection through EN Up
Set CLM = 8.5A, VIN = 19V
Set CLM = 10A, VIN = 19V
CH1: VOUT
500mV/div.
CH1: VOUT
500mV/div.
CH2: VEN
5V/div.
CH2: VEN
5V/div.
CH3: VSW
20V/div.
CH4: IL
10A/div.
CH3: VSW
20V/div.
CH4: IL
10A/div.
1ms/div.
MP8720 Rev. 1.01
8/1/2017
1ms/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
10
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 1.5µH, DCR = 10mΩ, FSW = 700kHz, DCM, CLM = 16A, TJ = +25°C, unless
otherwise noted.
Short-Circuit Protection through EN Up
Short-Circuit Protection through EN Up
Set CLM = 13A, VIN = 19V
Set CLM = 16.5A, VIN = 19V
CH1: VOUT
500mV/div.
CH1: VOUT
500mV/div.
CH2: VEN
5V/div.
CH2: VEN
5V/div.
CH3: VSW
20V/div.
CH4: IL
10A/div.
CH3: VSW
20V/div.
CH4: IL
10A/div.
1ms/div.
1ms/div.
Thermal Shutdown
Thermal Recovery
VIN = 19V, IOUT = 10A
VIN = 19V, IOUT = 10A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VPG
5V/div.
CH2: VPG
5V/div.
CH3: VSW
20V/div.
CH3: VSW
20V/div.
CH4: IL
10A/div.
CH4: IL
10A/div.
20µs/div.
1ms/div.
EN Pre-Bias Start-Up
OVP Circuit Protection
VIN = 19V, IOUT = 10A
VIN = 19V, IOUT = 10A, Force VOUT = 6.8V
CH1: VOUT
2V/div.
CH1: VOUT
5V/div.
CH2: VEN
2V/div.
CH2: VIN
20V/div.
CH3: VSW
10V/div.
CH4: IL
5A/div.
CH3: VSW
5V/div.
CH4: IL
5A/div.
400µs/div.
MP8720 Rev. 1.01
8/1/2017
10ms/div.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
11
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
BLOCK DIAGRAM
AGND
MODE
3V3
CLM
EN
VIN
BST
BSTREG
3V3
VIN
POR &
Reference
Soft Start
FB
FB
On Time
One Shot
REF
Min off time
Control
Logic
SW
VDDQ
DC Error
Correction
+
+
Output
Discharge
PGND
Vref
SW
130% Vref
OC Limit
OVP
PG
FB
95% Vref
POK
50% Vref
UVP-2
75% Vref
UVP-1
Fault
Logic
Figure 1: Functional Block Diagram
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
12
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
OPERATION
Pulse-Width Modulation (PWM) Operation
The MP8720 is a fully integrated, synchronous,
rectified, step-down, switch-mode converter
with an adjustable current limit (CLM).
Constant-on-time (COT) control provides fast
transient response and eases loop stabilization.
At the beginning of each cycle, the high-side
MOSFET (HS-FET) is turned on when the
feedback voltage (VFB) is below the reference
voltage (VREF), which indicates an insufficient
output voltage. The on period is determined by
both the output voltage and the input voltage to
make the switching frequency fairly constant
over the input voltage range.
After the on period elapses, the HS-FET is
turned off or enters an off state. The HS-FET is
turned on again when VFB drops below VREF. By
repeating operation this way, the converter
regulates the output voltage. The integrated
low-side MOSFET (LS-FET) is turned on when
the HS-FET is in its off state to minimize
conduction loss. A dead short occurs between
the input and GND if both the HS-FET and the
LS-FET are turned on at the same time. This is
called shoot-through. To prevent shoot-through,
a dead time (DT) is generated internally
between the HS-FET off and the LS-FET on
period or the LS-FET off and the HS-FET on
period.
Internal compensation is applied for COT
control for stable operation, even when ceramic
capacitors are used as output capacitors. This
internal compensation improves the jitter
performance without affecting the line or load
regulation.
Heavy-Load Operation
Continuous conduction mode (CCM) occurs
when the output current is high and the inductor
current is always above zero amps (see Figure
2). When VFB is below VREF, the HS-FET is
turned on for a fixed interval determined by the
one-shot on timer. When the HS-FET is turned
off, the LS-FET is turned on until the next
period.
Figure 2: CCM Operation
Light-Load Operation
When the load decreases, the inductor current
decreases as well. Once the inductor current
reaches zero, the MP8720 transitions from
CCM to discontinuous conduction mode (DCM).
DCM operation is shown in Figure 3.
When VFB is below VREF, the HS-FET is turned
on for a fixed interval determined by the oneshot on timer. When the HS-FET is turned off,
the LS-FET is turned on until the inductor
current reaches zero. In DCM operation, the VFB
does not reach VREF when the inductor current
is approaching zero. The LS-FET driver turns
into tri-state (Hi-Z) when the inductor current
reaches zero. A current modulator takes over
the control of the LS-FET and limits the inductor
current to less than
-1mA. Therefore, the
output capacitors discharge slowly to GND
through the LS-FET. As a result, the efficiency
during light-load condition improves greatly.
The HS-FET does not turn on as frequently
during a light-load condition as it does during a
heavy-load condition (skip mode).
At a light-load or no-load condition, the output
drops very slowly, and the MP8720 reduces the
switching frequency naturally, achieving high
efficiency at light load.
Figure 3: DCM Operation
In CCM operation, the switching frequency is
fairly constant (pulse-width modulation (PWM)
mode).
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.r
13
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
As the output current increases from light-load
condition, the current modulator regulation time
period becomes shorter. The HS-FET is turned
on more frequently, making the switching
frequency increases. The output current
reaches the critical level when the current
modulator time is zero. The critical level of the
output current is determined with Equation (1):
IOUT _ Critical
( VIN VOUT ) VOUT
2 L FS VIN
(1)
The MP8720 enters PWM mode once the
output current exceeds the critical level.
Afterward, the switching frequency remains
fairly constant over the output current range.
Jitter and FB Ramp
Jitter occurs in both PWM and skip mode when
noise in the VFB ripple propagates a delay to the
HS-FET driver (see Figure 4 and Figure 5).
Jitter affects system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope, so the jitter in DCM is usually
larger than it is in CCM. However, the VFB ripple
does not affect noise immunity directly.
VNOISE
V S L O PE1
VFB
VREF
HS D river
J itter
Figure 4: Jitter in PWM Mode
VS LOPE 2
VNOISE
V FB
V REF
HS D river
Jitter
Figure 5: Jitter in Skip Mode
Operating
without
External
Ramp
Compensation
The traditional COT control scheme is
intrinsically unstable if the output capacitor’s
ESR is not large enough to act as an effective
current-sense resistor.
MP8720 Rev. 1.01
8/1/2017
Usually, ceramic capacitors cannot be used
directly as output capacitors.
The MP8720 has built-in internal ramp
compensation to ensure that the system is
stable, even without the help of the output
capacitor’s ESR. Use the pure ceramic
capacitor solution, which reduces the output
ripple, total BOM cost, and board area
significantly.
Figure 6 shows a typical output circuit in PWM
mode without an external ramp circuit. Refer to
the Application Information section on page 17
for design steps without external compensation.
Figure 6: Simplified Output Circuit
When using a large capacitor (e.g.: OSCON) on
the output, add a >10µF ceramic capacitor in
parallel to minimize the effect of ESL.
Operating
with
External
Ramp
Compensation
Usually, the MP8720 is able to support ceramic
output capacitors without an external ramp.
However in some cases, the internal ramp may
not be enough to stabilize the system, or there
is too much jitter, which requires external ramp
compensation. Refer to the Application
Information section on page 17 for design steps
with external ramp compensation.
MODE Selection
The MP8720 implements MODE for multiple
applications for output and switching mode
selection. The output and switch mode can be
selected by a different resistor on MODE. There
are four modes that can be selected for normal
application with external resistors (see Table 2).
It is recommended to use a 1% accuracy
resistor.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
14
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
Table 2: MODE Selection
State
M1
M2
M3
M4
VOUT
DCM/CCM Resistor to GND
Vo < 3V
DCM
0Ω
Vo < 3V
CCM
90kΩ
Vo ≥ 3V
CCM
150kΩ
Vo ≥ 3V
DCM
>230kΩ or float
Power Good (PG)
The MP8720 uses a power good (PG) output to
indicate whether the output voltage of the VOUT
regulator is ready. PG is the open drain of a
MOSFET. It should be connected to VCC or
another voltage source through a resistor (e.g.:
100kΩ). After the input voltage is applied, the
MOSFET is turned on, so PG is pulled to GND
before SS is ready. After VFB reaches 95% of
VREF, PG is pulled high (after a delay time within
10µs). When VFB drops to 90% of VREF, PG is
pulled low.
Soft Start (SS)
The MP8720 employs a soft-start (SS)
mechanism to ensure a smooth output during
power-up. When EN becomes high, the internal
reference voltage ramps up gradually, and the
output voltage ramps up smoothly as well.
Once the reference voltage reaches the target
value, the soft start finishes, and the MP8720
enters steady-state operation (see Figure 7).
Output Discharge
The MP8720 discharges the output through an
internal 100Ω resistor when the controller is
turned off by a protection function (UVP, OCP,
OVP, UVLO, or thermal shutdown).
Over-Current Limit (OCL)
The MP8720 has cycle-by-cycle over-current
limiting control. The current-limit circuit employs
a valley current-sensing algorithm. The MP8720
uses the RDS(ON) of the LS-FET as a currentsensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle, even if FB is lower than REF (see
Figure 8).
Figure 8: Valley Current-Limit Control
Since the comparison is done during the LSFET on state, the over-current trip level sets the
valley level of the inductor current. The
maximum load current at the over-current
threshold (IOC) can be calculated using Equation
(2):
IOC I _ limit
Figure 7: Start-Up Power Sequence
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high-side and the low-side switches
until the voltage on the internal reference
exceeds the sensed output voltage at the FB
node.
MP8720 Rev. 1.01
8/1/2017
Iinductor
2
(2)
The over-current limit (OCL) limits the inductor
current and does not latch off. In an overcurrent condition, the current to the load
exceeds the current to the output capacitor, so
the output voltage tends to fall off. Eventually,
the current ends up crossing the under-voltage
protection (UVP) threshold and latches off.
Fault latching can be reset by EN going low or
cycling the power of VIN.
Current Limit (CLM) Selection
The MP8720 implements an adjustable valley
CLM by connecting CLM to GND with different
resistor values (see Table 3).
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
15
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
Table 3: CLM Selection
State
M1
M2
M3
M4
CLM
8.5A
10A
13A
16.5A
Resistor to GND
0Ω
90kΩ
150kΩ
>230kΩ or float
Over/Under-Voltage Protection (OVP, UVP)
The MP8720 monitors a resistor divided
feedback voltage to detect over- and undervoltage. When the feedback voltage rises
higher than 130% of the target voltage, the
OVP comparator output goes high, the circuit
latches as the HS-FET turns off, and the LSFET turns on, acting as a -2A current source.
Under-Voltage Lockout (UVLO) Protection
The MP8720 has two under-voltage lockout
(UVLO) protections: a 3V VCC UVLO and a 4.2V
VIN UVLO. The MP8720 starts up only when
both VCC and VIN exceed their respective UVLO
thresholds. The MP8720 shuts down when
either VCC is lower than the UVLO falling
threshold voltage (typically 2.8V) or VIN is lower
than the 3.8V VIN falling threshold. Both UVLO
protections are non-latch off.
If an application requires a higher UVLO, use
EN to adjust the input voltage UVLO by using
two external resistors (see Figure 9).
To protect the MP8720 from damage, there is
an absolute 3.6V OVP on VOUT when the
system is in VOUT < 3V mode. Once VOUT
reaches this value, it latches off. The LS-FET
behaves the same as it does at 130% OVP.
When the feedback voltage drops below 75% of
VREF, but remains higher than 50% of VREF, the
UVP-1 comparator output goes high, and the
MP8720 latches if VFB remains in this range for
about 30µs (latching the HS-FET off and the
LS-FET on). The LS-FET remains on until the
inductor current reaches zero. During this
period, the valley current limit helps control the
inductor current.
When the feedback voltage drops below 50% of
VREF, the UVP-2 comparator output goes high,
and the MP8720 latches off directly after the
comparator and logic delay (latching the HSFET off and the LS-FET on). The LS-FET
remains on until the inductor current reaches
zero. Fault latching can be reset by driving EN
low or cycling the power of VIN.
MP8720 Rev. 1.01
8/1/2017
Figure 9: Adjustable UVLO
Thermal Shutdown
Thermal shutdown is employed in the MP8720.
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds
the threshold value (typically 150°C), the
converter shuts off. This is a non-latch
protection. There is a hysteresis of about 25°C.
Once the junction temperature drops to about
125°C, a new soft start is initiated.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
16
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
APPLICATION INFORMATION
Setting the Output Voltage with No External
Ramp
The
MP8720
does
not
need
ramp
compensation for applications where POSCAP
or ceramic capacitors are set as output
capacitors (when VIN is over 6V), so the
external compensation is not needed. The
output voltage is then set by feedback resistors
R1 and R2 (see Figure 10).
Figure 10: Simplified Circuit without External
Ramp
First, choose a value for R2. R2 should be
chosen reasonably. A small value for R2 leads
to considerable quiescent current loss, but an
R2 value that is too large makes FB noisesensitive. It is recommended to choose a value
within 5 - 50kΩ for R2. Use a comparatively
larger value for R2 when VOUT is low; use a
smaller value for R2 when VOUT is high.
Considering the output ripple, R1 is determined
with Equation (3):
R1
VOUT VREF
R2
VREF
(3)
C4 acts as a feed-forward capacitor to improve
the transient and can be set in the range of
0 - 1000pF. A larger value for C4 leads to better
transient, but it is more noise sensitive.
Reserve room for a noise filter resistor (R9)
(see Figure 11).
Setting the Output Voltage with External
Compensation
If the system is not stable enough or there is
too much jitter when a ceramic capacitor is
used on the output (i.e.: with a ceramic COUT
and VIN is 5V or lower), an external voltage
ramp should be added to FB through resistor
R4 and capacitor C4. Since there is already an
internal ramp added in the system, a 1MΩ (R4),
220pF (C4) ramp should suffice.
MP8720 Rev. 1.01
8/1/2017
Figure 11: Simplified Circuit with External Ramp
Besides the R1 and R2 divider, the output
voltage is influenced by R4 (see Figure 12). R2
should be chosen reasonably. A small value for
R2 leads to considerable quiescent current loss,
but a value for R2 that is too large makes FB
noise sensitive. It is recommended to choose a
value within 5 - 50kΩ for R2. Use a
comparatively larger value for R2 when VOUT is
low; use a smaller value for R2 when VOUT is
high. The value of R1 then is determined with
Equation (4):
R1
1
R
VREF
R2 2
VOUT VREF R4
(4)
To get a pole for better noise immunity, set R9
with Equation (5):
R9
1
2 C4 2FSW
(5)
Set R9 in the range of 100Ω to 1kΩ to reduce
its influence on the ramp.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the step-down
converter while maintaining the DC input
voltage. For the best performance, use ceramic
capacitors placed as close to VIN as possible.
Capacitors with X5R and X7R ceramic
dielectrics are recommended because they are
fairly stable with temperature fluctuations.
The capacitors must have a ripple current rating
greater than the maximum input ripple current
of the converter. The input ripple current can be
estimated with Equation (6):
ICIN IOUT
VOUT
V
(1 OUT )
VIN
VIN
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.r
(6)
17
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (7):
ICIN
IOUT
2
(7)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitance value determines the
input voltage ripple of the converter. If there is
an input voltage ripple requirement in the
system, choose an input capacitor that meets
the specification.
The input voltage ripple can be estimated with
Equation (8):
VIN
IOUT
V
V
OUT (1 OUT )
FSW CIN VIN
VIN
(8)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (9):
VIN
IOUT
1
4 FSW CIN
(9)
Selecting the Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output
voltage ripple can be estimated using Equation
(10):
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (10)
FSW L
VIN
8 FSW COUT
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance, which mainly causes the output
voltage ripple. For simplification, the output
voltage ripple can be estimated with Equation
(11):
VOUT
VOUT
V
(1 OUT )
2
8 FSW L COUT
VIN
(11)
The output voltage ripple caused by the ESR is
very small. Therefore, an external ramp is
needed to stabilize the system. The external
ramp can be generated through resistor R4 and
capacitor C4.
MP8720 Rev. 1.01
8/1/2017
When using POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from
the ESR dominates the output ripple. The
output ripple can be approximated with
Equation (12):
VOUT
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(12)
The maximum output capacitor limitation should
be considered in the design application. The
MP8720 has a soft-start time period around
1.6ms. If the output capacitor value is too high,
the output voltage cannot reach the design
value during the soft-start time, causing it to fail
to regulate. The maximum output capacitor
value (Co_max) can be limited approximately with
Equation (13):
CO _ MAX (ILIM _ AVG IOUT ) Tss / VOUT (13)
Where ILIM_AVG is the average start-up current
during the soft-start period (which can be
equivalent to the current limit), and Tss is the
soft-start time.
Selecting the Inductor
An inductor is necessary for supplying constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor results in less ripple current, resulting
in a lower output ripple voltage, but also has a
larger physical footprint, a higher series
resistance, and a lower saturation current. A
good rule for determining the inductance value
is to design the peak-to-peak ripple current in
the inductor to be in the range of 30% to 50% of
the maximum output current, and the peak
inductor current below the maximum switch
current limit. The inductance value can be
calculated with Equation (14):
L
VOUT
V
(1 OUT )
FSW IL
VIN
(14)
Where ∆IL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current (including a
short-current), so ISAT is recommended to
be >13A.
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
18
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation of the IC. A 4-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure
12 and follow the guidelines below.
4. Keep the switching node (SW) short and
away from the feedback network.
1. Place the high-current paths (GND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
A thick PGND trace under the IC should be
top priority.
7. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
2. Place the input capacitors as close to VIN
and GND as possible on the same layer as
the IC.
9. Add several vias with 10mil drill/18mil
copper width close to the VIN and GND
pads to help thermal dissipation.
5. Place the external feedback resistors next
to FB.
6. Ensure that there is no via on the FB trace.
8. Keep the VIN and GND pads connected
with a large copper plane to achieve better
thermal performance.
3. Place the decoupling capacitor as close to
VCC and GND as possible.
Figure 12: Recommended PCB Layout
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
19
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
Design Example
Table 4 shows the application for different
output parameter settings when ceramic
capacitors are applied.
There is a resistor from an external 3.3V supply
to 3V3 acting as a ripple noise filter of the 3.3V
power supply. It is recommended to have a
resistor value from 0 - 5.1Ω depending on the
noise level. A size 0402 resistor is sufficient if
the 3.3V voltage rises up with SS > 100µs.
Otherwise, a larger resistor (e.g.: 0603/0805) is
needed.
Table 4: Design Example for 700kHz fSW
VOUT
(V)
Cout
(F)
L
RMode C4
(μH) (Ω) (pF)
R1
R2
(kΩ) (kΩ)
R4
(kΩ)
1.0V
1.2
22μx3
0.68
0
220
13.3
20
NS
22μx3
0.68
0
220
20
20
NS
5
220μF
poscap
1.5
Float
220
100
13.7
NS
5
22 μx6
1.5
Float
220
100
10
274
For applications where VIN is 5V or lower, it is
recommended to apply the SCH shown in
Figure 14 with a proper external ramp.
The MP8720 also supports non-DDR
applications with very compact external
components (see Figure 15).
Some design examples are provided below
when ceramic capacitors are applied:
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
20
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL APPLICATION CIRCUITS
Application for 5V Output
Figure 13: 5V Output Application
1.0V Output Application
Figure 14: 1.0V Output Application
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
21
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
TYPICAL APPLICATION CIRCUITS (continued)
5.0V Output Application with Forced CCM
Figure 15: 5V Output Application with Forced CCM
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
22
MP8720 – 26V, 10A, SYNCHRONOUS BUCK CONVERTER WITH ADJUSTABLE CLM
PACKAGE INFORMATION
QFN-16 (3mmx3mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8720 Rev. 1.01
8/1/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
23
工商网监
湘ICP备2023018690号
