MP8756
26V, 6A, Low IQ, High-Current,
Synchronous, Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP8756 is a fully integrated, highfrequency, synchronous, rectified, step-down,
switch-mode converter. It offers a very compact
solution that achieves 6A of continuous output
current with excellent load and line regulation
over a wide input supply range.
The MP8756 operates with high efficiency over
a wide output-current load range based on
MPS’ proprietary switching loss reduction
technique and internal low RDS(ON) power
MOSFETs.
Adaptive constant-on-time (COT) control mode
provides fast transient response and eases loop
stabilization. The DC auto-tune loop provides
good load and line regulation.
Full protection features include over-current limit,
over-voltage protection (OVP), under-voltage
protection (UVP), and thermal shutdown.
Wide 4.5V to 26V Operating Input Range
Output Adjustable from 0.6V
Ultrasonic Mode (USM)
117μA Low Quiescent Current
6A Continous Output Current
Adaptive COT for Fast Transient
DC Auto-Tune Loop
Stable with POSCAP and Ceramic Output
1% Reference Voltage
Internal Soft Start
Output Discharge
700kHz Switching Frequency
OCP, OVP, UVP (Hiccup), and Thermal
Shutdown
Available in a QFN-12 (2mmx3mm)
Package
APPLICATIONS
The converter requires a minimum number of
external components and is available in a QFN12 (2mmx3mm) package.
Laptop Computer
Tablet PC
Networking Systems
Personal Video Recorders
Flat-Panel Television and Monitors
Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
3.3
VIN
12V
220nF
BST
VIN
SW
22µF
VOUT
0.68µH
R4
499k
C5
220pF
MODE
48.7K
MP8756
GND
FB
EN
EN
PG
VOUT
AGND
PGND
GND
MP8756 Rev. 1.11
12/14/2018
R9
499
88uF
100.00
95.00
90.00
85.00
80.00
66.5K
VCC
1µF
1V/6A
75.00
70.00
65.00
60.00
55.00
50.00
0.01
0.1
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1
10
1
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8756GD
QFN-12 (2mmx3mm)
See Below
* FOR TAPE & REEL, ADD SUFFIX –Z (E.G. MP8756GD–Z)
TOP MARKING
ATQ: Product code of MP8756GD
Y: Year code
WW: Week code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
EN
FB
12
11
AGND VCC
10
9
1
VIN
8
SW
7
PGND
BST
2
3
4
5
PG
NC
VOUT
6
MODE
QFN-12 (2mmX3mm)
MP8756 Rev. 1.11
12/14/2018
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2
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Supply voltage (VIN)...................................... 26V
VSW…………………………… -0.6V to VIN + 0.3V
VSW (25ns)……………………... -3V to VIN + 4.5V
VBST……………………………………. VSW + 4.5V
VOUT…………………………………. -0.3V to 6.5V
All other pins…………………….. . -0.3V to +4.5V
Continuous power dissipation (TA=+25°C) (2)
QFN-12 (2mmx3mm)…………………….. .. 1.8W
Junction temperature…………………….. . 150°C
Lead temperature………………………… . 260°C
Storage temperature.................-65C to +150°C
QFN-12 (2mmx3mm)...............70....... 15 ... °C/W
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Supply voltage (VIN)……………….. 4.5V to 24V
Output voltage (VOUT)………………. 0.6V to 5.5V
Operating junction temp. (TJ)… -40°C to +125°C
MP8756 Rev. 1.11
12/14/2018
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3
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
1
117
2
135
μA
μA
Supply Current
Supply current (shutdown)
Supply current (quiescent)
IIN
IIN
VEN = 0V
VEN = 3.3V, VOUT = 5.5V
MOSFET
High-side switch on resistance
HSRDS(ON)
30
mΩ
Low-side switch on resistance
LSRDS(ON)
15
mΩ
Switch leakage
SWLKG
VEN = 0V, VSW = 0V
0
1
μA
10.5
12
A
Current Limit
Low-side valley current limit
ILIMIT
9
Switching Frequency and Timer
Switching frequency
FS
Constant on timer
TON
Minimum on time(5)
Minimum off time(5)
TON_Min
TOFF_Min
VIN = 10V, VOUT = 5V,
forced PWM mode
700
kHz
710
ns
50
250
ns
ns
Ultrasonic Mode (USM)
Ultrasonic mode operation period
TUSM
20
30
40
μs
117%
112%
70%
122%
117%
75%
50
50%
127%
122%
80%
VREF
VREF
VREF
μs
VREF
600
1.2
606
Over-Voltage (OVP) and Under-Voltage Protection (UVP)
OVP threshold
OVP falling threshold
UVP-1 threshold
UVP-1 deglitch timer(5)
UVP-2 threshold
VOVP_RISING
VOVP_FALLING
VUVP-1
TUVP-1
VUVP-2
45%
55%
Reference and Soft Start (SS)
Feedback voltage
Soft-start time
MODE
PWM mode input logic low
threshold
PFM with USM threshold
PFM without USM threshold
MP8756 Rev. 1.11
12/14/2018
VREF
TSS
594
VOUT 10% to 90%
VMODE_H
2.6
VMODE_MID
VMODE_L
1.2
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mV
ms
V
1.9
0.4
V
V
4
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameters
Symbol
Enable and UVLO
Enable rising threshold
Enable hysteresis
VEN_H
VEN-HYS
Enable input current
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
IEN
Condition
Min
Typ
Max
Units
1.15
1.25
100
5
0
1.35
V
mV
4.25
4.5
VEN = 2V
VEN = 0V
4
VINVTH
VINHYS
μA
250
V
mV
VCC Regulator
VCC regulator
VCC
VCC load regulation
3.5
ICC = 5mA
3.6
3.7
5
V
%
Power Good (PG)
PG when FB rising (good)
PG when FB falling (fault)
PG when FB rising (fault)
PG when FB falling (good)
Power good low-to-high delay
EN low to power good low delay
Power good sink-current
capability
Power good leakage current
Thermal Protection
Thermal shutdown(5)
Thermal shutdown hysteresis(5)
PGRising(Good)
PGFalling(Fault)
PGRising(Fault)
PGFalling(Good)
PGTd
PGTd_EN low
VFB rising, percentage of VFB
VFB falling, percentage of VFB
VFB rising, percentage of VFB
VFB falling, percentage of VFB
95
85
115
105
500
%
1
μs
μs
VPG
Sink 4mA
0.4
V
IPG_LEAK
VPG = 3.3V
5
μA
TSD
TSD-HYS
150
25
°C
°C
NOTE:
5) Guaranteed by engineering sample characterization.
MP8756 Rev. 1.11
12/14/2018
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5
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1V, L = 0.68µH/3.1mΩ, fS = 700kHz, TA = +25°C, PFM mode, unless otherwise
noted.
100.00
100.00
100.00
95.00
95.00
95.00
90.00
90.00
90.00
85.00
85.00
85.00
80.00
80.00
80.00
75.00
75.00
75.00
70.00
0.01
0.1
1
10
70.00
0.01
0.1
1
10
70.00
0.01
95.00
100.00
95.00
95.00
90.00
85.00
90.00
85.00
90.00
85.00
80.00
80.00
80.00
75.00
70.00
75.00
70.00
75.00
70.00
65.00
65.00
65.00
60.00
55.00
50.00
0.01
60.00
55.00
50.00
0.01
60.00
55.00
50.00
0.01
100.00
0.1
1
10
0.40
0.50
0.30
0.40
1
10
0.30
0.20
0.20
0.10
0.10
0.00
0.00
-0.10
-0.10
-0.20
-0.20
-0.30
-0.30
-0.40
0.1
-0.40
0
1
MP8756 Rev. 1.11
12/14/2018
2
3
4
5
6
-0.50
0
1
2
3
4
5
6
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
0
1
0.1
1
10
0.1
1
10
2
3
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4
5
6
6
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.68µH/3.1mΩ, fS = 700kHz, TA = +25°C, PFM mode, unless otherwise
noted.
MP8756 Rev. 1.11
12/14/2018
www.MonolithicPower.com
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7
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.68µH/3.1mΩ, fS = 700kHz, TA = +25°C, PFM mode, unless otherwise
noted.
MP8756 Rev. 1.11
12/14/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
8
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.68µH/3.1mΩ, fS = 700kHz, TA = +25°C, PFM mode, unless otherwise
noted.
MP8756 Rev. 1.11
12/14/2018
www.MonolithicPower.com
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9
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
PIN FUNCTIONS
PIN #
Name
1
VIN
2
PGND
3
PG
4
NC
5
VOUT
6
MODE
7
SW
8
BST
9
VCC
10
AGND
11
FB
12
EN
MP8756 Rev. 1.11
12/14/2018
Description
Supply voltage. VIN supplies power for the internal MOSFET and regulator. The MP8756
operates from a 4.5V to 26V input rail. Decouple the input rail with an input capacitor. Use
wide PCB traces and multiple vias to make the connection. Apply at least two layers for
this input trace.
Power ground. Connect using wide PCB traces and multiple vias large enough to handle
the load current.
Power good output. The output of PG is an open-drain signal. PG is high if the output
voltage is higher than 95% or lower than 105% of the nominal voltage.
Do not connect. NC must be left floating.
VOUT is used to sense the output voltage of the buck regulator. Connect VOUT to
the output capacitor of the regulator directly. Keep the VOUT sensing trace far away from
the SW node. Vias should also be avoided on the VOUT sensing trace. A trace larger
than 25mil is required.
USM, PFM, PWM selection. Pull MODE higher than 2.6V to operate the MP8756 in
forced PWM mode. Float MODE to operate the MP8756 in PFM mode with ultrasonic
mode (USM) at light load. Connect MODE to ground to operate the MP8756 in PFM mode
without USM.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to
VIN by the high-side switch during the PWM duty cycle on-time. The inductor current
drives SW negative during the off time. The on resistance of the low-side switch and the
internal diode fixes the negative voltage. Use wide and short PCB traces to make the
connection. Keep the SW pattern area minimized.
Bootstrap. A capacitor connected between SW and BST is required to form a floating
supply across the high-side switch driver.
Internal VCC LDO output. The driver and control circuits are powered by VCC. Decouple
with a minimum 1µF ceramic capacitor placed as close to VCC as possible. X7R or X5R
grade dielectric ceramic capacitors are recommended for their stable temperature
characteristics.
Signal logic ground. AGND is the Kelvin connection to PGND.
Feedback. FB sets the output voltage when connected to the tap of an external resistor
divider connected between output and GND.
Enable. EN is a digital input that turns the regulator on or off. When the power supply of
the control circuit is ready, drive EN high to turn on the regulator. Drive EN low to turn off
the regulator.
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10
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
BLOCK DIAGRAM
AGND
VCC
MODE
EN
VIN
VIN
Soft Start
BST
BSTREG
POR &
Reference
VIN
VOUT
BUF
FB
+
+
On-Time One
Shot
REF
Min Off Time
DC Error
Correction
Control
Logic
SW
VOUT
+
+
Output
Discharge
PGND
Vref
SW
VOUT
Slope
Generator
122% Vref
OC Limit
OVP
PG
FB
90% Vref
POK
50% Vref
UVP-2
75% Vref
UVP-1
Fault
Logic
Figure 1: Functional Block Diagram
MP8756 Rev. 1.11
12/14/2018
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11
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
OPERATION
PWM Operation
The MP8756 is a fully integrated, synchronous,
rectified, step-down, switch-mode converter.
Constant-on-time (COT) control is employed to
provide a fast transient response and ease loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned on when
the feedback voltage (VFB) falls below the
reference voltage (VREF), which indicates an
insufficient output voltage. The on period is
determined by the output voltage and input
voltage to make the switching frequency constant
over the input voltage range.
After the on period elapses, the HS-FET is turned
off or enters an off state. It is turned on again
when VFB drops below VREF. By repeating this
operation, the converter regulates the output
voltage. The integrated low-side MOSFET (LSFET) is turned on when the HS-FET is in its off
state to minimize conduction loss. There is a
dead short between the input and GND if both
the HS-FET and LS-FET are turned on at the
same time. This is called a shoot-through. To
avoid a shoot-through, a dead time (DT) is
generated internally between HS-FET off and LSFET on, or LS-FET off and HS-FET on.
In CCM operation, the switching frequency is in
pulse-width modulation (PWM) mode and is fairly
constant.
Light-Load Power Save Mode
The inductor current decreases as the load
decreases. Once the inductor current reaches
zero, the operation switches from continuous
conduction mode (CCM) to discontinuous
conduction mode (DCM).
The power save mode operation is shown in
Figure 3. When VFB is below VREF, the HS-FET is
turned on for a fixed interval, which is determined
by a one-shot on-timer, as shown in Equation 1.
When the HS-FET is turned off, the LS-FET is
turned on until the inductor current reaches zero.
In DCM operation, VFB cannot reach VREF while
the inductor current is approaching zero. The LSFET driver switches to tri-state (high-Z) whenever
the inductor current reaches zero. As a result, the
efficiency at light load is greatly improved. In
light-load condition, the HS-FET is not turned on
as frequently as in heavy-load condition. This is
called skip mode.
At light-load or no-load condition, the output
drops very slowly, and the MP8756 reduces the
switching frequency to achieve high efficiency.
Internal compensation is applied for COT control
to make a more stable operation, even when
ceramic capacitors are used as output capacitors.
This internal compensation improves jitter
performance without affecting line or load
regulation.
Heavy-Load Operation
Continuous conduction mode (CCM) occurs
when the output current is high and the inductor
current is always above zero amps (see Figure 2).
When VFB is below VREF, the HS-FET is turned on
for a fixed interval. When the HS-FET is turned
off, the LS-FET is turned on until the next period.
Figure 3: Light-Load Operation
As the output current increases from light-load
condition, the current modulator regulation time
period becomes shorter. The HS-FET is turned
on more frequently, so the switching frequency
increases correspondingly. The output current
reaches critical levels when the current
modulator time is zero. The critical level of the
output current is determined with Equation (1):
IOUT
Figure 2: Heavy-Load Operation
MP8756 Rev. 1.11
12/14/2018
(VIN VOUT ) VOUT
2 L FSW VIN
(1)
The device enters PWM mode once the output
current exceeds critical levels. Afterward, the
switching frequency remains fairly constant over
the output current range.
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12
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
DC Auto-Tune Loop
The MP8756 applies a DC auto-tune loop to
balance the DC error between VFB and VREF by
adjusting the comparator input REF to make VFB
follow VREF. This is a slow loop, so the load and
line regulation improve without affecting the
transient performance. The relationship between
VFB, VREF, and REF is shown in Figure 4.
Figure 4: DC Auto-Tune Loop Operation
External Ramp for Low Output Voltage
The
MP8756
uses
an
internal
ramp
compensation control scheme to improve stability
with a pure ceramic output capacitor. In some
operating cases, the internal ramp amplitude is
not sufficient to make the loop stable with
ceramic capacitors. Therefore, an extra external
ramp around 20mV is needed for loop
stabilization. Please refer to the Component
Selection section on page 15 for details.
Large Duty Operation
The MP8756 can support larger duty operations
with its internal TON extension function. When the
part detects that FB is lower than VREF, and VIN VOUT < 2V, TON and the duty cycle can be
extended. TON stops extending if FB is greater
than REF or if TON meets its limitation.
Light-Load Ultrasonic Mode (USM)
Ultrasonic mode (USM) is used to keep the
switching frequency above audible frequency
areas during light-load or no-load conditions.
Once the part detects that both the HS-FET and
LS-FET are off for about 32µs, TON shrinks to
keep VOUT under regulation with optimal
efficiency. If the load continues reducing, then
the part discharges VOUT to ensure that FB is
smaller than 102% of the internal reference. The
HS-FET turns on again once the internal FB
reaches VREF and then stops switching.
Configuring the EN Control
To start up the MP8756 automatically, pull EN up
to the input voltage through a resistive voltage
divider. Please refer to the UVLO Protection
Section on page 14 for details.
MODE Selection
MODE is used to select the MP8756’s working
mode. Pull MODE higher than 2.6V to operate
the MP8756 in forced PWM mode. Float MODE
to operate the MP8756 in PFM mode with USM
at light load. Connect MODE to ground to
operate the MP8756 in PFM mode without USM.
Soft Start (SS)
The MP8756 employs a soft-start (SS)
mechanism to ensure a smooth output during
power-up. When EN rises high, the internal
reference voltage and the output voltage ramp up
gradually. Once the reference voltage reaches its
target value, the soft start finishes and the circuit
enters steady-state operation.
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high-side and low-side switches until the
voltage on the internal reference exceeds the
sensed output voltage at the internal FB node.
Power Good (PG)
The MP8756 uses a power good (PG) output to
indicate whether the output voltage of the buck
regulator is ready or not. PG is the open drain of
the MOSFET and should be connected to VCC
or another voltage source through a resistor (e.g.:
100k). After the input voltage is applied, the
MOSFET is turned on and PG is pulled to GND
before SS is ready. Once the FB voltage reaches
95% of VREF, PG is pulled high after a 500µs
delay. When the FB voltage drops to 85% of VREF,
PG is pulled low. When the output voltage is
higher than 115% of the internal reference, PG is
pulled low. PG rises high again after the output
voltage drops below 105% of the internal
reference voltage.
USM is selected by the MODE setting. Float
MODE to operate the MP8756 in PFM mode with
USM in light-load condition.
MP8756 Rev. 1.11
12/14/2018
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13
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
Over-Current Protection (OCP)
The MP8756 has a cycle-by-cycle over-current
limiting control. The current-limit circuit employs a
valley current-sensing algorithm. The part uses
the RDS(ON) of the LS-FET as a current-sensing
element. If the magnitude of the current-sense
signal is above the current-limit threshold, PWM
is not allowed to initiate a new cycle.
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
and SW. GND is used as the positive current
sensing node so that GND should be connected
to the source terminal of the bottom MOSFET.
Since the comparison is done during the HS-FET
off and LS-FET on states, the OC trip level sets
the valley level of the inductor current. Thus, the
load current at the over-current threshold (IOC)
can be calculated with Equation (2):
IOC I _ limit
Iinductor
2
(2)
Under-Voltage Lockout (UVLO) Protection
The MP8756 can start up only when VIN is
higher than the under-voltage lockout (UVLO)
rising threshold voltage. The MP8756 shuts down
when VIN is lower than its falling threshold. The
UVLO protection is non-latch off.
If an application requires a higher UVLO, use EN
to adjust the input voltage UVLO by adding two
external resistors (see Figure 5).
It is recommended to use the resistor divider to
set the EN voltage above the EN rising threshold
and below the 4.5V absolute maximum rating.
The rising threshold should be set to provide
enough hysteresis to allow for any input supply
variations.
To avoid an excessive sink current on EN, keep
the EN resistor (RUP) in the range of 1MΩ - 2MΩ.
A typical pull-up resistor is 1.5MΩ. The RDOWN
value can then be determined by RUP and a
600kΩ internal pull-down resistor.
In an over-current condition, the current to the
load exceeds the current to the output capacitor,
and the output voltage can fall off. As a result,
the device encounters the under-voltage
protection threshold and hiccup.
Over-/Under-Voltage Protection (OVP/UVP)
The MP8756 monitors the output voltage to
detect over-voltage and under-voltage. Once the
feedback voltage rises higher than 122% of the
feedback voltage, the OVP comparator output
goes high and the circuit turns off the HS-FET
driver. The LS-FET driver turns on, acting as a
current source. The output is then discharged to
remain within the normal range. The MP8756
exits this regulation period when the feedback
voltage falls below 117% of the reference voltage.
When the feedback voltage falls below 75% of
VREF but is higher than 50%, the UVP-1
comparator output goes high, and the part
attempts to restart with hiccup mode periodically
for about 50µs if the feedback voltage remains in
this range.
When the feedback voltage falls below 50% of
VREF, the UVP-2 comparator output goes high
and the part enters hiccup mode directly after the
comparator and logic delay.
MP8756 Rev. 1.11
12/14/2018
Figure 5: Adjustable UVLO
Connecting EN directly to a voltage source
without a pull-up resistor requires limiting the
amplitude of the voltage source. The EN voltage
must not exceed the 4.5V absolute maximum
rating to avoid damaging the IC.
Thermal Shutdown
The MP8756 employs thermal shutdown. The
junction temperature of the IC is monitored
internally. If the junction temperature exceeds the
threshold value (typically 150°C), the converter
shuts off. This is a non-latch protection. There is
a hysteresis of about 25°C. Once the junction
temperature drops to about 125°C, a soft start is
initiated.
Output Discharge
When EN is low, the MP8756 discharges the
output using an internal 6Ω MOSFET.
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14
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
APPLICATION INFORMATION
COMPONENT SELECTION
Setting the Output Voltage with an ECapacitor or POS Capacitor
For applications that use an electrolytic capacitor
or POS capacitor with a controlled ESR output is
set
as
an
output
capacitor,
external
compensation is not need. The output voltage is
set by feedback resistors R1 and R2 (see Figure
6).
SW
L
Vo
R1
FB
R2
ESR
Figure 7: Feedback Network
When the internal ramp compensation is not
enough to stabilize the loop with a pure ceramic
capacitor, an extra external voltage ramp around
20mV should be added to FB through resistor R4
and capacitor C5.
POSCAP
Figure 6: Simplified Circuit of POS Capacitor
The value for R2 must be chosen carefully since
a small R2 value leads to considerable quiescent
current loss, while a value that is too large makes
FB noise sensitive. R2 is recommended to be
within 5kΩ - 100kΩ. Typically, set the current
through R2 between 5µA - 30µA to create a good
balance between the system stability and no-load
loss. Considering the output ripple, calculate R1
with Equation (3):
R1
VOUT VREF
R2
VREF
(3)
Setting the Output Voltage with a Pure
Ceramic Output Capacitor
The
MP8756
employs
internal
ramp
compensation. When the internal compensation
is enough for stable operation with the ceramic
output capacitors, the external resistor divider is
used to set VOUT. First, choose a value for R2.
Then R1 can be determined with Equation (4):
R1
VOUT VREF
R2
VREF
Figure 8: External Ramp Compensation
Figure 8 shows a simplified external ramp
compensation for PWM mode. Vramp on FB can
be estimated with Equation (5):
Vramp
Vin Vout
Ton
R4 C5
(5)
For better load or line regulation, use a lower
Vramp. Usually, Vramp is recommended to be
around 20mV.
The MP8756 employs a DC auto-tune loop to
balance the DC error between VFB and VREF. VFB
can maintain 0.6V, even with an external ramp
compensation circuit. Figure 9 shows the DC
equivalent circuit with an external ramp circuit.
(4)
The feedback circuit is shown in Figure 7.
Figure 9: Equivalent DC Circuit
MP8756 Rev. 1.11
12/14/2018
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15
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
Calculate R2 first, and then calculate R1 with
Equation (6):
1
(6)
R1=
VFB
1
R2 (VOUT -VFB ) R4 +R9
Usually, R9 is set to 499Ω. It should be five times
smaller than R1//R2 to minimize its influence on
Vramp. R9 can also be set for better noise
immunity with Equation (7):
R9
1
2 C4 2FSW
(7)
Table 1 lists the recommended resistor values for
common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
VOUT
(V)
R1
(kΩ)
R2
(kΩ)
L
(μH)
R4
(kΩ)
C5
(pF)
1
48.7
66.5
0.68
499
220
1.2
52.3
47
0.95
499
220
1.5
82.5
47
0.95
499
220
1.8
115
47
0.95
499
220
2.5
43.2
12.7
1.2
499
330
3.3
43
9.63
1.5
NS
NS
5
41.2
5.6
1.5
NS
NS
VOUT
V
(1 OUT )
FSW IL
VIN
VOUT
V
(1 OUT )
2FSW L
VIN
(9)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply AC current to the step-down converter
while maintaining the DC input voltage. Use
ceramic capacitors placed as close to VIN as
possible for best performance. Capacitors with
X5R and X7R ceramic dielectrics are
recommended because they are fairly stable with
temperature fluctuations.
VOUT
V
(1 OUT )
VIN
VIN
ICIN IOUT
(10)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (11):
ICIN
(8)
Where ∆IL is the peak-to-peak inductor ripple
current.
MP8756 Rev. 1.11
12/14/2018
ILP IOUT
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated with Equation (10):
Selecting the Inductor
The inductor is necessary for supplying a
constant current to the output load while being
driven by the switched input voltage. An inductor
with a larger value results in less ripple current
and a lower output ripple voltage. However, it
also has a larger physical footprint, higher series
resistance, and lower saturation current. A good
rule for determining the inductance value is to
design the peak-to-peak ripple current in the
inductor to be in the range of 30% to 40% of the
maximum output current to ensure that the peak
inductor current is below the maximum switch
current limit. The inductance value can be
calculated with Equation (8):
L
The inductor should not saturate under the
maximum inductor peak current. The peak
inductor current can be calculated with Equation
(9):
IOUT
2
(11)
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
an input capacitor that meets the specification.
The input voltage ripple can be estimated with
Equation (12):
VIN
IOUT
V
V
OUT (1 OUT )
FSW CIN VIN
VIN
(12)
Under worst-case conditions where VIN = 2VOUT,
use Equation (13):
VIN
IOUT
1
4 FSW CIN
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(13)
16
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POS capacitors
are recommended. The output voltage ripple can
be estimated with Equation (14):
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (14)
FSW L
VIN
8 FSW COUT
With ceramic capacitors, the impedance at the
switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated with
Equation (15):
VOUT
VOUT
V
(1 OUT )
8 FSW 2 L COUT
VIN
(15)
In the case of POS capacitors, the ESR
dominates the impedance at the switching
frequency.
The
output
ripple
can
be
approximated with Equation (16):
VOUT
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(16)
PCB Layout Guidelines
Efficient PCB layout is critical for stable operation.
A four-layer layout is strongly recommended to
achieve a better thermal performance. For best
results, refer to Figure 10 and follow the
guidelines below.
1. Place the high current paths (GND, IN, and
SW) very close to the device with short, direct,
and wide traces.
2. Place the input capacitors as close to IN and
GND as possible.
3. Place the decoupling capacitor as close to
VCC and GND as possible.
4. Keep the switching node SW short and away
from the feedback network.
5. Keep the BST voltage path as short as
possible with traces greater than 50mil.
6. Keep the IN and GND pads connected with
large copper traces to achieve better thermal
performance.
7. Add several vias with 10mil drill/18mil copper
width close to the IN and GND pads to help
with thermal dissipation.
The maximum output capacitor limitation should
be also considered during the design application.
If the output capacitor value is too high, the
output voltage cannot reach the design value
during the soft-start time and fails to regulate.
The maximum output capacitor value (Co_MAX)
can be limited approximately with Equation (17):
CO _ MAX (ILIM _ AVG IOUT ) Tss / VOUT
(17)
Where ILIM_AVG is the average start-up current
during a soft-start period, and Tss is the soft-start
time. The inductance value can be calculated
with Equation (18):
L
VOUT
V
(1 OUT )
FSW IL
VIN
(18)
Where ∆IL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current, including short
currents. Isat is recommended to be greater than
11.3A.
MP8756 Rev. 1.11
12/14/2018
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17
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
Figure 10: Recommend Layout
Design Example
Table 2 is a design example following the
application guidelines for the specifications below:
Table 2: Design Example
12V
VIN
1V
VOUT
6A
IOUT
MP8756 Rev. 1.11
12/14/2018
The detailed application schematic for the 1V
VOUT is shown in Figure 17. The typical
performance and waveforms are shown in the
Typical Characteristics Section. For more device
applications, please refer to the related
evaluation board datasheet.
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18
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
PG
VCC
AGND
PGND
BST
TYPICAL APPLICATION CIRCUITS
AGND
PGND
VCC
PG
BST
Figure 11: VIN = 12V(6), Vo = 5V, Io = 6A Application Schematic with Ceramic Output Capacitors
Figure 12: VIN = 12V(6), Vo = 3.3V, Io = 6A Application Schematic with Ceramic Output Capacitors
Figure 13: VIN = 12V 6), Vo = 2.5V, Io = 6A Application Schematic with Ceramic Output Capacitors
MP8756 Rev. 1.11
12/14/2018
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19
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 14: VIN = 12V(6), Vo = 1.8V, Io = 6A Application Schematic with Ceramic Output Capacitors
R3
3.3Ω
C3
220nF
8
VIN
1
100µF
Optional
C1A
22µF
C1B
22µF
C1C
100nF
R5
1.5M
R6
NC
GND
4
12
6
SW 7
VIN
NC
L1
0.95µH
R4
499K
1.5V
VOUT
C5
220pF
EN
MODE
11
FB
VOUT 5
GND
R1
82.5k
C2A
NC
C2B
100nF
C2C
22µF
C2D
22µF
C2E
22µF
C2F
22µF
R9
499
C2G
100nF
GND
R2
47k
VOUT
AGND
3
R8
100k
R10
NC
VCC
9
10
C4
1µF
2
C6
100nF
R7
NC
AGND
GND
Figure 15: VIN = 12V(6), Vo = 1.5V, Io = 6A Application Schematic with Ceramic Output Capacitors
R3
3.3Ω
C3
220nF
8
VIN
1
100µF
Optional
C1A
22µF
C1B
22µF
C1C
100nF
R5
1.5M
R6
NC
GND
4
12
6
SW 7
VIN
NC
R4
499K
L1
0.95µH
1.2V
VOUT
C5
220pF
EN
MODE
C2A
NC
C2B
100nF
C2C
22µF
C2D
22µF
C2E
22µF
C2F
22µF
R9
499
11
FB
VOUT 5
GND
R1
52.3k
C2G
100nF
GND
R2
47k
VOUT
AGND
VCC
R10
NC
3
R8
100k
9
10
C4
1µF
2
C6
100nF
R7
NC
AGND
GND
Figure 16: VIN = 12V(6), Vo = 1.2V, Io = 6A Application Schematic with Ceramic Output Capacitors
MP8756 Rev. 1.11
12/14/2018
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20
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 17: VIN = 12V(6), Vo = 1.0V, Io = 6A Application Schematic with Ceramic Output Capacitors
NOTE:
6) The EN resistor divider value should be modified accordingly with different input voltages. Please refer to the UVLO Protection section for
details.
MP8756 Rev. 1.11
12/14/2018
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21
MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-12 (2mmx3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8756 Rev. 1.11
12/14/2018
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