MP8764
High Efficiency, 12A, 18V
Synchronous Step-Down Converter
with Latch-off OCP
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP8764 is a fully integrated high frequency
synchronous rectified step-down switch mode
converter. It offers a very compact solution to
achieve 12A output current over a wide input
supply range with excellent load and line
regulation. The MP8764 operates at high
efficiency over a wide output current load range.
The MP8764 adopts Constant-On-Time (COT)
control mode that provides fast transient
response and eases loop stabilization.
Operation frequency can be programmed easily
from 200kHz to 1MHz by an external resistor
and keeps nearly constant as input supply
varies by the feedforward compensation.
VCC under voltage lockout is internally set at
3.9V, but can be increased by programming the
threshold with a resistor network on the enable
pin. The output voltage startup ramp is
controlled by the soft start pin. An open drain
power good signal indicates the output is within
its nominal voltage range.
2.5V to 18V Operating Input Range with
External 5V Bias
4.5V to 18V Operating Input Range with
Internal Bias
12A Output Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Technique
Adaptive COT for Ultrafast Transient
Response
1.5% Reference Voltage Over -40C to
+125C Junction Temperature Range
Programmable Soft Start Time
Pre-Bias Start up
Programmable Switching Frequency from
200kHz to 1MHz
OVP, latch-off SCP, Protection and Thermal
Shutdown
Output Adjustable from 0.611V to 13V
APPLICATIONS
Full integrated protection features include OCP,
OVP and thermal shutdown.
The MP8764 requires a minimum number of
readily available standard external components
and are available in QFN 3X4 package.
Set-top Boxes
XDSL Modem/DSLAM
Small-cell Base Stations
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
IN
C1
FREQ
ON/OFF
BST
C3
RFREQ
MP8764
VOUT
EN
R4
R1
C2
C4
FB
VCC
C5
L1
SW
R2
SS
R3
C6
PG PGND
MP8764 Rev. 1.2
2/26/2020
AGND
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1
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8764GLE
16-Pin QFN（3X4mm）
MP8764
E
* For Tape & Reel, add suffix –Z (e.g. MP8764GLE–Z);
PACKAGE REFERENCE
TOP VIEW
EN
1
FREQ
2
FB
3
SS
4
AG ND
5
PG
6
VCC
7
BST
8
IN
PG ND
PG ND
14
13
12
15
16
SW
SW
9
10
11
IN
PG ND
PG ND
16-Pin QFN (3x4mm)
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ........................................ 21V
VSW ........................................ -0.3V to VIN + 0.3V
VSW (30ns) ................................... -3V to VIN + 3V
VBST........................................................ VSW + 6V
Enable Current IEN(2)................................ 2.5mA
All Other Pins ................................. –0.3V to +6V
Continuous Power Dissipation (TA=+25)(3)
QFN3X4……………………….…..…………2.7W
Junction Temperature ............................... 150C
Lead Temperature .................................... 260C
Storage Temperature ................-65C to +150C
Recommended Operating Conditions (4)
Thermal Resistance (5)
θJA
θJC
QFN (3x4mm) ......................... 46 ........ 9 .... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to the section “Configuring the EN Control”.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Supply Voltage VIN ........................... 4.5V to 18V
Output Voltage VOUT ..................... 0.611V to 13V
IEN ................................................... 0mA to 1mA
Operating Junction Temp. (TJ). -40°C to +125°C
MP8764 Rev. 1.2
2/26/2020
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2
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = +25C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
VEN = 0V
VEN = 2V, VFB = 1V
760
0
860
1
960
μA
μA
Supply Current
Supply Current (Shutdown)
Supply Current (Quiescent)
IIN
IIN
MOSFET
High-side Switch On Resistance
HSRDS-ON
TJ =25C
21
mΩ
Low-side Switch On Resistance
LSRDS-ON
TJ =25C
VEN = 0V, VSW = 0V or 12V
7
mΩ
Switch Leakage
SWLKG
0
1
μA
Current Limit
Low-side Valley Current Limit (6)
Low-side Negative Current Limit
(6)
ILIMIT_VALLEY
12
ILIMIT_NEGATIVE
-4
A
-2.5
-1
A
Timer
Minimum On Time (6)
One-Shot On Time
Minimum Off Time(6)
TON_MIN
TON
TOFF_MIN
RFREQ=453kΩ, VOUT=1.2V
30
250
180
ns
ns
ns
130%
VFB
Over-voltage and Under-voltage Protection
OVP Latch Threshold (6)
OVP Non-latch Threshold
OVP Delay
UVP Threshold
(6)
VOVP_LATCH
VOVP_NON-
117%
LATCH
120%
123%
VFB
TOVP
2
μs
VUVP
50%
VFB
Reference And Soft Start
Reference Voltage
VREF
TJ = -40C to +125C (7)
602
611
620
TJ = +25C
605
611
617
50
100
nA
16
20
25
μA
1.1
1.3
1.5
V
Feedback Current
IFB
VFB = 650mV
Soft Start Charging Current
ISS
VSS=0V
mV
Enable And UVLO
Enable Input Low Voltage
Enable Hysteresis
Enable Input Current
MP8764 Rev. 1.2
2/26/2020
VILEN
VEN-HYS
IEN
VEN = 2V
VEN = 0V
250
0
0
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mV
μA
3
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = +25C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
3.75
3.9
4.05
V
VCC Regulator
VCC Under Voltage Lockout
Threshold Rising
VCC Under Voltage Lockout
Threshold Hysteresis
VCC Regulator
VCC Load Regulation
Power Good
Power Good Rising Threshold
Power Good Falling Threshold
Power Good Lower to High Delay
Power Good Sink Current
Capability
Power Good Leakage Current
VCCVth
VCCHYS
600
VCC
4.65
Icc=5mA
PGVth-Hi
PGVth-Lo
PGTd
4.8
0.5
mV
4.95
97%
90%
2.5
VPG
Sink 4mA
IPG_LEAK
VPG = 3.3V
10
V
%
VFB
VFB
ms
0.4
V
100
nA
Thermal Protection
Thermal Shutdown (6)
Thermal Shutdown Hysteresis (6)
TSD
150
25
°C
°C
Note:
6) Guaranteed by design
7) Not production test, guaranteed by characterization..
MP8764 Rev. 1.2
2/26/2020
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4
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
PIN FUNCTIONS
PIN#
16-Pin
QFN
Name
1
EN
2
FREQ
3
FB
4
SS
5
AGND
6
PG
7
VCC
8
BST
9, 14
IN
10,11,12,1
3
PGND
15, 16
SW
MP8764 Rev. 1.2
2/26/2020
Description
Enable pin. EN is a digital input that turns the regulator on or off. Drive EN high to
turn on the regulator, drive it low to turn it off. Connect EN to IN through a pull-up
resistor or a resistive voltage divider for automatic startup. Do not float this pin. See
Enable Control section for more details.
Frequency set during CCM operation. A resistor connected between FREQ and IN is
required to set the switching frequency. The ON time is determined by the input
voltage and the resistor connected to the FREQ pin. IN connect through a resistor is
used for line feed-forward and makes the frequency basically constant during input
voltage’s variation.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin,
sets the output voltage. It is recommended to place the resistor divider as close to FB
pin as possible. Vias should be avoided on the FB traces.
Soft Start. Connect an external capacitor to program the soft start time for the switch
mode regulator.
Analog ground. Select this pin as the control circuit reference point.
Power good output, the output of this pin is an open drain signal and a pull-up
resistor connected to a DC voltage is required to indicate high if the output voltage is
higher than 97% of the nominal voltage. There is a delay from FB ≥ 97% to PG goes
high.
Internal 4.8V LDO output. The driver and control circuits are powered from this
voltage. Decouple with a minimum 1µF ceramic capacitor as close to the pin as
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Bootstrap. A capacitor connected between SW and BST pins is required to form a
floating supply across the high-side switch driver.
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP8764 operates from a +2.5V to +18V input rail with 5V external bias and a +4.5V
to +18V input rail with internal bias. An input capacitor is needed to decouple the
input rail. Use wide PCB traces and multiple vias to make the connection.
System Ground. This pin is the reference ground of the regulated output voltage. For
this reason care must be taken in PCB layout. Use wide PCB traces to make the
connection.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
duty cycle. The inductor current drives the SW pin negative during the off-time. The
on-resistance of the low-side switch and the internal Schottky diode fixes the
negative voltage. Use wide PCB traces to make the connection.
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MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3V, L = 1µH, TA = 25ºC, unless otherwise noted.
MP8764 Rev. 1.2
2/26/2020
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6
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3V, L = 1µH, TA = 25ºC, unless otherwise noted.
MP8764 Rev. 1.2
2/26/2020
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MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3V, L = 1µH, TA = 25ºC, unless otherwise noted.
MP8764 Rev. 1.2
2/26/2020
www.MonolithicPower.com
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8
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3V, L = 1µH, TA = 25ºC, unless otherwise noted.
Input/Output Voltage
Ripple
Input/Output Voltage
Ripple
Start Up through Input
Voltage
IOUT=0A
IOUT=12A
IOUT=0A
VOUT
AC Coupled
50mV/div.
VOUT
AC Coupled
20mV/div.
VIN
AC Coupled
100mV/div.
VOUT
2V/div.
VIN
10V/div.
VPG
5V/div.
VIN
AC Coupled
500mV/div.
VSW
10V/div.
VSW
10V/div.
VSW
5V/div.
IL
10A/div.
IL
2A/div.
IL
2A/div.
Start Up through Input
Voltage
Shutdown through Input
Voltage
Shutdown through Input
Voltage
IOUT=12A
IOUT=0A
VOUT
2V/div.
VIN
4V/div.
VPG
5V/div.
VOUT
2V/div.
VIN
10V/div.
VPG
5V/div.
VSW
5V/div.
VSW
10V/div.
IL
1A/div.
IL
10A/div.
IOUT=12A
VOUT
2V/div.
VIN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
10A/div.
Start Up through EN
Shutdown through EN
Start Up through Enable
IOUT=10mA
IOUT=10mA
IOUT=12A
VOUT
2V/div.
VEN
5V/div.
VPG
5V/div.
VOUT
2V/div.
VEN
5V/div.
VOUT
2V/div.
VPG
5V/div.
VEN
5V/div.
VPG
5V/div.
VSW
10V/div.
VSW
10V/div.
VSW
10V/div.
IL
2A/div.
IL
2A/div.
IL
10A/div.
MP8764 Rev. 1.2
2/26/2020
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MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3V, L = 1µH, TA = 25ºC, unless otherwise noted.
Shutdown through Enable
Short Circuit Protection
IOUT=12A
VOUT
50mV/div.
VOUT
2V/div.
VEN
5V/div.
VPG
5V/div.
VOUT
1V/div.
VPG
5V/div.
VSW
10V/div.
VSW
10V/div.
IOUT
5A/div.
IL
10A/div.
Thermal Recovery
Thermal Shutdown
IOUT=0A, VOUT=3V
IOUT=0A, VOUT=3V
VOUT
1V/div.
VOUT
1V/div.
VSW
5V/div.
VSW
5V/div.
IL
2A/div.
IL
2A/div.
MP8764 Rev. 1.2
2/26/2020
IL
10A/div.
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MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
BLOCK DIAGRAM
Figure 1—Functional Block Diagram
MP8764 Rev. 1.2
2/26/2020
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11
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
OPERATION
PWM Operation
The MP8764 is fully integrated synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned ON when
the feedback voltage (VFB) is below the reference
voltage (VREF), which indicates insufficient output
voltage. The ON period is determined by the
input voltage and the frequency-set resistor as
follows:
6.1 R FREQ (k)
(1)
TON (ns)
VIN ( V ) 0.4
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through, a dead-time (DT) is
internally generated between HS-FET off and LSFET on, or LS-FET off and HS-FET on.
Heavy-Load Operation
interval which is determined by one-shot on-timer
as equation 1 shown. When the HS-FET is
turned off, the LS-FET is turned on until next
period.
In CCM mode operation, the switching frequency
is fairly constant and it is called PWM mode.
Light-Load Operation
As the load decreases, the inductor current
decreases too. When the inductor current
touches zero, the operation is transited from
continuous-conduction-mode
(CCM)
to
discontinuous-conduction-mode (DCM).
The light load operation is shown in Figure 3.
When VFB is below VREF, HS-FET is turned on for
a fixed interval which is determined by one- shot
on-timer as equation 1 shown. When the HS-FET
is turned off, the LS-FET is turned on until the
inductor current reaches zero. In DCM operation,
the VFB does not reach VREF when the inductor
current is approaching zero. The LS-FET driver
turns into tri-state (high Z) whenever the inductor
current reaches zero. A current modulator takes
over the control of LS-FET and limits the inductor
current to less than -1mA. Hence, the output
capacitors discharge slowly to GND through LSFET. As a result, the efficiency at light load
condition is greatly improved. At light load
condition, the HS-FET is not turned ON as
frequently as at heavy load condition. This is
called skip mode.
At light load or no load condition, the output
drops very slowly and the MP8764 reduces the
switching frequency naturally and then high
efficiency is achieved at light load.
Figure 2—Heavy Load Operation
When the output current is high and the inductor
current is always above zero amps, it is called
continuous-conduction-mode (CCM). The CCM
mode operation is shown in Figure 2. When VFB
is below VREF, HS-FET is turned on for a fixed
MP8764 Rev. 1.2
2/26/2020
Figure 3—Light Load Operation
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12
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
IOUT
( VIN VOUT ) VOUT
2 L FSW VIN
(2)
Where FSW is the switching frequency.
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
High switching frequency makes it possible to
utilize small sized LC filter components to save
system PCB space.
Jitter and FB Ramp Slope
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
HS-FET deviates from its intended location and
produces jitter. It is necessary to understand that
there is a relationship between a system’s
stability and the steepness of the VFB ripple’s
downward slope. The slope steepness of the VFB
ripple dominates in noise immunity. The
magnitude of the VFB ripple doesn’t affect the
noise immunity directly.
Switching Frequency
The selection of switching frequency is a tradeoff
between efficiency and component size. Low
frequency operation increases efficiency by
reducing MOSFET switching losses, but requires
larger inductance and capacitance to maintain
low output voltage ripple.
For MP8764 ， the on time can be set using
FREQ pin, then the frequency is set in steady
state operation at CCM mode.
Adaptive constant-on-time (COT) control is used
in MP8764 and there is no dedicated oscillator in
the IC. Connect FREQ pin to IN pin through
resistor RFREQ and the input voltage is feedforwarded to the one-shot on-time timer through
the resistor RFREQ. When in steady state
operation at CCM, the duty ratio is kept as
VOUT/VIN. Hence the switching frequency is fairly
constant over the input voltage range. The
switching frequency can be set as follows:
FSW (kHz )
6
10
(3)
6.1 R FREQ (k) VIN ( V )
TDELAY (ns)
VIN ( V ) 0.4
VOUT ( V )
Where TDELAY is the comparator delay. It’s about
5ns. After adding load, the frequency may be
affected a little because power MOSFET voltage
drop will affect the duty cycle.
Figure 4—Jitter in PWM Mode
Figure 5—Jitter in Skip Mode
Ramp with Large ESR Capacitor
In the case of POSCAP or other types of
capacitor with lager ESR is applied as output
capacitor, the ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 6 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
Generally, the MP8764 is set for 200kHz to
1MHz application. It is optimized to operate at
high switching frequency with high efficiency.
MP8764 Rev. 1.2
2/26/2020
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13
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
information section for design steps with large
ESR capacitors.
SW
FB
ESR
R1
VRAMP
POSCAP
R2
To realize the stability when no external ramp is
applied, usually the ESR value should be chosen
as follow:
TSW
T
ON
2
0.7
COUT
(4)
Where TSW is the switching period.
Ramp with Small ESR Capacitor
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps.
VOUT
L
SW
R4
VSLOPE1
IC4
(8)
As can be seen from equation 8, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 5, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 9.
TSW
T
ON RESR COUT
I 10 3
2
VSLOPE1 0.7
VOUT OUT
2 L COUT
TSW TON
(9)
Where IOUT is the load current.
In skip mode, the downward slope of the VFB
ripple is almost same whether the external ramp
is used or not. Fig.8 shows the simplified circuit
of the skip mode when both the HS-FET and LSFET are off.
VOUT
R1
IFB
FB
Ceramic
FB
(7)
VOUT
VRAMP
TOFF
R 4 C4
C4
IR4
R9
VIN VOUT
R1 // R2
TON
R 4 C4
R1 // R2 R9
The downward slope of the VFB ripple then
follows:
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
RESR
(6)
IR 4 I C 4 IFB IC 4
And the ramp on the VFB can then be estimated
as:
VOUT
L
Where:
R1
C OUT
R2
ROUT
R2
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
In PWM mode, an equivalent circuit with HS-FET
off and the use of an external ramp
compensation circuit (R4, C4) is simplified in
Figure 7. The external ramp is derived from the
inductor ripple current. If one chooses C4, R9,
R1 and R2 to meet the following condition:
1
2 FSW C4
MP8764 Rev. 1.2
2/26/2020
1 R1 R2
R9
5 R1 R2
Figure 8—Simplified Circuit in skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follows:
VSLOPE 2
VREF
[(R1 R2) // ROUT ] COUT
(10)
Where ROUT is the equivalent load resistor.
(5)
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MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
As described in Fig.5, VSLOPE2 in the skip mode is
lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during ultra light load condition, the values of the
VFB resistors should not be too big, however, that
will decrease the light load efficiency.
Configuring the EN Control
En high to turn on the regulator and EN low to
turn it off. Do not float the pin.
For automatic start-up the EN pin can be pulled
up to input voltage through a resistive voltage
divider. Choose the values of the pull-up resistor
(RUP from VIN pin to EN pin) and the pull-down
resistor(RDOWN from EN pin to GND) to determine
the automatic start-up voltage:
VINSTART 1.5
(R UP R DOWN )
(V )
R DOWN
(11)
For example, for RUP=100kΩ and RDOWN=51kΩ,
the VIN-START is set at 4.44V.
To avoid noise, a 10nF ceramic capacitor from
EN to GND is recommended.
There is an internal zener diode on the EN pin,
which clamps the EN pin voltage to prevent it
from running away. The maximum pull up current
assuming a worst case 6V internal zener clamp
should be less than 1mA.
Therefore, when EN is driven by an external logic
signal, the EN voltage should be lower than 6V;
when EN is connected with VIN through a pull-up
resistor or a resistive voltage divider, the
resistance selection should ensure the maximum
pull up current less than 1mA.
If using a resistive voltage divider and VIN higher
than 6V, the allowed minimum pull-up resistor
RUP should meet the following equation:
VIN 6V
6V
1mA
R UP
R DOWN
(12)
Especially, just using the pull-up resistor RUP (the
pull-down resistor is not connected), the VIN-START
is determined by VCC UVLO, and the minimum
resistor value is:
R UP
MP8764 Rev. 1.2
2/26/2020
VIN 6V
( )
1mA
(13)
A typical pull-up resistor is 100kΩ.
External VCC bias
An external 5V VCC bias can disable the internal
LDO, in this case, Vin can be as low as 2.5V.
Soft Start
The MP8764 employs soft start (SS) mechanism
to ensure smooth output during power-up. When
the EN pin becomes high, an internal current
source (20μA) charges up the SS capacitor. The
SS capacitor voltage takes over the REF voltage
to the PWM comparator. The output voltage
smoothly ramps up with the SS voltage. Once the
SS voltage reaches the same level as the REF
voltage, it keeps ramping up while VREF takes
over the PWM comparator. At this point, the soft
start finishes and it enters into steady state
operation.
The SS capacitor value can be determined as
follows:
CSS nF
TSS ms ISS A
VREF V
(14)
If the output capacitors have large capacitance
value, it’s not recommended to set the SS time
too small. Otherwise, it’s easy to hit the current
limit during SS.
Pre-Bias Startup
The MP8764 has been designed for monotonic
startup into pre-biased loads. If the output is prebiased to a certain voltage during startup, the IC
will disable the switching of both high-side and
low-side switches until the voltage on the softstart capacitor exceeds the sensed output
voltage at the FB pin.
Power Good (PG)
The MP8764 have power-good (PG) output. The
PG pin is the open drain of a MOSFET. It should
be connected to VCC or other voltage source
that is less 5.5V through a pull-up resistor (e.g.
100k). After VCC is ready, the MOSFET is turned
on so that the PG pin is pulled to GND before SS
is ready. After FB voltage reaches 97% of REF
voltage, the PG pin is pulled high after a 2.5ms
delay.
When the FB voltage drops to 90% of REF
voltage or exceeds 120% of the nominal REF
voltage, the PG pin will be pulled low.
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15
MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP
If the MP8764 doesn’t work, the PG pin is also
pulled low even though this pin is tied to an
external DC source through a pull-up resistor(e.g.
100k).
Over-Current Protection (OCP)
The MP8764 features three current limit levels for
over-current conditions: high-side peak current
limit, low-side valley current limit and low-side
negative current limit.
High-side peak current limit: MP8764 has cycleby-cycle over-current limiting function. During
HS-FET ON state, the inductor current is
monitored. When the sensed inductor current hits
the peak current limit, the HS limit comparator
(shown in Figure 1) turns over, the device enters
over-current protection mode immediately, turns
off HS-FET and turns on LS-FET.
Low-side valley current limit: During LS-FET ON
state, the inductor current is also monitored. At
the end of OFF time, the LS-FET sourcing
current is compared to the internal positive valley
current limit. If the LS-FET sourcing current is
exceeded the valley current limit, the HS-FET is
not turned on and the LS-FET keeps on for the
next ON time. Until the LS-FET sourcing current
is below the valley current limit the HS-FET is
turned on again.
After soft-start ends, if the over-current condition
holds 180us, or VFB
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