MP8770C
3V to 17V, 8A, Synchronous
Step-Down Converter with Forced CCM
DESCRIPTION
FEATURES
The MP8770C is a fully integrated, highfrequency, synchronous rectified step-down
switch-mode converter with internal power
MOSFETs. The MP8770C offers a very compact
solution to achieve 8A of continuous output
current with excellent load and line regulation
over a wide input range. The MP8770C uses
synchronous mode operation for higher
efficiency over the output current load range.
Constant-on-time (COT) control operation
provides very fast transient response and easy
loop design, as well as very tight output
regulation.
Full protection features include short-circuit
protection (SCP), over-current protection (OCP),
under-voltage protection (UVP), and thermal
shutdown.
The MP8770C requires a minimal number of
readily available, standard external components,
and is available in a space-saving QFN-16
(3mmx3mm) package.
Wide 3V to 17V Operating Input Range
8A Output Current
22mΩ/10mΩ Low RDS(ON) Internal Power
MOSFETs
100μA Quiescent Current
Output Adjustable from 0.6V
High-Efficiency Synchronous Mode
Operation
Pre-Biased Start-Up
Fixed 700kHz Switching Frequency
Forced PWM Operation
External Programmable Soft-Start Time
EN and Power Good for Power Sequencing
Over-Current Protection (OCP) and Hiccup
Mode
Thermal Shutdown
Available in a QFN-16 (3mmx3mm)
Package
APPLICATIONS
Security Cameras
Portable Devices, XDSL Devices
Digital Set-Top Boxes
Flat-Panel Televisions and Monitors
General Purpose
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are registered
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
TYPICAL APPLICATION
Efficiency vs. Load Current
3V to 17V
VIN
BST
C1
22µFx2
C3
0.1µF L1
0.56µH
MP8770C
1V/8A
VOUT
SW
PG
PG
EN
ENABLE
R1
20kΩ
FB
R4
1kΩ
AGND
VCC
PGND
C4
1µF
SS
C5
22nF
R2
30kΩ
C2
22µFx4
EFFICIENCY (%)
VIN
VOUT
100
90
80
70
60
50
40
30
20
10
0
0.0
= 1V, L = 0.56μH, DCR = 1.5mΩ
Vin=5V
Vin=12V
2.0
4.0
6.0
LOAD CURRENT (A)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
8.0
1
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8770CGQ
QFN-16 (3mmx3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8770CGQ–Z).
TOP MARKING
BGC: Product code of MP8770CGQ
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
SW
16
NC
1
15
NC
BST
2
14
VCC
EN
3
13
PGND
FB
4
12
PGND
5
11
PGND
SS
6
10
PGND
PG
7
9
PGND
AGND
8
VIN
QFN-16 (3mmx3mm)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
2
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
1, 15
NC
2
3
4
5
6
7
8
9, 10,
11, 12,
13
14
16
Description
No connection. Pin must be left floating.
Bootstrap. A capacitor connected between the SW and BS pins is required to form a floating
supply across the high-side switch driver. It is recommended for the BST resistor to be less
than 4.7Ω.
Enable. Pull EN high to enable the MP8770C. When floating, EN is pulled down to GND by
EN
an internal 1.2MΩ resistor so it is disabled.
Feedback. Sets the output voltage when connected to the tap of an external resistor divider
FB
that is connected between output and GND.
Signal ground. AGND is not internally connected to the system ground. Ensure that AGND
AGND
is connected to the system ground in PCB layout.
Soft start. Connect a capacitor across SS and GND to set the soft-start time and avoid startSS
up inrush current.
Power good output. The output of this pin is an open drain. It will change state if UVP, OCP,
PG
OTP, or OV occurs.
Supply voltage. The MP8770C operates from a 3V to 17V input rail. C1 is needed to
VIN
decouple the input rail. Use a wide PCB trace to make the connection.
System ground. This pin is the reference ground of the regulated output voltage, so care
PGND must be taken during PCB layout. It is recommended to connect it to GND with copper pours
and vias.
Internal bias supply output. Decouple with a 1µF capacitor. The VCC capacitor should be
VCC
placed close to the VCC and GND pins.
BST
SW
Switch output. Use a wide PCB trace to make the connection.
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
VIN ................................................ -0.3V to +20V
VSW - 0.3V (-5V < 10ns) to + VIN +0.7V (23V <
10ns)
VBST .....................................................VSW + 4V
VEN ................................................................ VIN
All other pins .................................. -0.3V to +4V
Continuous power dissipation (TA = 25°C) (2) (4)
………………………………………………...3.2W
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +125°C
QFN-16 (3mmx3mm)
EV8770C-Q-00A (4) ...................38......10....°C/W
JESD51-7 (5)………….……….….50…..12…°C/W
Recommended Operating Conditions (3)
Supply voltage (VIN) ........................... 3V to 17V
Output voltage (VOUT) ............. 0.6V to VIN * DMAX
or 12V max
Operating junction temp ........... -40°C to +125°C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ (MAX)
- TA) / θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its operating
conditions.
4) Measured on EV8770C-Q-00A, 4-layer PCB.
5) The value of θJA given in this table is only valid for comparison
with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD51-7,
and simulated on a specified JEDEC board. They do not
represent the performance obtained in an actual application.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
3
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (6)
VIN = 12V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Input voltage range
Supply Current
VIN
Supply current (shutdown)
IIN
VEN = 0V
Supply current (quiescent)
MOSFET
IQ
VEN = 2V, VFB = 0.65V
100
VBST-SW = 3.3V
VCC = 3.3V
VEN = 0V, VSW = 17V
22
10
HS switch on resistance
LS switch on resistance
Switch leakage
Current Limit
HSRDS-ON
LSRDS-ON
SW LKG
3
Valley current limit
ILIMIT_VY
(7)
Short hiccup duty cycle
DHICCUP
Switching Frequency and Minimum On/Off Timer
Switching frequency
(7)
Minimum on time
Minimum off time (7)
Reference and Soft Start
fSW
700
17
V
5
µA
150
µA
1
mΩ
mΩ
µA
A
%
800
50
100
VEN RISING
1.1
1.25
1.4
V
VEN FALLING
0.9
1
1.1
V
ISS_START
EN rising threshold
EN falling threshold
594
591
ns
ns
4
IFB
TJ = 25°C
TJ = -40°C to +125°C
VFB = 700mV
kHz
606
609
50
8
Feedback current
Soft-start current
Enable and UVLO
VCC load regulation
600
Units
600
600
10
6
VFB
VCC under-voltage lockout
rising threshold
VCC under-voltage lockout
threshold
VCC regulator
10
10
tON_MIN
tOFF_MIN
Feedback voltage
EN pin pull-down resistor
VCC
8
Max
REN_PD
2.6
2.8
nA
µA
MΩ
1.2
VCCVth
mV
3
V
VCCHYS
350
mV
VCC
3.4
V
3
%
RegVCC
ICC = 5mA
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
4
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (continued) (6)
VIN = 12V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
PGUVvth_Hi
0.85
0.9
0.95
VFB
PGUVvth_Lo
0.75
0.80
0.85
VFB
PGOVvth_Hi
1.15
1.2
1.25
VFB
PGOVvth_Lo
1.05
1.1
1.15
VFB
Power Good
Power good UV rising
threshold
Power good UV falling
threshold
Power good OV rising
threshold
Power good OV falling
threshold
Power good delay
Power good sink current
capability
Power good leakage current
PGTd
Both edge
50
µs
VPG
Sink 4mA
0.4
V
IPG_LEAK
VPG = 5V
10
μA
Thermal Protection
Thermal shutdown (7)
Thermal hysteresis (7)
TSD
TSD-HYS
150
20
°C
°C
Notes:
6) Not tested in production. Guaranteed by over-temperature correlation.
7) Guaranteed by design and characterization test.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
5
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
VOUT = 1.2V, L = 0.56μH, DCR = 1.5mΩ
EFFICIENCY (%)
EFFICIENCY (%)
VOUT = 1V, L = 0.56μH, DCR = 1.5mΩ
Vin=5V
Vin=12V
Vin=17V
0.0
2.0
4.0
6.0
LOAD CURRENT (A)
100
90
80
70
60
50
40
30
20
10
0
EFFICIENCY (%)
EFFICIENCY (%)
80
70
60
Vin=5V
Vin=12V
Vin=17V
0
2.0
4.0
6.0
LOAD CURRENT (A)
8.0
EFFICIENCY (%)
EFFICIENCY (%)
Vin=18V
2.0
4.0
6.0
LOAD CURRENT (A)
8.0
VOUT = 3.3V, L = 1μH, DCR = 1.35mΩ
Vin=12V
Vin=17V
4.0
6.0
LOAD CURRENT (A)
Vin=12V
Efficiency vs. Load Current
Vin=5V
2.0
8.0
Vin=5V
0.0
VOUT = 2.5V, L = 0.82μH, DCR = 0.9mΩ
0.0
4.0
6.0
LOAD CURRENT (A)
100
90
80
70
60
50
40
30
20
10
0
Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
2.0
VOUT = 1.8V, L = 0.82μH, DCR = 0.9mΩ
100
90
0.0
Vin=17V
Efficiency vs. Load Current
VOUT = 1.5V, L = 0.56μH, DCR = 1.5mΩ
30
20
10
Vin=12V
0.0
8.0
Efficiency vs. Load Current
50
40
Vin=5V
8.0
100
90
80
70
60
50
40
30
20
10
0
Vin=5V
Vin=12V
Vin=17V
0.0
2.0
4.0
6.0
LOAD CURRENT (A)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
8.0
6
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
VIN = 3.3V, L = 0.68μH, DCR = 1.58mΩ
EFFICIENCY (%)
EFFICIENCY (%)
VOUT = 5V, L = 1.2μH, DCR = 1.8mΩ
Vin=7V
Vin=12V
Vin=18V
0.0
2.0
4.0
6.0
LOAD CURRENT (A)
100
90
80
70
60
50
40
30
20
10
0
8.0
LOAD REGULATION (%)
LOAD REGULATION (%)
VIN=5V
VIN=12V
VIN=17V
2
3
4
5
6
LOAD CURRENT (A)
7
8
8.0
2
3
4
5
6
LOAD CURRENT (A)
7
8
VOUT = 1.8V
VIN=5V
VIN=12V
VIN=17V
2
1
Load Regulation vs. Load Current
LOAD REGULATION (%)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
VIN=5V
VIN=12V
VIN=17V
0
VOUT = 1.5V
LOAD REGULATION (%)
4.0
6.0
LOAD CURRENT (A)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
Load Regulation vs. Load Current
1
2.0
VOUT = 1.2V
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
Vout=2.5V
Load Regulation vs. Load Current
VOUT = 1V
1
Vout=1.2V
0.0
Load Regulation vs. Load Current
0
Vout=0.9V
3
4
5
6
LOAD CURRENT (A)
7
8
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
VIN=5V
VIN=12V
VIN=17V
0
1
2
3
4
5
6
LOAD CURRENT (A)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
7
8
7
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
Load Regulation vs. Load Current
Load Regulation vs. Load Current
VOUT = 3.3V
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
VIN=5V
VIN=12V
VIN=17V
0
1
2
3
4
5
6
LOAD CURRENT (A)
7
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
LOAD REGULATION (%)
LOAD REGULATION (%)
VOUT = 2.5V
VIN=5V
VIN=12V
VIN=17V
0
8
Load Regulation vs. Load Current
1
2
3
4
5
6
LOAD CURRENT (A)
7
8
Line Regulation vs. Input Voltage
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
LINE REGULATION (%)
LOAD REGULATION (%)
VOUT = 5V
VIN=7V
VIN=12V
VIN=17V
0
1
2
3
4
5
6
7
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
8
Io=0.01A
Io=5A
Io=8A
3
5
LOAD CURRENT (A)
Case Temperature Rise vs. Output
Current
30
17
120
Vout=1V
Vout=3.3V
Vout=5V
35
15
Enabled Supply Current vs. Input
Voltage
ENABLED SUPPLY CURRENT
(μA)
CASE TEMPERATURE RISE(℃)
40
7
9
11
13
INPUT VOLTAGE (V)
110
100
25
20
15
10
5
0
90
80
70
60
50
40
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
3
5
7
9
11
13
15
17
INPUT VOLTAGE (V)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
8
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
DISABLED SUPPLY CURRENT
(μA)
Disabled Supply Current vs. Input
Voltage
5
4
3
2
1
0
3
5
7
9
11
13
15
17
INPUT VOLTAGE (V)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
9
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
Input/Output Ripple
Input/Output Ripple
IOUT = 0A
IOUT = 8A
CH1:
VOUT/AC
10mV/div.
CH2:
VIN/AC
500mV/div.
CH1:
VOUT/AC
10mV/div.
CH2: VIN/AC
20mV/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH4: IL
5A/div.
CH4: IL
10A/div.
2µs/div.
2µs/div.
Start-Up through Input Voltage
Start-Up through Input Voltage
IOUT = 0A
IOUT = 8A
CH1: VOUT
1V/div.
CH2: VIN
10V/div.
CHR1: VPG
5V/div
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH2: VIN
10V/div.
CH3: VSW
10V/div.
CH4: IL
10A/div.
CH3: VSW
10V/div.
CH4: IL
5A/div.
2ms/div.
2ms/div.
Shutdown through Input Voltage
Shutdown through Input Voltage
IOUT = 0A
IOUT = 8A
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH2: VIN
10V/div.
CH3: VSW
10V/div.
CH4: IL
5A/div.
CH2: VIN
10V/div.
CH3: VSW
10V/div.
CH4: IL
10A/div.
40ms/div.
40ms/div.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
10
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
Start-Up through EN
Start-Up through EN
IOUT = 0A
IOUT = 8A
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH2: VEN
5V/div.
CH2: VEN
5V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH4: IL
5A/div.
CH4: IL
10A/div.
2ms/div.
2ms/div.
Shutdown through EN
Shutdown through EN
IOUT = 0A
IOUT = 8A
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH1: VOUT
1V/div.
CHR1: VPG
5V/div.
CH2: VEN
5V/div.
CH2: VEN
5V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH4: IL
5A/div.
CH4: IL
10A/div.
400ms/div.
200µs/div.
Short-Circuit Protection Entry
Short-Circuit Protection Steady State
IOUT = 0A
Short output to GND
CH1: VOUT
1V/div.
CH2: VPG
5V/div.
CH1: VOUT
1V/div.
CH2: VPG
5V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH4: IL
10A/div.
CH4: IL
10A/div.
20ms/div.
10ms/div.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
11
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 0.56µH, TA = 25°C, unless otherwise noted.
Short-Circuit Protection Recovery
Load Transient
IOUT = 0A
IOUT = 4A to 8A
CH1:
VOUT/AC
100mV/div.
CH1: VOUT
1V/div.
CH2: VPG
5V/div.
CH3: VSW
10V/div.
CH4: IL
10A/div.
CH4: IOUT
5A/div.
20ms/div.
100µs/div.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
12
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
VIN
Bias &
Voltage
Reference
EN
Bootstrap
Regulator
BST
3.3V
LDO
VCC
Main Switch
(NCH)
HS
Driver
Iss
SS
SW
EA
On
Timer
AGND
Logic
Control
VCC
COMP
FB
BUF
LS
Driver
Ramp
PWM
Current
Modulator
90% VREF Rising
80% VREF Falling
Synchronous
Rectifier (NCH)
Current-Sense
Amplifier
PG
120% VREF Rising
110% VREF Falling
GND
Figure 1: Functional Block Diagram
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
13
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
The MP8770C is a fully integrated, synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. Figure 2 shows the simplified ramp
compensation block in the MP8770C. At the
beginning of each cycle, the high-side MOSFET
(HS-FET) is turned on when the feedback
voltage (VFB) is below the reference voltage
(VREF), which indicates insufficient output voltage.
The on period is determined by both the output
voltage and input voltage to make the switching
frequency fairly constant across the entire input
voltage range.
After the on period elapses, the HS-FET turns off.
The HS-FET turns on again when VFB drops
below VREF. By repeating this operation, the
converter regulates the output voltage.
The MP8770C operates in continuous
conduction mode (CCM). The integrated lowside MOSFET (LS-FET) turns on when the HSFET is in its off state to minimize conduction loss.
If both the HS-FET and LS-FET are turned on at
the same time, a dead short occurs between
input and GND. This is called shoot-through. In
order to avoid shoot-through, a dead time (DT) is
internally generated between the HS-FET off
and LS-FET on periods, or vice versa.
An internal compensation is applied for COT
control for more stable operation even when
ceramic capacitors are used as output
capacitors. This internal compensation improves
jitter performance without affecting the line or
load regulation.
REF
FB
On
Timer
BUF
RAMP
Logic
Control
L
VOUT
SW
RESR
Cout
RAMP
GENERATOR
PWM
R1
R2
Figure 2: Simplified Ramp Compensation Block
VCC Regulator
The 3.4V internal regulator powers most of the
internal circuitries. This regulator takes the VIN
input and operates in the full VIN range. When VIN
exceeds 3.4V, the output of the regulator is in full
regulation. When VIN falls below 3.4V, the
regulator output decreases following VIN. A 1μF
decoupling ceramic capacitor is needed at the
pin.
Enable
EN is a digital control pin that turns the regulator
on and off. Drive EN above 1.25V to turn on the
regulator, drive it below 1V to turn it off.
When floating, EN is pulled down to GND by an
internal 1.2MΩ resistor.
EN can be connected directly to VIN. It supports
a 17V input range.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The MP8770C’s UVLO comparator monitors the
output voltage of the internal regulator’s VCC.
The VCC UVLO rising threshold is about 2.8V,
while its falling threshold is 2.45V.
When the input voltage exceeds the UVLO rising
threshold voltage, the MP8770C powers up. It
shuts off when the input voltage falls below the
UVLO falling threshold voltage. This is a nonlatch protection.
Soft Start
The MP8770C employs a soft start (SS)
mechanism to ensure smooth output ramping
during power-up. When the EN pin goes high, an
internal (6μA) current source charges up the SS
capacitor. The SS capacitor voltage takes over
VREF to the PWM comparator. The output voltage
smoothly ramps up with the SS voltage. Once
SS voltage (VSS) rises above VREF, it continues to
ramp up and VREF takes over. At this point, soft
start finishes and the device enters steady state
operation.
The SS capacitor value can be determined with
Equation (1):
Css (nF) 0.83
t ss (ms) Iss (uA)
VREF (V)
(1)
If the output capacitance is a large value, it is not
recommended to set the SS time too short. This
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
14
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
avoids accidentally reaching the current limit
during SS. An SS capacitor less than 4.7nF
should be avoided.
reference. Once UV is triggered, the MP8770C
enters hiccup mode to periodically restart the
part.
Power Good Indicator (PG)
The PG pin is the open drain of a MOSFET that
connects to VCC or some other voltage source
through a resistor (e.g. 100kΩ). The MOSFET
turns on with the application of an input voltage
so that the PG pin is pulled to GND before SS is
ready. After VFB reaches 90% of VREF, the PG pin
is pulled high after a 50μs delay. When the VFB
drops to 80% of VREF, the PG pin is pulled low.
During OCP, the device tries to recover from an
over-current fault with hiccup mode. This means
the chip disables the output power stage,
discharges the soft-start capacitor, then
automatically tries to soft start again.
When UVLO or OTP occurs, the PG pin is pulled
low immediately. If OC (over-current) occurs, the
PG pin is pulled low when VFB drops below 80%
of VREF after a 0.05ms delay. When OV occurs,
PG is pulled low when VFB rises above 120% of
VREF after a 0.05ms delay. If VFB falls back below
110% of VREF, PG is pulled high after a 0.05ms
delay.
If the input supply fails to power the MP8770C,
PG is clamped low, even though PG is tied to an
external DC source through a pull-up resistor.
Figure 3 shows the relationship between the PG
voltage and the pull-up current.
PG Clamped Voltage vs. Pull-Up Current
PG CLAMPED VOLTAGE (V)
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
PULL-UP CURRENT (mA)
4
5
Figure 3: PG Clamped Voltage vs. Pull-Up
Current
Over-Current Protection (OCP) and ShortCircuit Protection (SCP)
The MP8770C has valley limit control. The LSFET monitors the current flowing through it. The
HS-FET waits until the valley current limit
disappears to turn on again. Meanwhile, the
output voltage drops until VFB is below the undervoltage (UV) threshold, typically 50% below the
If the over-current condition still remains after
soft start ends, the device repeats this operation
cycle until the over-current conditions disappear
and the output rises back to regulation level.
OCP is a non-latch protection.
Pre-Bias Start-Up
The MP8770C has been designed for monotonic
start-up into pre-biased loads. If the output is
pre-biased to a certain voltage during start-up,
the BST voltage is refreshed and charged, and
the voltage on the soft-start capacitor is also
charged. If the BST voltage exceeds its rising
threshold voltage and the soft-start capacitor
voltage exceeds the sensed output voltage at the
FB pin, the part starts to work normally.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die temperature exceeds
150°C, it shuts down the whole chip. When the
temperature falls below its lower threshold
(typically 130°C), the chip is enabled again.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection, with a rising
threshold of 1.7V and a hysteresis of 150mV. VIN
regulates the bootstrap capacitor voltage
internally through D1, M1, R4, C4, LO, and CO
(see Figure 4). If VIN - VSW exceeds 3.3V, U2
regulates M1 to maintain a 3.3V BST voltage
across C4. It is recommended for the BST
resistor (R4) to be less than 4.7Ω.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
15
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
VIN
D1
3.3V
M1
R4
C4
U2
SW
VOUT
LO C
O
Figure 4: Internal Bootstrap Charger
Start-Up and Shutdown
If both VIN and EN exceed their respective
thresholds, the chip starts. The reference block
starts first, generating a stable reference voltage
and current, and then the internal regulator is
enabled. The regulator provides a stable supply
for the remaining circuits.
Three events can shut down the chip: EN low,
VIN low, and thermal shutdown. The shutdown
procedure starts by initially blocking the signaling
path to avoid any fault triggering, and then the
internal supply rail is pulled down.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
16
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
COMPONENT SELECTION
Setting the Output Voltage
The external resistor divider is used to set the
output voltage. First, choose a value for R2. R2
should be chosen reasonably, as a small R2
value leads to considerable quiescent current
loss and too large a value makes the FB noise
sensitive. It is recommended to choose a value
between 2kΩ and 100kΩ for R2. Typically, a
current less than 250μA through R2 offers a
good balance between system stability and no
load loss. R1 is then determined with Equation
(2):
R1
VOUT VREF
R2
VREF
(2)
Figure 5 shows the feedback circuit.
R1
CF
RT
FB
R2
Figure 5: Feedback Network
Table 1 lists the recommended resistor values
for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
VOUT
(V)
1.0
1.2
1.5
1.8
2.5
3.3
5
R1 (kΩ)
R2 (kΩ)
L (μH)
20
20
20
20
20
20
20
30
20
13
10
6.34
4.42
2.7
0.56
0.56
0.56
0.82
0.82
1
1.2
CF
(pF)
56
56
56
56
56
56
56
L
VOUT
V
(1 OUT )
fSW IL
VIN
RT
(kΩ)
1
1
1
1
1
1
1
Selecting the Inductor
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor will result in less ripple current and a
lower output ripple voltage. However, it also has
a larger physical footprint, higher series
(3)
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated with Equation
(4):
ILP IOUT
VOUT
MP8770C
resistance, and a lower saturation current. A
good rule for determining the inductance value is
to design the peak-to-peak ripple current in the
inductor to be between 30% and 40% of the
maximum output current. The peak inductor
current should also be below the maximum
switch current limit. The inductance value can be
calculated with Equation (3):
VOUT
V
(1 OUT )
2fSW L
VIN
(4)
Selecting the Input Capacitor
The step-down converter has a discontinuous
input current, and requires a capacitor to supply
the AC current to the converter while maintaining
the DC input voltage. Ceramic capacitors are
recommended for best performance, and should
be placed as close to the VIN pin as possible.
Capacitors with X5R and X7R ceramic
dielectrics are recommended because they are
fairly stable with temperature fluctuations.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated with Equation (5):
ICIN IOUT
VOUT
V
(1 OUT )
VIN
VIN
(5)
The worst-case condition occurs at VIN = 2VOUT,
calculated with Equation (6):
ICIN
IOUT
2
(6)
For simplification, choose the input capacitor
with an RMS current rating greater than half of
the maximum load current.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
17
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
The input capacitance value determines the
input voltage ripple of the converter. If there is an
input voltage ripple requirement in the system,
choose the input capacitor that meets the
specification.
The input voltage ripple can be estimated with
Equation (7):
VIN
IOUT
V
V
OUT (1 OUT )
fSW CIN VIN
VIN
(7)
The worst-case condition occurs at VIN = 2VOUT,
calculated with Equation (8):
VIN
I
1
OUT
4 fSW CIN
(8)
Selecting the Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output
voltage ripple can be estimated with Equation (9):
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (9)
fSW L
VIN
8 fSW COUT
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The output voltage ripple is mainly
caused by the capacitance. For simplification,
the output voltage ripple can be estimated with
Equation (10):
VOUT
VOUT
V
(1 OUT )
8 fSW 2 L COUT
VIN
(10)
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be estimated with Equation (11):
VOUT
VOUT
V
(1 OUT ) RESR (11)
fSW L
VIN
Besides considering the output ripple, a larger
output capacitor also can get better load
transient response. However, maximum output
capacitor limitation should be also considered in
design application. If the output capacitor value
is too high, the output voltage cannot reach the
design value during the soft-start time, and the
device will fail to regulate. The maximum output
capacitor value CO_MAX can be limited with
Equation (12):
CO _ MAX (ILIM _ AVG IOUT ) t ss / VOUT (12)
Where ILIM_AVG is the average start-up current
during soft-start period, and tss is the soft-start
time.
Design Example
A design example is provided below when the
ceramic capacitors are applied:
VIN
VOUT
IOUT
12V
1V
8A
For detailed application schematics, see the
Typical Application Circuits section on page 20.
For the typical performance and waveforms, see
the Typical Characteristics section on page 6.
For more device applications, refer to the related
evaluation board datasheet.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
18
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
PCB Layout Guidelines
Efficient layout is very important for proper
device function. Poor layout design can result in
poor line or load regulation and stability issues.
It is strongly recommended to use a 4-layer
board layout, with the two middle layers being
GND. For best performance, refer to Figure 6
and follow the guidelines below:
1. Place the high current paths (GND, IN, and
SW) very close to the device with short,
direct, and wide traces.
GND
VIN
SW
GND
2. Place the input capacitor as close as
possible to the IN and GND pins.
VOUT
Top Layer
3. Place the VCC decoupling capacitor close to
the device.
4. Connect AGND and PGND at the point of the
VCC capacitor’s ground connection.
5. Place the external feedback resistors next to
the FB pin.
VIN
GND
6. Keep the switching node (SW) short and
away from the feedback network.
Bottom Layer
Figure 6: Recommended PCB Layout
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
19
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
12V
C1
22µF
8
C1A
22µF
C1B
0.1µF
VIN
R6
100kΩ
EN
PG
7
R5
100kΩ
NC
FB
14
2
R3
0Ω
C3
0.1µF L1
0.56µH
MP8770C
SW
3
EN
PG
BST
16
1,15
C6
56pF
PGND
9,10,11,
12,13
SS
VOUT
1V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R2
30kΩ
R4
1kΩ
VCC
C4
1µF
AGND
VIN
6
C5
22nF
5
Figure 7: VIN = 12V, VOUT = 1V, IOUT = 8A (8)
12V
C1
22µF
8
C1A
22µF
C1B
0.1µF
VIN
R6
100kΩ
EN
PG
7
R5
100kΩ
NC
FB
14
2
R3
0Ω
C3
0.1µF L1
0.56µH
MP8770C
SW
3
EN
PG
BST
16
1,15
C6
56pF
PGND
9,10,11,
12,13
SS
VOUT
1.2V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R2
20kΩ
R4
1kΩ
VCC
C4
1µF
AGND
VIN
6
C5
22nF
5
Figure 8: VIN = 12V, VOUT = 1.2V, IOUT = 8A (8)
C1
22µF
8
C1A
22µF
C1B
0.1µF
7
R5
100kΩ
C4
1µF
BST
R6
100kΩ
3
EN
PG
VIN
14
2
R3
0Ω
C3
0.1µF L1
0.56µH
MP8770C
SW
EN
PG
NC
FB
16
1,15
C6
56pF
9,10,11,
12,13
SS
5
VOUT
1.5V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R4
1kΩ
VCC
AGND
12V
PGND
VIN
6
R2
13kΩ
C5
22nF
Figure 9: VIN = 12V, VOUT = 1.5V, IOUT = 8A (8)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
20
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
12V
C1
22µF
8
C1A
22µF
C1B
0.1µF
VIN
EN
PG
7
R5
100kΩ
NC
FB
14
2
R3
0Ω
C3
0.1µF L1
0.82µH
MP8770C
SW
3
EN
PG
BST
R6
100kΩ
16
1,15
C6
56pF
PGND
9,10,11,
12,13
SS
VOUT
1.8V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R2
10kΩ
R4
1kΩ
VCC
C4
1µF
AGND
VIN
6
C5
22nF
5
Figure 10: VIN = 12V, VOUT = 1.8V, IOUT = 8A (8)
12V
C1
22µF
8
C1A
22µF
C1B
0.1µF
VIN
EN
PG
7
R5
100kΩ
NC
FB
14
2
R3
0Ω
C3
0.1µF L1
0.82µH
MP8770C
SW
3
EN
PG
BST
R6
100kΩ
16
1,15
C6
56pF
PGND
9,10,11,
12,13
SS
VOUT
2.5V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R2
6.34kΩ
R4
1kΩ
VCC
C4
1µF
AGND
VIN
6
C5
22nF
5
Figure 11: VIN = 12V, VOUT = 2.5V, IOUT = 8A (8)
C1
22µF
8
C1A
22µF
C1B
0.1µF
3
EN
PG
7
R5
100kΩ
C4
1µF
VIN
BST
R6
100kΩ
14
2
R3
0Ω
C3
0.1µF L1
1µH
MP8770C
SW
EN
PG
NC
FB
16
1,15
C6
56pF
9,10,11,
12,13
SS
5
VOUT
3.3V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R4
1kΩ
VCC
AGND
12V
PGND
VIN
6
R2
4.42kΩ
C5
22nF
Figure 12: VIN = 12V, VOUT = 3.3V, IOUT = 8A (8)
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
21
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
C1
22µF
8
C1A
22µF
C1B
0.1µF
7
R5
100kΩ
C4
1µF
BST
R6
100kΩ
3
EN
PG
VIN
14
2
R3
0Ω
C3
0.1µF L1
1.2µH
MP8770C
SW
EN
PG
NC
FB
16
1,15
C6
56pF
9,10,11,
12,13
SS
5
VOUT
5V
R1
C2
C2A C2B
20kΩ 22µF 22µF 22µF
C2C
22µF
4
R4
1kΩ
VCC
AGND
12V
PGND
VIN
6
R2
2.7kΩ
C5
22nF
Figure 13: VIN = 12V, VOUT = 5V, IOUT = 8A (8)
Note:
8) When VIN is low, see the Selecting the Input Capacitor Section on page 17.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
22
MP8770C – 17V, 8A, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-16 (3mmx3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN
MILLIMETERS.
2) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
3) JEDEC REFERENCE IS MO-220.
4) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP8770C Rev. 1.0
www.MonolithicPower.com
9/10/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
23