MP8795
16V, 15A, Synchronous, Step-Down
Converter with Adjustable Current Limit,
Programmable Frequency
DESCRIPTION
FEATURES
The MP8795 is a fully integrated, highfrequency, synchronous, buck converter. It
offers a very compact solution that achieves up
to 15A of output current with excellent load and
line regulation over a wide input supply range.
The MP8795 operates at high efficiency over a
wide output current load range.
•
The MP8795 adopts an internally compensated
constant-on-time (COT) control mode that
provides fast transient response and eases loop
stabilization.
The operating frequency can be set to
600kHz, 800kHz, or 1000kHz easily with MODE
configuration, allowing the MP8795 frequency to
remain constant regardless of the input and
output voltages.
The output voltage start-up ramp is controlled by
an internal 1ms timer. It can be increased by
adding a capacitor on SS. An open-drain power
good (PGOOD) signal indicates if the output is
within its nominal voltage range. PGOOD is
clamped at around 0.7V with an external pull-up
voltage when the input supply fails to power the
MP8795.
Full protection features include over-current
protection (OCP), over-voltage protection (OVP),
under-voltage protection (UVP), and overtemperature protection (OTP).
The MP8795 requires a minimal number of
readily available, standard, external components
and is available in a QFN-21 (3mmx4mm)
package.
MP8795 Rev. 1.1
10/18/2022
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•
•
•
•
•
•
•
•
•
•
•
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Wide Input Voltage Range
o 2.7V to 16V with External 3.3V VCC
Bias
o 4V to 16V with Internal Bias or External
3.3V VCC Bias
Differential Output Voltage Remote Sense
Programmable Accurate Current Limit Level
15A Output Current
Low RDS(ON) Integrated Power MOSFETs
Selectable Pulse Skip or Forced CCM
Operation
Excellent Load Regulation
Output Voltage Discharge
PGOOD Active Clamped at Low Level
during Power Failure
Programmable Soft-Start Time from 1ms
Selectable Switching Frequency from
600kHz, 800kHz, and 1000kHz
Non-Latch OCP, UVP, UVLO, Thermal
Shutdown, and Latch-Off for OVP
Output Adjustable from 0.6V to 90%*VIN,
up to 5.5V Max
Available in a QFN-21 (3mmx4mm)
Package
APPLICATIONS
•
•
•
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Solid-State Drives (SSD)
Flat-Panel Televisions and Monitors
Set-Top Boxes
Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
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1
MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION
CBST
L1
VIN
BST
VIN
CIN1
CIN2
VOUT
SW
CIN3
U1
EN
EN
VOSENSE+
MP8795
Cff
COUT
PG
FB
RFB1
CVCC
RFB2
VOSENSE-
CSS1
RMODE
MP8795 Rev. 1.1
10/18/2022
RCS
CSS2
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number
MP8795GLE*
Package
QFN-21 (3mmx4mm)
Top Marking
See Below
MSL Rating
1
* For Tape & Reel, add suffix –Z (e.g. MP8795GLE–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
8795: Part number
LLL: Lot number
E: Package prefix
PACKAGE REFERENCE
TOP VIEW
21
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
11
9
10
QFN-21 (3mmx4mm)
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS
(1)
Supply voltage (VIN) .....................................18V
VSW (DC) ............................... -0.3V to VIN + 0.3V
VSW (25ns) (2) ................................... -5V to +25V
VBST......................................................VSW + 4V
VCC, EN ...................................................... 4.5V
VRGND ........................................................ ±0.3V
All other pins ............................... -0.3V to +4.3V
Junction temperature ............................... 170°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +170°C
Recommended Operating Conditions
(3)
Supply voltage (VIN) ........................... 4V to 16V
VIN(DC) - VSW(DC) (4)................... -0.3V to VIN + 0.3V
VSW(DC) (4) ............................... -0.3V to VIN + 0.3V
Output voltage (VOUT ) ..................... 0.6V to 5.5V
External VCC bias (VCC_EXT) ......... 3.12V to 3.6V
EN voltage (VEN) ........................................3.6V
Operating junction temp. (TJ). .. -40°C to +125°C
MP8795 Rev. 1.1
10/18/2022
Thermal Resistance
θJA
θJC
QFN-21 (4mmx3mm)
EV8795-LE-00A (5)...……….…20…...5.... °C/W
JESD51-7 (6)...……….………..44…..39.....°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) Measured using a differential oscilloscope probe.
3) The device is not guaranteed to function outside of its operating
conditions.
4) The voltage rating can be in the range of -5V to +25V for a
period of 25ns or less with a maximum repetition rate of
1000kHz when the input voltage is 16V.
5) Measured on EV8795-LE-00A (78mmx81mm), 4-layer PCB.
6) The value of θJA given in this table is only valid for comparison
with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD51-7,
and simulated on a specified JEDEC board. They do not
represent the performance obtained in an actual application.
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C (7), typical values are tested at T J = 25°C, unless otherwise noted.
Parameters
Supply Current
Supply current (shutdown)
Supply current (quiescent)
MOSFET
Symbol
Typ
Max
Units
VEN = 0V
VEN = 2V, VFB = 0.62V
0
650
10
850
μA
μA
HS switch on resistance
HSRDS-ON
VBST-SW = 3.3V
10
LS switch on resistance
LSRDS-ON
VCC = 3.3V
3
Switch leakage
SW LKG_HS
SW LKG_LS
VEN = 0V, VSW = 0V
VEN = 0V, VSW = 12V
0
0
10
30
μA
1.15
9
1.2
10
1.25
11
V
μA/A
480
600
720
kHz
680
800
920
kHz
850
1000
1150
kHz
50
180
ns
ns
Current Limit
Current limit threshold
ICS to IOUT ratio
Switching Frequency
Switching frequency(8)
ISD
IQ
VLIM
ICS/IOUT
f SW
Condition
IOUT ≥ 2A
MODE = GND, IOUT = 0A,
VOUT = 1V
MODE = 30.1kΩ, IOUT = 0A,
VOUT = 1V
MODE = 60.4 kΩ, IOUT = 0A,
VOUT = 1V
Minimum on time (8)
TON_MIN
Minimum off time (8)
TOFF_MIN
Over-Voltage and Under-Voltage Protection
OVP threshold
VOVP
UVP threshold
VUVP
Feedback Voltage and Soft Start
Feedback voltage
SS sourcing current
SS sinking current
Soft-start time
Error Amplifier
Error amplifier offset
Feedback current
MP8795 Rev. 1.1
10/18/2022
VREF
ISS_Source
ISS_Sink
tSS
VOS
IFB
TJ = 25°C
TJ = -40°C to +125°C
VSS = 0V
VSS = 1V
CSS = 1nF, TJ = +25°C
Min
m
113%
77%
116%
80%
119%
83%
VREF
VREF
594
591
600
600
42
12
1
606
609
1.25
mV
mV
μA
μA
ms
0
50
3
100
mV
nA
0.75
-3
VFB = VREF
m
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C (7), typical values are tested at T J = 25°C, unless otherwise noted.
Parameters
Enable and UVLO
Enable input rising threshold
Enable hysteresis
Enable input current
Soft shutdown discharge FET
VIN UVLO
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
VCC Regulator
VCC under-voltage lockout
threshold rising
VCC under-voltage lockout
threshold hysteresis
VCC regulator
VCC load regulation
Power Good
Power good high threshold
Power good low threshold
Power good low to high delay
Power good sink current
capability
Power good leakage current
Power good low-level output
voltage
Symbol
Condition
VIHEN
VEN-HYS
IEN
Min
Typ
Max
Units
1.1
1.2
200
1.3
V
mV
VEN = 2V
RON_DISCH
VINVth_Rise
μA
0
2.1
80
150
2.4
2.7
VCC = 3.3V
V
VINvth_HYS
0.55
VCCVth_Rise
2.65
VCCvth_HYS
IPG_LEAK
VOL_100
VOL_10
2.95
FB from low to high
FB from low to high
FB from high to low
TJ = 25°C
V
3.00
0.5
3.12
V
%
89.5%
113%
77%
0.63
92.5%
116%
80%
0.9
95.5%
119%
83%
1.17
VREF
VREF
VREF
ms
0.4
V
3
µA
650
850
mV
800
1000
mV
IPG = 10mA
VPG = 3.3V
VIN = 0V, pull PGOOD up to
3.3V through a 100kΩ
resistor
VIN = 0V, pull PGOOD up to
3.3V through a 10kΩ resistor
V
2.88
Icc = 25mA
VPG
2.8
0.3
VCC
PGVth_Hi_Rise
PGVth_Lo_Rise
PGVth_Lo_Fall
PGTd
Ω
Thermal Protection
Thermal shutdown (7)
Thermal shutdown hysteresis (7)
TSD
TSD_HYS
160
30
°C
°C
Notes:
7) Derived by over-temperature correlation. Not tested in production.
8) Derived by sample characterization. Not tested in production.
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, TA = 25°C, VOUT = 1V, fSW = 800kHz, unless otherwise noted.
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, TA = 25°C, VOUT = 1V, fSW = 800kHz, unless otherwise noted.
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, TA = 25°C, VOUT = 1V, fSW = 800kHz, unless otherwise noted.
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
PIN FUNCTIONS
QFN-21
PIN #
Name
1
BST
2
3
AGND
CS
4
MODE
Description
Bootstrap. Connect a capacitor between SW and BS to form a floating supply across
the high-side switch driver.
Analog ground. Select AGND as the control circuit reference point.
Current limit. Connect a resistor to ground to set the current limit trip point.
Operation mode selection. Program MODE to select CCM, pulse skip mode, and
the operating switching frequency. See Table 1 for additional details.
Soft start input. The soft start time could be set through using different soft start
5
SS
6
RGND
7
FB
8
EN
9
PGOOD
10, 21
VIN
11, 12, 13,
14, 15, 16,
17, 18
PGND
19
VCC
20
SW
MP8795 Rev. 1.1
10/18/2022
capacitance. The total capacitance of CSS1 and CSS2 determines the soft-start time
(tSS). See Equation 2 for additional details. Minimum 1nF of both two SS capacitors
(CSS1 from SS to RGND, CSS2 from SS to AGND) are always required respectively.
Place SS capacitors as close to it as possible. X7R or X5R grade dielectric ceramic
capacitors are recommended for their stable temperature characteristics.
Differential remote sense negative input. Connect RGND to the negative side of
the voltage sense point directly. Short RGND to GND if the remote sense is not used.
Feedback (differential remote sense positive input). An external resistor divider
from the output to RGND tapped to FB sets the output voltage. It is recommended to
place the resistor divider as close to FB as possible. Vias should be avoided on the
FB traces.
Enable. EN is an input signal that turns the regulator on or off. Drive EN high to turn
on the regulator; drive EN low to turn off the regulator. Connect EN to VIN through a
pull-up resistor or a resistive voltage divider for automatic start-up. Do not float EN.
Power good output. PGOOD is an open-drain signal. A pull-up resistor connected
to a DC voltage is required to indicate a logic high signal if the output voltage is within
regulation. There is a delay of about 1ms between the time FB ≥ 92.5% and PGOOD
pulling high.
Input voltage. VIN supplies power for the internal MOSFET and regulator. Input
capacitors are needed to decouple the input rail. Use wide PCB traces to make the
connection.
System ground. PGND is the reference ground of the regulated output voltage.
Therefore, care must be taken during PCB layout. Use wide PCB traces to make the
connection.
Internal 3V LDO output. The driver and control circuits are powered from the VCC
voltage. Decouple VCC with a ceramic capacitor at least 1µF placed as close to it as
possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven
up to VIN by the high-side switch during the on-time of the PWM duty cycle. The
inductor current drives SW low during the off-time. Use wide PCB traces to make the
connection.
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
VIN
MODE
MODE
Select
3 V LDO
VCC
BST
REG
EN
Reference
System
Monitor
HS
Driver
xS
OV_TH UV_TH
xR
RGND
FB
Q
HSG
LSG
SS
Error
Amplifier
BST
Off
Timer
Logic
Control
SW
On
Timer
PWM
Comparator
HSG
LSG
LS
Driver
Ramp
ZCD
Valley
Current
xLIM Limit &
ZCD
PGOOD
Comparator
AGND
OV_TH
OV Detect
Comparator
PGOOD
PGND
CS
UV_TH
FAULT
UV Detect
Comparator
Figure 1: Functional Block Diagram
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
OPERATION
COT Control
The MP8795 employs a constant-on-time (COT)
control to achieve a fast load transient response.
Figure 2 shows the details of the control stage of
the MP8795.
The operational amplifier (AMP) corrects any
error voltage between FB and VREF. The
MP8795 can use AMP to provide excellent load
regulation over the entire load range in either
forced continuous conduction mode (CCM) or
pulse skip mode.
The dedicated RGND pin helps provide the
feature of the differential output voltage remote
sense. The pair of the remote sense trace should
be kept in low impedance to achieve the best
performance.
The MP8795 has an internal RAMP
compensation to support a low ESR MLCC
output capacitor solution. The adaptive internal
RAMP is optimized so that the MP8795 is stable
in the entire operating input and output voltage
ranges with a proper design of the output L/C
filter.
FET) turns on when the HS-FET is in its off state
to minimize conduction loss. A dead short occurs
between VIN and PGND if both the HS-FET and
the LS-FET are turned on at the same time. This
is called a shoot-through. To avoid a shootthrough, a dead time (DT) is generated internally
between the HS-FET off and the LS-FET on
period or the LS-FET off and the HS-FET on
period.
FB
REF
RAMP
COMP
PWM
HS-FET
Driver
TON
LS-FET
Driver
IO
IL
VIN
PWM
Comparator
FB
RGND
AMP
VREF
COMP
+Σ
+
Figure 3: Heavy-Load Operation (PWM)
HSFET
ON
Timer
PWM
Adaptive
RAMP
SW
L
Vsens+
LSFET
Vsens-
COUT
PGND
Figure 2: COT Control
PWM Operation
Figure 3 shows how the PWM signal is
generated. AMP corrects any error between FB
and REF and generates a fairly smooth DC
voltage (COMP). The internal RAMP is
superimposed onto COMP, which is compared
with the FB signal. Whenever FB drops below
the superimposed COMP, the integrated highside MOSFET (HS-FET) is turned on. The HSFET remains on for a fixed turn-on time. The
fixed on time is determined by the input voltage,
output voltage, and selected switching frequency.
After the on period elapses, the HS-FET turns
off. It turns on again when FB drops below the
superimposed COMP. By repeating this
operation, the MP8795 regulates the output
voltage. The integrated low-side MOSFET (LS-
MP8795 Rev. 1.1
10/18/2022
CCM Operation
Continuous conduction mode (CCM) occurs
when the output current is high, and the inductor
current is always above zero amps (see Figure
3). The MP8795 can also be configured to
operate in forced CCM operation when the
output current is low (see the Mode Selection
section on page 14 for details).
In CCM operation, the switching frequency is
fairly constant (PWM mode), hence the output
ripple remains almost constant throughout the
entire load range.
Pulse Skip Operation
In light-load condition, the MP8795 can be
configured to work in pulse skip mode to
optimize efficiency. When the load decreases,
the inductor current decreases as well. Once the
inductor current reaches zero, the MP8795
transitions from CCM to pulse skip mode if the
MP8795 is configured in this way (see the Mode
Selection section on page 14 for details).
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
Figure 4 shows pulse skip mode operation at
light-load condition. When FB drops below the
superimposed COMP, the HS-FET turns on for a
fixed interval. When the HS-FET turns off, the
LS-FET turns on until the inductor current
reaches zero. In pulse skip mode operation, FB
does not reach superimposed COMP when the
inductor current approaches zero. The LS-FET
driver turns into tri-state (high-Z) when the
inductor current reaches zero. A current
modulator takes over the control of the LS-FET
and limits the inductor current to less than
1mA. Therefore, the output capacitors discharge
slowly to PGND through the LS-FET. At lightload condition, the HS-FET is not turned on as
frequently in pulse skip mode as it is in forced
CCM. As a result, the efficiency in pulse skip
mode is improved greatly compared to that in
forced CCM operation.
REF
FB
RAMP
COMP
PWM
TON
HS-FET
Driver
LS-FET
Driver
IO
IL
Figure 4: Pulse Skip in Light Load
As the output current increases from light load,
the time period the current modulator regulates
in becomes shorter. The HS-FET is turned on
more frequently, and the switching frequency
increases accordingly. The output current
reaches critical levels when the current
modulator time is zero. The critical level of the
output current can be determined with Equation
(1):
IOUT =
( VIN − VOUT ) VOUT
2 L FSW VIN
The MP8795 enters PWM mode once the output
current exceeds the critical level. Afterward, the
switching frequency remains fairly constant over
the output current range.
The MP8795 can be configured to operate in
forced CCM, even in light-load condition (see
Table 1).
Mode Selection
The MP8795 provides both forced CCM
operation and pulse skip mode operation in lightload condition. The MP8795 has three options
for switching frequency selection. Selecting the
operation mode under light-load condition and
the switching frequency is done by choosing the
resistance value of the resistor connected
between MODE and AGND or VCC (see Table
1).
Table 1: MODE Selection
Light-Load
Switching
MODE
Mode
Frequency
VCC
Pulse skip
600kHz
243kΩ (±20%)
Pulse skip
800kHz
to GND
121kΩ (±20%)
Pulse skip
1000kHz
to GND
GND
Forced CCM
600kHz
30.1kΩ (±20%)
Forced CCM
800kHz
to GND
60.4kΩ (±20%)
Forced CCM
1000kHz
to GND
Soft Start (SS)
The MP8795 employs soft start (SS) to ensure a
smooth output during start-up. If EN goes high,
then an internal current source starts to charge
the soft-start capacitors. The SS voltage (VSS)
overrides the REF voltage (VREF) to the PWM
comparator so that the output voltage smoothly
ramps up as VSS rises. Once VSS reaches VREF,
VREF takes over the PWM comparator. Once SS
is complete, the part enters steady-state
operation.
The soft-start capacitance
calculated with Equation (2):
(CSS)
(1)
can
be
(2)
Where FSW is the switching frequency.
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
Where CSS is the total capacitance of CSS1 and
CSS2. Both CSS1 and CSS2 are required to ensure
VREF is stable during SS.
The MP8795 has an internal minimum soft-start
time (tSS) (1ms). CSS1 and CSS2 should each be
≥1nF to achieve the minimum tSS.
For a longer tSS, see Equation 2 on page 13. For
simplification, choose CSS2 to be 22nF, and
adjust CSS1 to set the target VREF. For example,
with a 22nF CSS2 and 100nF CSS1, tSS should be
2ms.
Pre-Bias Start-Up
The MP8795 is designed for monotonic start-up
into pre-biased loads. If the output is pre-biased
to a certain voltage during start-up, the IC
disables switching for both the HS-FET and LSFET until the voltage on the SS capacitor
exceeds the sensed output voltage at FB. Before
the SS voltage reaches the pre-biased FB level,
if the BST voltage (from BST to SW) is lower than
2.3V, the LS-FET is turned on to allow the BST
voltage to be charged through VCC. The LS-FET
is turned on for very narrow pulses, so the drop
in the pre-biased level is negligible.
Output Voltage Discharge
When the MP8795 is disabled through EN,
output voltage discharge mode is enabled. This
causes both the HS-FET and the LS-FET to latch
off. A discharge FET connected between SW
and PGND is turned on to discharge the output
voltage. The typical switch on resistance of this
FET is about 80Ω. Once the FB voltage drops
below 20% of VREF, the discharge FET is turned
off.
Current Sense and Over-Current Protection
(OCP)
The MP8795 features an on-die current sense
and a programmable positive current limit
threshold.
The current limit is active when the MP8795 is
enabled. During the LS-FET on state, the SW
current (inductor current) is sensed and mirrored
to CS with the ratio of GCS. By using a resistor
(RCS) from CS to AGND, the VCS voltage is
proportional to the SW current cycle-by-cycle.
The HS-FET is only allowed to turn on when VCS
is below the internal OCP voltage threshold
(VOCP) during the LS-FET on state to limit the SW
valley current cycle-by-cycle.
MP8795 Rev. 1.1
10/18/2022
Calculate the current limit threshold setting from
RCS with Equation (3):
RCS () =
VOCP
(VIN − VO ) VO
1
GCS (ILIM −
)
VIN
2 L fs
(3)
Where VOCP = 1.2V, GCS = 10µA/A, and ILIM is the
desired output current limit (A).
The OCP hiccup is active 3ms after the MP8795
is enabled. Once OCP hiccup is active, if the
MP8795 detects the over-current condition for 31
consecutive cycles, or if FB drops below the
under-voltage protection (UVP) threshold, it
enters hiccup mode. In hiccup mode, the
MP8795 latches off the HS-FET immediately,
and latches off the LS-FET after ZCD is detected.
Meanwhile, the SS capacitor is also discharged.
After about 11ms, the MP8795 attempts to soft
start automatically. If the over-current condition
still remains after 3ms of running, the MP8795
repeats this operation cycle until the over-current
condition disappears, and the output voltage
rises back to the regulation level smoothly.
Output Sinking Mode (OSM)
The MP8795 employs output sinking mode
(OSM) to regulate the output voltage to the
targeted value. When the FB voltage is higher
than 104% of VREF but is below the OVP
threshold, OSM is triggered. During OSM
operation, the LS-FET remains on until it
reaches the -7.5A current limit. The LS-FET is
then turned off momentarily for 200ns before
turning on again. The MP8795 repeats this
operation until FB drops below 102% of VREF.
The MP8795 exits OSM after 15 consecutive
cycles of forced CCM.
Over-Voltage Protection (OVP)
The MP8795 monitors the output voltage by
connecting FB to the tap of the output voltage
feedback resistor divider to detect an overvoltage condition. This provides latch-off OVP
mode.
If the FB voltage exceeds 116% of VREF, the
MP8795 enters latch-off OVP mode. The HSFET latches off and PGOOD latches low until
VCC or EN is recycled (turned off and turned on
again). Meanwhile, the LS-FET remains on until
it reaches the low-side negative current limit
(NOCP). The LS-FET is then turned off
momentarily for 200ns before turning on again.
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
The MP8795 repeats this operation to attempt to
bring down the output voltage. When the FB
voltage drops below 50% of VREF, the LS-FET is
turned off for pulse skip mode and continues
turning on for forced CCM operation. If FB rises
higher than 116% VREF again, the LS-FET turns
on again with NOCP until FB drops back below
50% of VREF. The MP8795 needs EN or VIN to
recycle to clear the OVP fault.
The OVP function is enabled after SS reaches
600mV.
Over-Temperature Protection (OTP)
The MP8795 has over-temperature protection
(OTP). The IC monitors the junction temperature
internally. If the junction temperature exceeds
the threshold value (typically 160°C), the
converter shuts off and discharges the SS
capacitors. This is a non-latch protection. There
is a hysteresis of about 30°C. Once the junction
temperature drops to about 130°C, a soft start is
initiated. The OTP function is effective once the
MP8795 is enabled.
Output Voltage Setting and Remote Output
Voltage Sensing
First, choose a value for R1. Then R2 can be
determined with Equation (4):
VREF
R2 (k) =
R1(k)
VO − VREF
(4)
To optimize the load transient response, a feedforward capacitor (CFF) is recommended to be
placed in parallel with R1. R1 and CFF add an
extra zero to the system, which improves loop
response. R1 and CFF are selected so that the
zero formed by R1 and CFF is located around
20kHz~60kHz. Calculate this zero with Equation
(5):
fZ =
1
2 R1 CFF
(5)
Power Good (PGOOD)
The MP8795 has a power good (PGOOD)
output. PGOOD is the open-drain of a MOSFET.
Connect PGOOD to VCC or another external
voltage source less than 3.6V through a pull-up
resistor (typically 10kΩ). After applying the input
voltage, the MOSFET turns on, so PGOOD is
MP8795 Rev. 1.1
10/18/2022
pulled to GND before SS is ready. After the FB
voltage reaches 92.5% of VREF, PGOOD is
pulled high after a 0.8ms delay.
When the FB voltage drops to 80% of VREF, or
exceeds 116% of the nominal VREF PGOOD is
latched low. PGOOD can only be pulled high
again after a new SS.
If the input supply fails to power the MP8795,
PGOOD is clamped low, even though PGOOD is
tied to an external DC source through a pull-up
resistor. The relationship between the PGOOD
voltage and the pull-up current is shown in
Figure 5.
Figure 5: PGOOD Clamped Voltage vs. Pull-Up
Current
Enable (EN) Configuration
The MP8795 turns on when EN goes high; the
MP8795 turns off when EN goes low. EN cannot
be left floating for proper operation. EN can be
driven by an analog or digital control logic signal
to enable or disable the MP8795.
The MP8795 provides accurate EN thresholds,
so a resistor divider from VIN to AGND can be
used to program the input voltage, at which the
MP8795 is enabled. This is highly recommended
for applications where there is no dedicated EN
control logic signal to avoid possible UVLO
bouncing during power-up and power-down. The
resistor divider values can be determined with
Equation (6):
VIN _ START ( V ) = VIH EN
R UP + R DOWN
R DOWN
(6)
Where VIHEN is 1.22V, typically.
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
RUP and RDOWN should be chosen so that VEN
does not exceed 3.6V when VIN reaches the
maximum value.
EN can also be connected to VIN directly
through a pull-up resistor (RUP). RUP should be
chosen so that the maximum current going to
EN is 50μA. RUP can be calculated with
Equation (7):
R UP (KΩ ) =
VIN MAX (V)
0.05(mA)
(7)
External VCC Bias
The MP8795 has an internal 3V LDO to power
the driver and control circuits. Decouple VCC pin
with a ceramic capacitor at least 1µF, and place
as close to it as possible.
An external bias voltage between 3.16V to 3.6V
can be applied for lower input down to 3.3V
application. This can also improve the efficiency
of the converter because the external bias
overrides internal VCC to power on the driver
and control circuits.
It’s important to apply the external bias to VCC
pin before VIN UVLO rising threshold or EN
rising threshold comes to avoid the external bias
sinking current from VCC pin.
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
APPLICATION INFORMATION
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply AC current to the step-down converter
while maintaining the DC input voltage. Use
ceramic capacitors for the best performance.
During layout, place the input capacitors as close
to VIN as possible.
The capacitance can vary significantly with
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over a wide temperature
range and offer very low ESR.
The capacitors must have a ripple current rating
that exceeds the converter’s maximum input
ripple current. Estimate the input ripple current
with Equation (8):
ICIN = IOUT
VOUT
V
(1 − OUT )
VIN
VIN
(8)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (9):
ICIN =
IOUT
2
(9)
For simplification, choose an input capacitor with
an RMS current rating that exceeds half the
maximum load current. The input capacitor value
determines the converter input voltage ripple. If
there is an input voltage ripple requirement in the
system, select an input capacitor that meets the
specification.
Estimate the input voltage ripple with Equation
(10):
IOUT
V
V
VIN =
OUT (1 − OUT )
FSW CIN
VIN
VIN
(10)
The worst-case condition occurs at VIN = 2VOUT,
where:
VIN =
MP8795 Rev. 1.1
10/18/2022
IOUT
1
4 FSW CIN
(11)
Output Capacitor
The output capacitor maintains the DC output
voltage. Use POSCAP or ceramic capacitors.
Estimate the output voltage ripple with Equation
(12):
VOUT =
VOUT
V
1
(1 − OUT ) (RESR +
)
FSW L
VIN
8 FSW COUT
(12)
When using ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The capacitance also dominates the
output voltage ripple. For simplification, estimate
the output voltage ripple with Equation (13):
VOUT =
VOUT
8 FSW L COUT
2
(1 −
VOUT
) (13)
VIN
For simplification, the output ripple can be
approximated with Equation (14):
VOUT =
VOUT
V
(1 − OUT ) RESR
FSW L
VIN
(14)
Inductor
The inductor supplies a constant current to the
output load while being driven by the switching
input voltage. A larger value inductor results in
less ripple current and lower output ripple
voltage, but also has a larger physical size, a
higher series resistance, and a lower saturation
current. Design for a peak inductor current that
is below the maximum switch current limit.
Calculate the inductance value with Equation
(15):
L=
VOUT
V
(1 − OUT )
FSW IL
VIN
(15)
Where ∆IL is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated with Equation
(16):
ILP = IOUT +
VOUT
V
(1 − OUT )
2 FSW L
VIN
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(16)
17
MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For best performance, refer to Figure
6 and follow the guidelines below.
5. Place the VCC decoupling capacitor close to
the device.
1. Place the input MLCC capacitors as close to
VIN and PGND as possible.
2. Place the major MLCC capacitors on the
same layer as the MP8795.
7. Place the BST capacitor as close to BST and
SW as possible with 20 mil or wider traces to
route the path. It is recommended to use a
bootstrap capacitor 0.1µF to 1µF.
3. Maximize the VIN and PGND copper plane
to minimize the parasitic impedance.
8. Place the REF capacitor close to SS to
RGND.
4. Place as many PGND vias as possible as
close to PGND as possible to minimize both
parasitic impedance and thermal resistance.
9. Place via at least 10mm away from the
positive side of the first input decoupling
capacitor close to the IC if it must be placed
on the PGOOD pad.
6. Connect AGND and PGND at the point of the
VCC capacitor's ground connection.
VOSENSE +
VOSENSE RFB1
CFF
CSS2 V O
AGND
CSS1
RFB2
SS
MODE
CS
AGND
BST
5
4
3
2
1
7
6
FB
8
RGND
EN
PGOOD 9
PGND
VOUT
CIN3
VIN
21
VIN
20
SW
10
VIN
CIN2
CIN1
SW
18
PGND
PGND
PGND
VCC
17
19
16
PGND
PGND
PGND
13
PGND
PGND
15
12
14
11
PGND
VIN
CVCC
Figure 6: Recommended PCB Layout
MP8795 Rev. 1.1
10/18/2022
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUIT
10
VIN
12V
C1
10µF
21
C1A
10µF
C1B
10µF
C1C C1D
1µF 1µF
VIN
BST
CBST
1µF
SW
8
EN
R6
100kΩ
PG
R5
10kΩ
U1
FB
MP8795
9
19
CVCC
1µF
PG
RGND
VCC
SS
R9
121kΩ
R8
60.4kΩ
R7
30.1kΩ
11,12,13,14,
15,16,17,18
PGND
Jumper
R10
243kΩ
AGND
MODE
L1
0.4µH
1V15A
20
R1
3.4kΩ
7
R2
4.99kΩ
CS
4
RBST
0Ω
VIN
R4
499kΩ
EN
1
C2
C2A C2B C2C C2D
47µF 47µF 47µF 47µF 47µF
C2E
47µF
CFB
1nF
6
5
CREF
100nF
3
C1
RCS
22nF
6.8kΩ
2
Figure 7: VIN = 12V, VOUT = 1V, IOUT = 15A
MP8795 Rev. 1.1
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-21 (3mmx4mm)
PIN 1 ID
0.15 X 45° TYP
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.15 X 45°
NOTE:
1) LAND PATTERN OF PIN1,9,10,11,19,20 AND
21 HAVE THE SAME WIDTH.
2) ALL DIMENSIONS ARE IN MILLIMETERS.
3) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
4) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
5) JEDEC REFERENCE IS MO-220.
6) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP8795 Rev. 1.1
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
CARRIER INFORMATION
Part Number
Package
Description
Quantity/
Reel
Quantity/
Tube
Reel
Diameter
Carrier
Tape
Width
Carrier
Tape
Pitch
MP8795GLE-Z
QFN-21
(3mmx4mm)
5000
N/A
13in
12mm
8mm
MP8795 Rev. 1.1
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MP8795 – 16V, 15A, SYNCHRONOUS, STEP-DOWN CONVERTER
REVISION HISTORY
Revision #
Revision Date
1.01
9/8/2017
1.1
10/18/2022
Description
Initial Release
Removed “Voltage Tracking” from the header
Updated the Top Marking; added the MSL Rating; updated Pin
5 from the TRK/REF pin to the SS pin in the Package Information
section
Removed “VSW (25ns) (2)…-3V to +25V” and updated VRGND in
the Absolute Maximum Ratings section; updated the Thermal
Resistance section; updated Note 5; added Note 6
Updated the supply current (shutdown) symbol to “ISD”; updated
the supply current (quiescent) symbol to “IQ”; updated the
feedback current condition to “VFB = VREF”; removed “VFB = 0.5V”
from the minimum on time and minimum off time conditions
Updated the conditions for the Electrical Characteristics section
Updated Note 7 and Note 8
Updated the conditions for the Typical Performance
Characteristics section
Updated the SS description in the Pin Functions section
Updated the section title to “Functional Block Diagram”; added
“AGND” to Figure 1
Updated the Soft Start (SS) section
Added the External VCC Bias section
Updated the Inductor section
Added Figure 7
Added the Carrier Information section
Updated the footer
Formatting updates
Pages
Updated
1
3
4
5
5–6
6
7–9
10
11
13–14
16
17
19
21
22
All
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP8795 Rev. 1.1
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