MP8867
High-Efficiency, 8A, 17V, Synchronous
Step-Down Converter with I2C Interface
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP8867 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with an I2C control interface. It achieves an 8A
output current with excellent load and line
regulation over a wide input supply range.
The reference voltage level is controlled by the
I2C serial interface with an adjustable reference
voltage ranging from 0.6V to 1.87V in 10mV
steps. The voltage scaling slew rate, the
switching frequency, enable/sync, and power
save mode are all selectable through the I2C
interface.
Current-mode operation provides a fast
transient response and eases loop stabilization.
EN/SYNC
supports
external
clock
synchronization, and an open-drain power good
indicates when the output voltage is in the
nominal range. Full protection features include
over-voltage protection (OVP), hiccup overcurrent protection (OCP), and thermal
shutdown.
The MP8867 requires a minimal number of
readily
available,
standard,
external
components and is available in a QFN-14
(3x4mm) package.
Wide 4.5V to 17V Operating Input Range
1% Internal Reference Accuracy
I2C Programmable Reference Output
Voltage
Reference Voltage Range from 0.6V to
1.87V in 10mV Steps with Slew Rate
Control
I2C Selectable Switching Frequency
200kHz to 2MHz Synchronized External
Clock
OTP and OCP Hiccup Indication via I2C
Selectable PSM and FS through I2C
Programmable Soft-Start Time
Open-Drain Power Good Indicator
Small 3x4mm QFN-14 Package
APPLICATIONS
FPGA-Based Systems
ASIC Supplies
Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology”
are registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
100
90
80
70
60
50
40
30
0.01
MP8867 Rev.1.01
2/21/2017
0.10
1.00
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10.00
1
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
MP8867GLE
Package
QFN-14 (3mmx4mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8867GLE–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
8867: First four digits of the part number
LLL: Lot number
PACKAGE REFERENCE
QFN-14 (3mmx4mm)
MP8867 Rev.1.01
2/21/2017
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2
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
VIN …………………………….. ........ -0.3V to 19V
VSW…………………………………
-0.3V (-6V for 2V
0
0.4
0
0.4
VBus < 2V
0
0.2
VBus
0
0.2
VBus
V
-
3
-
3
mA
-
50
-
50
Ω
Condition
Units
V
V
V
Transfer gate on resistance for
currents between SDA and
SCAH, or SCL and SCLH
RonL
VOL level, IOL = 3mA
Transfer gate on resistance
between SDA and SCAH, or
SCL and SCLH
RonH
Both signals (SDA and SDAH,
or SCL and SCLH) at VBus level
50
-
50
-
kΩ
Pull-up current of the SCLH
current source
Ics
SCLH output levels between
0.3VBus and 0.7VBus
2
6
2
6
mA
Capacitive load from 10pF to
100pF
10
40
ns
Capacitive load of 400pF
20
80
ns
Capacitive load from 10pF to
100pF
10
40
ns
Rise time of the SCLH or SCL
signal
Fall time of the SCLH or SCL
signal
Rise time of SDAH signal
Fall time of SDAH signal
Pulse width of spikes that must
be suppressed by the input filter
trCL
tfCL
trDA
tfDA
Output rise time (current source
enabled) with an external pullup current source of 3mA
Output fall time (current source
enabled) with an external pullup current source of 3mA
Capacitive load of 400pF
20
80
20
250
ns
Capacitive load from 10pF to
100pF
10
80
-
-
ns
Capacitive load of 400pF
20
160
20
250
ns
Capacitive load from 10pF to
100pF
10
80
-
-
ns
Capacitive load of 400pF
20
160
20
250
ns
0
10
0
50
ns
-
10
-10
+10
µA
-
10
-
10
pF
tSP
Input current each I/O
Ii
Capacitance for each I/O
Ci
Input voltage between 0.1VBus
and 0.9VBus
NOTE:
VBus is the I2C bus voltage, 1.8V to 5.0V range, 3.3V typically.
MP8867 Rev.1.01
2/21/2017
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6
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
I2C Port Signal Characteristics
Parameter
Symbol Condition
SCLH
and
SCL
clock
frequency
Set-up time for a repeated
start condition
Hold time for a repeated start
condition
Low period of the SCL clock
High period of the SCL clock
Data set-up time
Data hold time
Cb = 100pF
Min
Max
Cb = 400pF
Min
Max
Units
fSCHL
0
3.4
0
0.4
MHz
TSU;STA
160
-
600
-
ns
THD;STA
160
-
600
-
ns
tLOW
tHIGH
TSU:DAT
THD;DAT
160
60
10
0
70
1300
600
100
0
-
ns
ns
ns
ns
Rise time of SCLH signal
trCL
10
40
20*0.1Cb
300
ns
Rise time of SCLH signal after
a repeated start condition and
after an acknowledge bit
tfCL1
10
80
20*0.1Cb
300
ns
Fall time of SCLH signal
TfCL
10
40
20*0.1Cb
300
ns
Rise time of SDAH signal
tfDA
10
80
20*0.1Cb
300
ns
Fall time of SDAH signal
Set-up time for stop condition
Bus free time between a stop
and start condition
Data valid time
Data valid acknowledge time
TfDA
TSU;STO
10
160
80
-
20*0.1Cb
600
300
-
ns
ns
TBUF
160
-
1300
-
ns
TVD;DAT
TVD;ACK
Capacitive load for each bus
line
-
16
160
100
-
90
900
400
ns
ns
pF
Cb
-
400
-
400
pF
Noise margin at the low level
Ci
-
0.1VBus
0.1VBus
-
V
Noise margin at the high level
VnH
-
0.2VBus
0.2VBus
-
V
SDAH and SCLH line
SDAH + SDA line
and SCLH + SCL line
For each connected
device
For each connected
device
NOTE:
VBus is the I2C bus voltage, 1.8V to 5.0V range, 3.3V typically,
MP8867 Rev.1.01
2/21/2017
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7
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted.
700
650
600
550
500
450
400
350
300
4.5
6 7.5 9 10.5 12 13.5 15 16.5
15
14
13
12
11
10
9
8
7
6
5
4
4.5 6 7.5 9 10.5 12 13.5 15 16.5
1.6
618
1.55
614
1.5
610
1.35
1.3
1.25
1.2
-40 -20
0
20 40 60 80 100 120125
4.2
4.15
4.1
4.05
4
-40 -20 0
520
500
598
480
594
460
590
440
586
420
582
-40 -20 0
20 40 60 80 100 120125
20 40 60 80 100 120125
400
-40 -20 0
20 40 60 80 100 120125
14
16
13.5
15
13
14
12.5
13
12
12
11.5
11
11
10.5
10
10
9
8
10
4.3
4.25
540
602
1.4
4.35
560
606
1.45
4.4
9.5
20
MP8867 Rev.1.01
2/21/2017
30
40
50
60
70
9
-40 -20 0
20 40 60 80 100 120
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8
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted.
100
100
90
90
80
80
70
70
60
60
50
50
40
40
40
35
30
25
20
30
0.01
0.10
1.00
10.00
30
0.01
15
10
5
0.10
1.00
10.00
0
0
1
2
3
4
5
6
7
8
9
0.9
1.00
60
0.7
0.75
48
180
144
0.5
0.50
36
108
72
0.3
0.25 No Load
24
12
0.1
0.00
36
0
-0.1
-0.25
-0.3
-0.50
-0.5
-0.75
-0.7
-1.00
4 5 6 7 8 9 10 1112 13 1415 1617
0
1
2
MP8867 Rev.1.01
2/21/2017
3
4
5
6
7
8
8A Load
0
5A Load
-12
-36
-24
-72
-36
-108
-48
-144
-180
1000000
-60
1000
10000
100000
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9
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board in the Design Example section.
VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted.
VOUT
500mV/div.
VOUT
500mV/div.
VPG
5V/div.
VPG
5V/div.
VSW
10V/div.
VSW
10V/div.
IL
10A/div.
IL
10A/div.
VOUT
500mV/div.
VEN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
Start-Up through Enable
Shutdown through Enable
Shutdown through Enable
IOUT = 8A
IOUT = 0A
IOUT = 8A
VOUT
500mV/div.
VEN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
10A/div.
VOUT
500mV/div.
VEN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
VOUT
500mV/div.
VEN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
10A/div.
VOUT
500mV/div.
VIN
10V/div.
VOUT
500mV/div.
VIN
10V/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
VOUT
500mV/div.
VIN
10V/div.
VPG
5V/div.
VSW
10V/div.
IL
10A/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board in the Design Example section.
MP8867 Rev.1.01
2/21/2017
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10
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted.
VOUT/AC
10mV/div.
VOUT/AC
10mV/div.
VOUT
500mV/div.
VIN
5V/div.
VPG
5V/div.
VSW
10V/div.
VIN/AC
100mV/div.
VIN/AC
10mV/div.
VSW
10V/div.
VSW
10V/div.
IL
10A/div.
IL
5A/div.
VOUT/AC
100mV/div.
VOUT
500mV/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
VOUT
500mV/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
IL
500mA/div.
VOUT
500mV/div.
VPG
5V/div.
VSW
10V/div.
IL
2A/div.
IL
2A/div.
VOUT
500mV/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
MP8867 Rev.1.01
www.MonolithicPower.com
2/21/2017
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Preliminary Specifications Subject to Change
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11
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
QFN14
PIN#
Name
1
BST
Bootstrap. Requires a capacitor between SW and BST to form a floating supply
across the high-side switch driver.
2
SW
Switch output. Connect using a wide PCB trace.
3
SCL
I2C serial clock.
4
SDA
I2C serial data.
5
EN/SYNC
6
A0
7
PG
8
PGND
9
VIN
10
VOUT
11
FB
12
SS
13
VCC
14
AGND
MP8867 Rev.1.01
2/21/2017
Description
EN/SYNC high to enable the MP8867. EN/SYNC has an internal 5.4µA pull-up
current of 5V, so the MP8867 can start up automatically when EN/SYNC is floating.
Apply an external clock to EN/SYNC to change the switching frequency.
I2C address set. Let A0 float or pull it to VCC to set one address. Pull A0 to ground to
set a different address.
Power good indication. PG is an open-drain structure. PG switches low if the output
voltage is out of the regulation window. PG indicates UV conditions only.
System power ground. PGND is the reference ground of the regulated output voltage.
PGND requires special consideration during PCB layout. Connect to ground plane with
copper traces and vias.
Supply voltage. The MP8867 operates on a 4.5V to 17V input rail. VIN requires a
ceramic capacitor to decouple the input rail. Connect using a wide PCB trace.
Sense input of the output voltage. Connect VOUT to the positive loading terminal.
Feedback. Connect FB to the tap of an external resistor divider from the output to
GND to set the output voltage in the FB control loop.
Soft start. Connect a capacitor from SS to ground to set the soft-start time.
Internal LDO regulator output. Decouple with a 0.47µF capacitor.
Signal ground. AGND is not connected directly to system ground internally. Make
sure AGND connects to system ground in the PCB layout.
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12
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
I2C IF &
Registers
DAC
Comparator
On-Time
Control Logic
Scheme
Figure 1: Functional Block Diagram
MP8867 Rev.1.01
2/21/2017
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13
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
The MP8867 is a high-frequency, synchronous
rectified, step-down, switch-mode converter
with built-in power MOSFETs. It offers a very
compact solution that achieves an 8A output
current with excellent load and line regulation
over a wide input supply range.
The MP8867 has three working modes:
continuous conduction mode (CCM), advanced
asynchronous modulation (AAM) mode, and
discontinuous conduction mode (DCM). The
MP8867’s default operation mode is CCM. The
register of the MODE bit (reg01 [0]) in the I2C
can be set to “0.”
CCM Control Operation
In CCM, the internal clock initiates the PWM
cycle, and the HS-FET turns on and remains on
until VILsense reaches the value set by VCOMP.
After a period of dead time, the LS-FET turns
on and remains on until the next clock cycle
begins. The device repeats this operation in
every clock cycle to regulate the output voltage.
If VILsense does not reach the value set by VCOMP
within 95% (500kHz switching frequency) of
one PWM period, the HS-FET is forced off.
AAM Control Operation
In a light-load condition, the MP8867 works in
AAM mode if the mode bit is set to “0” (see
Figure 2). VAAM is fixed internally when the input
and output voltages are fixed. VCOMP is the error
amplifier output, which represents the peak
inductor current information. When the VCOMP is
lower than VAAM, the internal clock is blocked,
and the MP8867 skips some pulses, achieving
the light-load power save. Refer to AN032 for
additional details.
The internal clock resets every time VCOMP is
higher than VAAM. The HS-FET turns on and
remains on until VILsense reaches the value set
by VCOMP.
The light-load feature in this device is optimized
for 12V input applications.
MP8867 Rev.1.01
2/21/2017
Figure 2: Simplified AAM Control Logic
DCM Control Operation
VCOMP ramps up with the increase of the output
current. When its minimum value exceeds VAAM,
the device enters DCM. In this mode, the
internal clock initiates the PWM cycle, and the
HS-FET turns on and remains on until VILsense
reaches the value set by VCOMP (see Figure 3).
After a period of dead time, the LS-FET turns
on and remains on until the inductor current
value decreases to zero. The device will repeat
the same operation in every clock cycle to
regulate the output voltage.
IL
Figure 3: DCM Control Operation
VCC Regulator
A 5V internal regulator powers most of the
internal circuitries. This regulator takes the VIN
input and operates in the full VIN range. When
VIN is greater than 5.0V, the output of the
regulator is in full regulation. When VIN is lower
than 5.0V, the output voltage decreases and
follows the input voltage. A 0.47μF ceramic
capacitor is required for decoupling purposes.
Error Amplifier (EA)
The error amplifier compares the FB voltage
against the internal reference (REF) for the FB
control loop and outputs the COMP voltage,
which controls the power MOSFET current. In
I2C mode, FB is opened and VOUT is connected
to an EA non-inverter input. The optimized
internal compensation network minimizes the
external component count and simplifies the
control loop design.
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14
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
EN/SYNC Control
EN/SYNC is a digital control pin that turns the
regulator block on and off, including I2C. Drive
EN/SYNC high to turn on the regulator; drive
EN/SYNC low to turn off the regulator. An
internal 5.4µA pull-up current to a 5V power
supply allows for automatic start-up when
EN/SYNC is floating.
SS capacitor. The SS capacitor voltage takes
over the REF voltage to the PWM comparator,
and the output voltage ramps up smoothly with
the SS voltage. Once the SS voltage reaches
the same level as the REF voltage, it continues
to ramp up while VREF takes over the PWM
comparator. At this point, the soft start finishes
and the MP8867 enters steady-state operation.
EN/SYNC is clamped internally using a 5.7V
series Zener diode (see Figure 4). Connecting
the EN/SYNC input through a pull-up resistor to
the voltage on VIN limits the EN/SYNC input
current to less than 100µA.
For example, with 12V connected to VIN,
RPULLUP ≥ (12V – 5.7V) ÷ 100µA = 63kΩ.
The SS capacitor value can be determined with
Equation (1):
Connecting EN/SYNC directly to a voltage
source without a pull-up resistor requires
limiting the amplitude of the voltage source to
≤5.5V to prevent damage to the Zener diode.
Figure 4: 5.7V Zener Diode Connection
For external clock synchronization, connect a
clock with a frequency range between 200kHz
and 2MHz to EN/SYNC. The internal clock
rising edge will synchronize with the external
clock rising edge once the external clock is
present. Set the external clock signal with a
pulse width of less than 80% of one internal
clock cycle time.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The MP8867 UVLO comparator monitors the
output voltage of the internal regulator (VCC).
The UVLO rising threshold is about 4.2V while
its falling threshold is 3.54V.
Soft Start (SS)
The MP8867 employs a soft-start (SS)
mechanism to ensure a smooth output during
power up. When EN/SYNC becomes high, an
internal current source (10μA) charges up the
MP8867 Rev.1.01
2/21/2017
CSS nF
TSS ms ISS A
VREF V
(1)
If the output capacitors have large capacitance
values, it is not recommended to set a SS time
that is too small. Otherwise, the current limit
can be hit easily during SS.
Pre-Bias Start-Up
The MP8867 is designed for a monotonic startup into a pre-biased output voltage. If the output
is pre-biased to a certain voltage during start-up,
the voltage on the soft-start capacitor is
charged. When the soft-start capacitor’s voltage
exceeds the sensed output voltage at FB(9), the
part turns on the high-side and low-side power
switches sequentially. The output voltage then
starts to ramp up with a soft-start slew rate.
NOTE:
2
9) FB voltage in the FB control loop or VOUT voltage in the I C
control loop.
Power Good Indicator
The MP8867 uses a power good (PG) output to
indicate whether the output voltage of the
converter is ready. PG is an open-drain output.
Connect PG to VCC or another voltage source
through a pull-up resistor (e.g. 100kΩ). When
the input voltage is applied, PG is pulled down
to GND. When VFB(9) is above 90% VREF, PG is
pulled high after a 100µs delay. During normal
operation, PG is pulled low when VFB(9) drops
below 70% of the VREF after a 100µs delay.
When UVLO or OTP occurs, PG is pulled low
immediately. When OC (over-current) occurs,
PG is pulled low when VFB(9) drops below 70%
of VREF after a 100µs delay.
PG will not respond to an output over-voltage
condition.
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15
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
The PG bit in the I2C register has the same
indication as the external PG.
Output Over-Voltage Protection (OVP)
The MP8867 monitors both the FB and the VOUT
to detect an over-voltage event. When the
“V_BOOT” bit = 1, the internal comparator
monitors the FB while the “V_BOOT” bit = 0
monitors the VOUT. When the feedback voltage
rises above 120% of the internal reference
voltage, the controller enters linear discharge
mode. During this period, a 35Ω resistor
connected
between
VOUT
and
ground
discharges the output to keep it within the
normal range. Once the output voltage drops
below 105% of the reference, the controller
exits linear discharge mode.
Over-Current Protection and Hiccup Mode
The MP8867 has a cycle-by-cycle, over-current
limit. When the inductor current peak value
exceeds the set current limit threshold, The HSFET turns off, and the LS-FET turns on and
remains on until the inductor current falls below
the internal “valley” current limit threshold. The
“valley” current limit circuit is employed to
decrease the operation frequency after the
“peak” current limit threshold is triggered.
Meanwhile, the output voltage drops until VFB(9)
is below the under-voltage (UV) threshold,
typically 30% below the reference. Once UV is
triggered, the MP8867 enters hiccup mode to
restart the part periodically. This protection
mode is especially useful when the output is
dead-shorted to ground. The average shortcircuit current is greatly reduced to alleviate
thermal issues and protect the regulator. The
MP8867 exits hiccup mode once the overcurrent condition is removed.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed 160°C, the entire chip shuts down.
When the temperature is less than its lower
threshold, typically 140°C, the chip is enabled
again.
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through
D1, M1, C5, L1, and C2 (see Figure 5). If VINVSW exceeds 5V, U1 will regulate M1 to
maintain a 5V BST voltage across C5.
Figure 5: Internal Bootstrap Charging Circuit
Start-Up and Shutdown
If both VIN and EN/SYNC exceed their
respective thresholds, the chip starts up. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides a stable supply for the remaining
circuitries.
Three events can shut down the chip: EN low,
VIN low, and thermal shutdown. During the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. The
COMP voltage and the internal supply rail are
then pulled down. The floating driver is not
subject to the shutdown command.
I2C Control and Default Output Voltage
When the MP8867 is enabled (EN=high and
VIN>UVLO), the chip starts up to an output
voltage set by the FB resistors with a
programmed soft-start time. The I2C bus can
then communicate with the master. If it doesn’t
receive a constant I2C communication signal,
the chip works through the FB feedback and
behaviors similarly to a traditional non-I2C part.
Floating Driver and Bootstrap Charging
MP8867 Rev.1.01
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16
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
Once the I2C receives valid output reference
voltage scaling instructions and V_BOOT = “1,”
the output voltage is determined by the resistor
divider R1, R2, and the VREF voltage. The VOUT
value is calculated by Equation (2). The VREF
default value is 0.6V:
VOUT VREF (1
R1
)
R2
(2)
If V_BOOT = “0”, the output voltage is
determined by the I2C control, and the FB loop
is disabled.
The output reference voltage scaling is realized
by adjusting the internal reference voltage
(V_REF), which is the non-inverted input of the
error amplifier. After the MP8867 receives a
valid data byte of the output reference voltage
setting, it searches the corresponding
reference voltage from the truth table and
sends the command to adjust VREF with a
controlled slew rate. The slew rate is
determined by 3 bits of another register, which
can be read and write accordingly.
MP8867 Rev.1.01
2/21/2017
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17
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
I2C INTERFACE
2
I C Serial Interface Description
I2C is a 2-wire bidirectional serial interface,
consisting of a data line (SDA) and a clock line
(SCL). The lines are pulled externally to a bus
voltage when they are “idle.” A master device
connects to the line, generates the SCL signal
and device address, and arranges the
communication sequence. The MP8867
interface is an I2C slave. The I2C interface adds
flexibility to the power supply solution. The
output voltage, transition slew rate, or other
interesting parameters can be controlled
instantaneously by the I2C interface. The default
I2C address of the MP8867 is “62” (HEX) or
“1100010” (BINARY), and “6A” (HEX) or
“1101010” (BINARY) if A0 is pulled to ground.
Data Validity
One clock pulse is generated for each data bit
transferred. The data on the SDA line must be
stable during the high period of the clock. The
high or low state of the data line can only
change when the clock signal on the SCL line is
low (see Figure 6).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 6: Bit Transfer on the I2C Bus
Start and stop are signaled by the master
device, which signifies the beginning and the
end of the I2C transfer. The start condition is
defined as the SDA signal transitioning from
high to low while the SCL is high. The stop
condition is defined as the SDA signal
transitioning from low to high while the SCL is
high (see Figure 7).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Figure 7: Start and Stop Conditions
MP8867 Rev.1.01
2/21/2017
Start and stop conditions are always generated
by the master. The bus is considered busy after
the start condition. The bus is considered free
again after a minimum of 4.7µs after the stop
condition. The bus stays busy if a repeated start
(Sr) is generated instead of a stop condition.
The start (S) and repeated start (Sr) conditions
are functionally identical.
Transfer Data
Every byte put on the SDA line must be 8 bits
long. Each byte has to be followed by an
acknowledge bit. The acknowledge-related
clock pulse is generated by the master. The
transmitter releases the SDA line (high) during
the acknowledge clock pulse. The receiver
must pull down the SDA line during the
acknowledge clock pulse, so that it remains at a
stable low during the high period of this clock
pulse.
Data transfers follow the format shown in Figure
8. A slave address is sent after the start
condition (S). This address is 7 bits long,
followed by an eighth bit, which is a data
direction bit (R/W). A zero indicates a
transmission (write), and a one indicates a
request for data (read). A data transfer is
always terminated by a stop condition (P)
generated by a master. However, if a master
still wishes to communicate on the bus, it can
generate a repeated start condition (Sr) and
address another slave without first generating a
stop condition.
SDA
SCL
1
7
8
9
R/W
ACK
1
7
8
9
1
7
8
9
P
S
START
condition
ADDRESS
DATA
ACK
DATA
ACK
STOP
condition
Figure 8: A Complete Data Transfer
The MP8867 requires a start condition, a valid
I2C address, a register address byte, and a data
byte for a single data update. The MP8867
acknowledges the receipt of each byte by
pulling the SDA line low during the high period
of a single clock pulse. A valid I2C address
selects the MP8867, which performs an update
on the falling edge of the LSB.
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18
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
REGISER DESCRIPTION
Register Map
ADD
00
NAME
VSEL
R/W
R/W
D7
V_BOOT
01
SysCntlreg1
R/W
EN
02
03
ID1
Status
R
R
D6
D5
GO_BIT
Vendor ID
Reserved
D4
D3
D2
D1
Output Reference
Switching
Slew Rate
Frequency
Die ID
VID_OK
OC
OTEW
OT
D0
Mode
PG
Register Description
1. Reg00 VSEL
NAME
BITS
DEFAULT
V_BOOT
D7
1
Output
Reference
D[6:0]
0000000
DESCRIPTION
FB control loop enable bit. V_BOOT=”1” means the output voltage is
determined by the resistor divider connected to FB (FB control loop).
V_BOOT=”0” means the output voltage is controlled by the I2C through
“VOUT” (I2C control loop). This bit is helpful for the default output voltage
setting before the I2C signal pulses. If the I2C is not used, the part works
well with FB.
Output setting bit. Set the output voltage from 0.6V to 1.87V (see Table
1). The default value is 0.6V.
Table 1: Output Voltage Chart
D[6:0]
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
001 0010
001 0011
001 0100
001 0101
001 0110
001 0111
001 1000
001 1001
001 1010
001 1011
001 1100
001 1101
001 1110
001 1111
MP8867 Rev.1.01
2/21/2017
VOUT
0.60
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
D[6:0]
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
010 0111
010 1000
010 1001
010 1010
010 1011
010 1100
010 1101
010 1110
010 1111
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
011 1010
011 1011
011 1100
011 1101
011 1110
011 1111
VOUT
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
D[6:0]
100 0000
100 0001
100 0010
100 0011
100 0100
100 0101
100 0110
100 0111
100 1000
100 1001
100 1010
100 1011
100 1100
100 1101
100 1110
100 1111
101 0000
101 0001
101 0010
101 0011
101 0100
101 0101
101 0110
101 0111
101 1000
101 1001
101 1010
101 1011
101 1100
101 1101
101 1110
101 1111
VOUT
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
1.35
1.36
1.37
1.38
1.39
1.40
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
D[6:0]
110 0000
110 0001
110 0010
110 0011
110 0100
110 0101
110 0110
110 0111
110 1000
110 1001
110 1010
110 1011
110 1100
110 1101
110 1110
110 1111
111 0000
111 0001
111 0010
111 0011
111 0100
111 0101
111 0110
111 0111
111 1000
111 1001
111 1010
111 1011
111 1100
111 1101
111 1110
111 1111
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VOUT
1.56
1.57
1.58
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
1.69
1.70
1.71
1.72
1.73
1.74
1.75
1.76
1.77
1.78
1.79
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
19
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
2. Reg01 SysCntlreg1
NAME
BITS
DEFAULT
EN
D[7]
1
GO_BIT
D[6]
0
Slew Rate
D[5:3]
100
Switching
Frequency
D[2:1]
00
Mode
D0
1
DESCRIPTION
I2C controlled turn on or turn off of the part. When the external EN is
low, the converter is off, and I2C shuts down. When EN is high, the EN
bit will take over. The default EN bit is “1.”
Switch bit of the I2C writing authority output reference command
only. Set GO_BIT=”1” to enable the I2C authority writing output
reference. When the command is finished, GO_BIT will auto reset to “0”
to prevent false operation of the VOUT scaling. If the reference
adjustment is within 50mV, GO_BIT will not reset to “0” automatically. In
this case, manually set GO_BIT to “0.” It is recommended to write
GO_BIT=”1” first before writing the output reference voltage.
D[5:3]
Slew Rate
D[5:3]
Slew Rate
000
64 mV/µs
100
4 mV/µs
001
32 mV/µs
101
2 mV/µs
010
16 mV/µs
110
1 mV/µs
011
8 mV/µs
111
0.5 mV/µs
D[2:1]
Fs
00
500kHz
01
750KHz
10
1MHz
11
1.5MHz
PFM enable/disable bit. A “0” enables PFM mode, and a high disables
PFM mode. The default is forced CCM.
3. Reg02 ID1
NAME
Vendor ID
IC Revision
ID
BITS
D[7:4]
DESCRIPTION
1000
D[3:0]
IC revision
4. Reg03 Status
NAME
Reserved
BITS
D[7:5]
VID_OK
D[4]
OC
D[3]
OTEW
D[2]
OT
D[1]
PG
D[0]
MP8867 Rev.1.01
2/21/2017
DESCRIPTION
Reserved for future use. Always set to 0.
I2C controlled voltage adjustment is done. The internal circuit compares the DAC
output with VOUT . If VOUT is in the 90%-110% range of the DAC output, the VID_OK bit
is high, which means the voltage scaling is finished. Otherwise, VID_OK= “0.” VID_OK
compares DAC with VOUT/FB. UV is 90%+-3%, OV is 110%+-3%.
Output over-current indication. When the bit is high, the IC is in hiccup mode.
Die temperature early warning bit. When the bit is high, the die temperature is higher
than 120˚C.
Over-temperature indication. When the bit is high, the IC is in thermal shutdown.
Output power good indication. When the bit is high, VOUT power is good. This means
that VOUT is higher than 90% of the designed regulation voltage. See additional details
in the Power Good Indicator section.
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MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage in a FB Control
Loop
The reference voltage and external resistor
dividers set the output voltage through FB. The
feedback resistors R1 and R3 also set the
feedback loop bandwidth with the internal
compensation capacitor. Choose the R1 value
first and calculate R2 with Equation (3)(10):
R2
R1
VOUT
1
VREF
(3)
NOTE:
10) VREF is 0.6V when the power is up or EN is on. After the
MP8867 is enabled, VREF can be programmed through the
2
I C. Set V_BOOT=1 to enable the FB control loop.
The T-type network (see Figure 9) is highly
recommended.
Setting the Output Voltage in an I2C Control
Loop
In addition to setting the output voltage through
the FB loop, the I2C loop also sets the output
voltage through VOUT by setting V_BOOT=0. In
this case, the output voltage is the set reference
voltage. Refer to Table 1 for additional details
about the output voltage settings.
Output Voltage Dynamic Scale
To set the output voltage to dynamic scaling
during normal operation, refer to Figure 10 and
follow the steps below:
1. Write the GO_bit (reg01[6]) to “1.”
2. Write reg00 to select the feedback loop
by setting V_BOOT (reg00[7]) and set
the reference voltage output reference
(reg00[0:6]) simultaneously. If the
reference adjustment is within 50mV,
GO_BIT will not reset to “0”
automatically. If this is the case, set
GO_BIT to “0” manually.
Repeat these steps if dynamic scaling is
needed for other voltages.
Figure 9: T-Type Network
Voltage Scaling
Start
Table 1 lists the recommended feedback
resistor values for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages with Default 0.6V VREF(11)
VOUT
(V)
0.9
1.0
1.2
2.5
3.3
5
R1
(kΩ)
80.6
(1%)
80.6
(1%)
80.6
(1%)
60.4
(1%)
60.4
(1%)
60.4
(1%)
R2
(kΩ)
162
(1%)
120
(1%)
80.6
(1%)
19.1
(1%)
13.3
(1%)
8.25
(1%)
R3
(kΩ)
51
(1%)
51
(1%)
40.2
(1%)
30
(1%)
20
(1%)
20
(1%)
C6
(pF)
L
(µH)
22
1.5
22
1.5
22
1.5
22
2.2
33
3.3
33
3.3
NOTE:
11) The recommended parameters are based on a 12V input
voltage and a 22µFx4 output capacitor. Different input
voltages and output capacitor values may affect the
selection of R1, R2, R3, and C6. For additional component
parameters, please refer to the Typical Application Circuits
section on page 26.
MP8867 Rev.1.01
2/21/2017
Write reg01[6]
“GO_Bit”=1
Loop Selection
FB Control Loop
(FB Sense Feedback)
Write reg00(Set
“V_BOOT”=1 &
“Vref” Code)
I2C Control Loop
(VOUT Direct Sense
Feedback)
Write reg00(Set
“V_BOOT”=0 &
“Vref” Code)
Figure 10: Output Voltage Dynamic Scale Flow
Chart
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21
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
Selecting the Inductor
Use a 0.47µH to 10µH inductor with a DC
current rating at least 25% higher than the
maximum load current for most applications.
For highest efficiency, use an inductor with a
DC resistance of less than 15mΩ. For most
designs, the inductance value is derived from
Equation (4):
L1
VOUT (VIN VOUT )
VIN IL fOSC
Choose the inductor ripple current to be
approximately 30% of the maximum load
current. The maximum inductor peak current is
calculated with Equation (5):
IL
2
(5)
Use a larger inductor for improved efficiency
under light-load conditions below 100mA.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore requires a
capacitor to supply the AC current to the stepdown converter while maintaining the DC input
voltage. For best performance, use low ESR
capacitors. Ceramic capacitors with X5R or
X7R dielectrics are recommended because of
their low ESR and small temperature
coefficients. For most applications, use twopiece 22µF capacitors.
Since C1 absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (6):
I C1 ILOAD
VOUT VOUT
1
VIN
VIN
(6)
The worse-case condition occurs at VIN=2VOUT,
shown in Equation (7):
I C1
ILOAD
2
(7)
For simplification, choose an input capacitor
with an RMS current rating greater than half the
maximum load current. The input capacitor can
be electrolytic, tantalum, or ceramic. When
MP8867 Rev.1.01
2/21/2017
VIN
(4)
Where ∆IL is the inductor ripple current.
IL(MAX) ILOAD
using electrolytic or tantalum capacitors, add a
small high-quality ceramic capacitor (e.g.
0.1μF) placed as close to the IC as possible.
When using ceramic capacitors, ensure that
they have enough capacitance to provide a
sufficient charge to prevent excessive voltage
ripple at the input. The input voltage ripple
caused by capacitance can be estimated with
Equation (8):
ILOAD VOUT VOUT
1
fS C1 VIN
VIN
(8)
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output
voltage ripple low. The output voltage ripple can
be estimated with Equation (9):
VOUT
VOUT VOUT
1
1
RESR
fS L1
VIN
8 fS C2
(9)
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated with Equation (10):
∆VOUT
V
VOUT
1 OUT
VIN
8 fS2 L1 C2
(10)
For tantalum or electrolytic capacitors, ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (11):
∆VOUT
VOUT VOUT
1
fS L1
VIN
RESR
(11)
The characteristics of the output capacitor
affect the stability of the regulation system. The
MP8867 can be optimized for a wide range of
capacitance and ESR values.
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22
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
PCB Layout Guidelines (12)
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 11
and follow the guidelines below.
4. Place the decoupling capacitor as close to
VCC and GND as possible.
5. Place the external feedback resistors next
to FB, ensuring that there is no via on the
FB trace.
6. Keep the switching node SW short and
away from the feedback network.
7. Keep the BST voltage path (BST, C5, and
SW) as short as possible. A four-layer
layout is strongly recommended to achieve
better thermal performance.
1. Place the high-current paths (PGND, VIN,
and SW) as close as possible to the device
with short, direct, and wide traces.
2. Keep the IN and GND pads connected with
large copper traces and use at least two
layers for the IN and GND traces to achieve
better thermal performance. To help with
thermal dissipation, add several vias close
to the IN and GND pads.
3. Place the input capacitors as close to VIN
and GND as possible.
NOTE:
12) The recommended layout is based on Figure 13.
R2
C4
C3
14
13
12
11
10
R5
1
9
C1
2
8
L1
3
4
5
6
7
C2
Figure 11: Recommended Layout
MP8867 Rev.1.01
2/21/2017
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MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
Design Example
Table 2 is a design example following the
application guidelines for the specifications
below:
Table 2: Design Example
VIN
VOUT
IO
12V
1V
8A
The detailed application schematics are shown
in Figure 13. The typical performance and
circuit waveforms are shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
evaluation board datasheets.
MP8867 Rev.1.01
2/21/2017
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24
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (13)
Figure 12: VIN = 4.5-17V, VOUT = 0.9V, IOUT = 8A
R5
0Ω
VIN
1
4.5V-17V
9
C1
22µF
C1A
22µF
C1B
0.1µF
5
13
C3
0.47μF
EN
PG
SDA
SCL
A0
C5
0.1µF
SW
7
3
6
1V/8A
2
VOUT
C2
22µF
EN/SYNC
VCC
R4
100kΩ
4
L1
1.5µH
BST
VIN
VOUT
10
FB
11
SS
12
C2A
22µF
C2B
22µF
C2C
22µF
MP8867
R3
51kΩ
PG
SDA
SCL
A0
AGND
14
R1
80.6kΩ
C6
22pF
R2
120kΩ
PGND
8
C4
22nF
Figure 13: VIN = 4.5-17V, VOUT = 1V, IOUT = 8A
Figure 14: VIN = 4.5-17V, VOUT = 1.2V, IOUT = 8A
NOTE:
13) All circuits are based on a 0.6V default reference voltage.
MP8867 Rev.1.01
2/21/2017
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MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
Figure 15: VIN = 4.5-17V, VOUT = 2.5V, IOUT = 8A
Figure 16: VIN = 6-17V, VOUT = 3.3V, IOUT = 8A(14)
Figure 17: VIN = 8-17V, VOUT = 5V, IOUT = 8A(14)
NOTE:
14) Based on Evaluation Board test results at 25°C ambient temperature. Lower input voltage will trigger over-temperature protection with
full load.
MP8867 Rev.1.01
2/21/2017
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26
MP8867 – SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-14 (3x4mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8867 Rev.1.01
2/21/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
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