MP8869S
The Future of Analog IC Technology
18V, 12A, High-Efficiency, Wide-Input,
Synchronous, Step-Down Converter with
Integrated Telemetry via I2C Interface
DESCRIPTION
FEATURES
The
MP8869S
is
a
high-frequency,
synchronous, rectified, step-down, switch-mode
converter with an I2C control interface. The
MP8869S offers a fully integrated solution that
achieves 12A of continuous current and 15A of
peak output current with excellent load and line
regulation over a wide input supply range.
The output voltage level can be controlled onthe-fly through an I2C serial interface. The
reference voltage range can be adjusted from
0.6V to 1.108V in 4mV steps. The voltage slew
rate, frequency, current limit, hiccup/latch-off
protection, enable, and power-saving mode are
also selectable through the I2C interface.
Constant-on-time (COT) control operation
provides fast transient response. An open-drain
power good (PG) pin indicates when the output
voltage is in the nominal range. Full protection
features include over-voltage protection (OVP),
over-current protection (OCP), and thermal
shutdown.
Vout Adjustable up to 5.5V using FB pin
Wide 2.85V to 18V Operating Input Range
12A Continuous/15A Peak Output Current
1% Internal Reference Accuracy
I2C-Programmable Reference Range from
0.6V to 1.108V in 4mV Steps with Slew
Rate Control
5% Accuracy Output Voltage and Output
Current Monitoring via I2C
Selectable PFM/PWM Mode, Adjustable
Frequency and Current Limit through I2C
Four Different Selectable I2C Addresses
External Soft Start (SS)
Open-Drain Power Good (PG) Indication
Output Over-Voltage Protection (OVP)
Hiccup/Latch-Off Over-Current Protection
(OCP)
Available in a QFN-14 (3mmx4mm)
Package
APPLICATIONS
The MP8869S is available in a QFN-14
(3mmx4mm) package.
Solid-State Drives (SSD)
Flat-Panel Televisions and Monitors
Digital Set-Top Boxes
Distributed Power Systems
Networking/Servers
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs. Output Current
VOUT = 1V, L = 1.5μH, DCR = 2.1mΩ
100
100
95
VIN=12V
EFFICIENCY (%)
EFFICIENCY (%)
90
VIN=4.5V
80
70
VIN=18V
60
85
VIN=12V
VIN=18V
80
75
50
40
0.01
VIN=4.5V
90
0.1
OUTPUT CURRENT (A)
1
70
1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (A)
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
1
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number
MP8869SGL*
EVKT-8869S
Package
QFN-14 (3mmx4mm)
Evaluation Kit
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8869SGL–Z)
TOP MARKING
MP: Product code of MP8869SGL
Y: Year code
W: Lot number
8869S: First five digits of the part number
LLL: Lot number
EVALUATION KIT EVKT-8869S
EVKT-8869S Kit contents: (Items can be ordered separately).
#
Part Number
Item
1
EV8869S-L-00A
2
EVKT-USBI2C-02
3
Tdrive-8869S
MP8869SGL Evaluation Board
Includes one USB to I2C Dongle, one USB Cable, and
one Ribbon Cable
USB Flash drive that stores the GUI installation file and
supplemental documents
Quantity
1
1
1
Order direct from MonolithicPower.com or our distributors
Figure 1. EVKT-8869S Evaluation Kit Setup
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
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© 2020 MPS. All Rights Reserved.
2
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
PACKAGE REFERENCE
TOP VIEW
QFN-14 (3mmx4mm)
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
VIN .................................................. -0.3V to 19V
VSW ................................ -0.6V (-7V for 2V
0
0.4
0
0.4
VCC < 2V
0
0.2VCC
0
0.2VCC
-
3
-
3
mA
-
50
-
50
Ω
50
-
50
-
kΩ
2
6
2
6
mA
10
40
ns
20
80
ns
10
40
ns
20
80
20
250
ns
10
80
-
-
ns
20
160
20
250
ns
10
80
-
-
ns
20
160
20
250
ns
IOL
RonL
0.3VCC
VCC +
0.5
Units
VOL level, IOL = 3mA
Both signals (SDA and
SDAH, or SCL and SCLH)
at VCC level
SCLH output levels
between 0.3Vcc and
0.7VCC
Output rise time (current
source enabled) with an
external pull-up current
source of 3mA
Capacitive load from 10pF
to 100pF
Capacitive load of 400pF
Output fall time (current
source enabled) with an
external pull-up current
source of 3mA
Capacitive load from 10pF
to 100pF
Capacitive load of 400pF
Capacitive load from 10pF
to 100pF
Capacitive load of 400pF
Capacitive load from 10pF
to 100pF
Capacitive load of 400pF
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
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© 2020 MPS. All Rights Reserved.
V
V
6
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
I/O LEVEL CHARACTERISTICS (continued)
Parameter
Pulse width of spikes that
must be suppressed by the
input filter
Symbol Condition
tSP
Input current each I/O pin
Ii
Capacitance for each I/O pin
Ci
Input voltage between
0.1VCC and 0.9VCC
HS-Mode
Min
Max
LS-Mode
Min
Max
Units
0
10
0
50
ns
-
10
-10
+10
µA
-
10
-
10
pF
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
7
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
I2C PORT SIGNAL CHARACTERISTICS
Parameter
Symbol
SCLH and SCL clock
frequency
Set-up time for a
repeated start
condition
Hold time (repeated)
start condition
Low period of the SCL
clock
High period of the
SCL clock
Data set-up time
Data hold time
Rise time of SCLH
signal
Rise time of SCLH
signal after a repeated
start condition and
after an acknowledge
bit
Fall time of SCLH
signal
Rise time of SDAH
signal
Fall time of SDAH
signal
Set-up time for stop
condition
Bus free time between
a stop and start
condition
Data valid time
Data valid
acknowledge time
Capacitive load for
each bus line
Noise margin at the
low level
Noise margin at the
high level
Condition
Cb = 100pF
Min
Max
Cb = 400pF
Min
Max
Units
fSCHL
0
3.4
0
0.4
MHz
τSU;STA
160
-
600
-
ns
τHD;STA
160
-
600
-
ns
τLOW
160
-
1300
-
ns
τHIGH
60
-
600
-
ns
τSU:DAT
τHD;DAT
10
0
70
100
0
-
ns
ns
τrCL
10
40
20*0.1Cb
300
ns
τfCL1
10
80
20*0.1Cb
300
ns
τfCL
10
40
20*0.1Cb
300
ns
τfDA
10
80
20*0.1Cb
300
ns
τfDA
10
80
20*0.1Cb
300
ns
τSU;STO
160
-
600
-
ns
τBUF
160
-
1300
-
ns
τVD;DAT
-
16
-
90
ns
τVD;ACK
-
160
-
900
ns
-
100
-
400
pF
-
400
-
400
pF
-
0.1VCC
0.1VCC
-
V
-
0.2VCC
0.2VCC
-
V
Cb
Ci
VnH
SDAH and SCLH line
SDAH + SDA line
and SCLH + SCL line
For each connected
device
For each connected
device
2
NOTE: VCC is the I C bus voltage, 1.8V to 3.6V range, and used for 1.8V, 2.5V, and 3.3V bus voltages.
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
8
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
Disabled Supply Current
vs. Input Voltage
500
8
450
7
400
6
350
5
300
4
250
3
200
2
150
1
100
3 4 5 6 7 8 9 101112131415161718
1.225
0.726
0.6
LINE REGULATION (%)
0.4
0.2
IOUT=12A
0
-0.2
IOUT=6A
-0.4
-0.6
0.71
-40-25 -10 5 20 35 50 65 80 95110125
6
9
12
15
INPUT VOLTAGE (V)
TEMPERATURE (oC)
100
90
85
80
VIN=12V
VIN=18V
1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (A)
70
VIN=18V
60
0.1
1
OUTPUT CURRENT (A)
100
95
VIN=4.5V
80
VIN=12V
70
VIN=18V
60
40
0.01
VIN=4.5V
90
VIN=12V
85
VIN=18V
80
75
50
75
70
90
EFFICIENCY (%)
EFFICIENCY (%)
VIN=4.5V
VIN=12V
80
40
0.01
18
100
95
VIN=4.5V
50
-0.8
-1
3
0.712
90
EFFICIENCY (%)
REFERENCE VOLTAGE (mV)
0.714
100
EFFICIENCY (%)
0.728
0.716
TEMPERATURE (oC)
Line Regulation vs.
Input Voltage
VOUT = 1V
1
0.8
IOUT=0A
0.718
1.2
1.195
-40-25-10 5 20 35 50 65 80 95110125
INPUT VOLTAGE (V)
0.73
0.72
1.21
1.205
0
3 4 5 6 7 8 9 101112131415161718
Reference Voltage
vs. Temperature
0.722
1.22
1.215
INPUT VOLTAGE (V)
0.724
EN Rising Threshold
vs. Temperature
EN RISING THRESHOLD (V)
Enabled Supply Current
vs. Input Voltage
0.1
OUTPUT CURRENT (A)
1
70
1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (A)
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
9
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
100
VIN=4.5V
80
70
VIN=4.5V
95
EFFICIENCY (%)
EFFICIENCY (%)
90
100
VIN=12V
VIN=18V
60
90
VIN=12V
85
90 VIN=4.5V
EFFICIENCY (%)
100
VIN=18V
80
75
50
40
0.01
0.1
70
1
85
80
VIN=4.5V
90
VIN=18V
80
VIN=12V
70
1
VIN=4.5V
95
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
VIN=18V
0.1
OUTPUT CURRENT (A)
100
100
95
90
VIN=12V
VIN=18V
85
80
75
75
60
0.01
1 2 3 4 5 6 7 8 9 10 11 12
100
100
VIN=5V
70
1
1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (A)
100
VIN=5V
VIN=7V
EFFICIENCY (%)
VIN=18V
80
VIN=12V
90
VIN=12V
VIN=18V
85
80
EFFICIENCY (%)
95
90
70
0.1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
EFFICIENCY (%)
VIN=12V
60
40
0.01
1 2 3 4 5 6 7 8 9 10 11 12
VIN=4.5V
70
70
OUTPUT CURRENT (A)
100
VIN=12V
VIN=18V
50
OUTPUT CURRENT (A)
90
80
90
VIN=18V
80
VIN=12V
70
75
60
0.01
0.1
OUTPUT CURRENT (A)
1
70
1 2 3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (A)
60
0.01
0.1
1
OUTPUT CURRENT (A)
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
10
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
Load Regulation vs.
Output Current
Load Regulation vs.
Output Current
VIN=12V
90
LOAD REGULATION (%)
EFFICIENCY (%)
95
VIN=18V
85
80
75
70
1
0.8
0.6
VOUT = 1V
VIN=18V
0.4
0.2
VIN=4.5V
-0.2
-0.4
-0.6
-0.8
-1
0
1 2 3 4 5 6 7 8 9 10 11 12
VIN=4.5V
0.4
0.2 VIN=12V
VIN=18V
0
-0.2
-0.4
-0.6
LOAD REGULATION (%)
-0.8
-1
0
1
0.8
0.6
2
4
6
8
10
LOAD REGULATION (%)
VOUT = 1.5V
1
0.8
0.6
12
4
6
8
10
VIN=12V
0
12
VIN=18V
-0.2
-0.4
-0.6
-0.8
-1
0
VOUT = 1.8V
VIN=4.5V
0.2 VIN=12V
VIN=18V
0
-0.2
-0.4
-0.6
2
4
6
8
10
OUTPUT CURRENT (A)
Load Regulation vs.
Output Current
Load Regulation vs.
Output Current
2
4
6
8
10
12
1
0.8
0.6
12
VOUT = 2.5V
VIN=12V
VIN=4.5V
0.4
0.2
VIN=18V
0
-0.2
-0.4
-0.6
-0.8
-1
0
2
4
6
8
10
12
OUTPUT CURRENT (A)
VOUT = 5V
50
45
VIN=4.5V
0.4
0.2
VIN=12V
0
-0.2
VIN=18V
-0.4
-0.6
-0.8
-1
0
0.2
Load Regulation vs.
Output Current
0.4
1
VIN=4.5V
0.4
Load Regulation vs.
Output Current
OUTPUT CURRENT (A)
VOUT = 3.3V
VOUT = 1.2V
OUTPUT CURRENT (A)
-0.8
-1
0
2
4
6
8
10
OUTPUT CURRENT (A)
12
LOAD REGULATION (%)
LOAD REGULATION (%)
Load Regulation vs.
Output Current
2
1
0.8
0.6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
1
0.8
0.6
VIN=12V
0
LOAD REGULATION (%)
VIN=7V
LOAD REGULATION (%)
100
0.6
40
VIN=4.5V
35
30
0.2
VIN=12V
15
VIN=18V
10
-0.6
-1
0
25
20
-0.2
2
4
6
8
10
12
5
0
0
2
4
6
8
10
12
14
OUTPUT CURRENT (A)
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
11
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
Load Regulation
Case Temperature Rise
vs. Output Current
VIN = 3V, VOUT = 0.9V
FS=500kHz
FS=750kHz
12
55
2
1.6
1.2
14
VIN = 3V, VOUT = 0.9V
45
0.8
10
0
FS=1.25MHz
8
VOUT=1.8V
0.4
FS=1MHz
-0.4
VOUT=1.2V
35
VOUT=0.9V
25
-0.8
6
-1.2
4
-1.6
-2
0
1
2
3
4
5
6
0
100
VOUT=1.8V
6
8
10
12
5
2 3 4 5 6 7 8 9 10 11 12 13
VOUT=1.8V
95
90
VOUT=0.9V
80
90
VOUT=1.2V
85
60
80
50
75
40
0.001
4
VIN = 3V, VOUT = 0.9V
VIN = 3V, VOUT = 0.9V
70
2
Efficiency Curve
Efficiency Curve
100
15
0.01
0.1
1
VOUT=1.2V
VOUT=0.9V
70
1 2 3 4 5 6 7 8 9 10 11 12
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
12
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
VOUT/AC
10mV/div.
VIN/AC
20mV/div.
VSW
5V/div.
IL
2A/div.
VOUT/AC
10mV/div.
VIN/AC
20mV/div.
VOUT/AC
10mV/div.
VIN/AC
10mV/div.
VSW
10V/div.
IL
2A/div.
VSW
5V/div.
IL
2A/div.
VOUT
500mV/div.
VIN
10V/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
VOUT
500mV/div.
VIN
10V/div.
VPG
5V/div.
VSW
10V/div.
VOUT/AC
10mV/div.
VIN/AC
200mV/div.
VSW
10V/div.
IL
10A/div.
VOUT
500mV/div.
VIN
10V/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
VOUT
500mV/div.
VIN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
10A/div.
IL
10A/div.
VOUT
500mV/div.
VEN
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
5A/div.
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
13
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
IL
10A/div.
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
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© 2020 MPS. All Rights Reserved.
14
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 3V, VOUT = 0.9V, L = 0.47µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
VOUT/AC
20mV/div.
VIN/AC
50mV/div.
VSW
2V/div.
IL
2A/div.
VOUT/AC
20mV/div.
VIN/AC
100mV/div.
VSW
2V/div.
IL
10A/div.
VOUT/AC
20mV/div.
VIN/AC
50mV/div.
VOUT/AC
20mV/div.
VIN/AC
50mV/div.
VSW
2V/div.
VSW
2V/div.
IL
2A/div.
IL
10A/div.
VOUT
500mV/div.
VOUT
500mV/div.
VIN
2V/div.
VPG
2V/div.
VIN
2V/div.
VPG
2V/div.
VSW
2V/div.
VSW
2V/div.
IL
10A/div.
IL
10A/div.
VOUT
500mV/div.
VOUT
500mV/div.
VPG
2V/div.
VIN
2V/div.
VPG
2V/div.
VEN
2V/div.
VPG
2V/div.
VSW
2V/div.
VSW
2V/div.
VSW
2V/div.
IL
10A/div.
IL
10A/div.
IL
10A/div.
VOUT
500mV/div.
VIN
2V/div.
2μ s/div.
MP8869S Rev. 1.05
www.MonolithicPower.com
8/4/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
15
MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board.
VIN = 3V, VOUT = 0.9V, L = 0.47µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless
otherwise noted.
VOUT
500mV/div.
VEN
2V/div.
VOUT
500mV/div.
VEN
2V/div.
VPG
2V/div.
VPG
2V/div.
VSW
2V/div.
VSW
2V/div.
IL
10A/div.
IL
10A/div.
IL
10A/div.
VOUT/AC
20mV/div.
VOUT
500mV/div.
VOUT
500mV/div.
VPG
2V/div.
VPG
2V/div.
VSW
2V/div.
VSW
2V/div.
IOUT
5A/div.
IL
10A/div.
IL
10A/div.
VOUT
500mV/div.
VOUT
500mV/div.
VPG
2V/div.
VPG
2V/div.
VSW
2V/div.
VSW
2V/div.
IL
10A/div.
IL
10A/div.
VOUT
500mV/div.
VEN
2V/div.
VPG
2V/div.
VSW
2V/div.
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
PIN FUNCTIONS
QFN-14
Pin#
Name
1
BST
2
3
4
SW
SCL
SDA
5
EN
6
A0
7
PG
8
PGND
9
VIN
10
VOUT
11
FB
12
13
SS
VCC
14
AGND
Description
Bootstrap. A capacitor is required between SW and BST to form a floating supply
across the high-side switch driver.
Switch output. Connect SW using a wide PCB trace.
I2C serial clock.
I2C serial data.
Enable. Drive EN high to enable the MP8869S. EN has a 1.5MΩ internal pull-down
resistor to GND. EN is a high-voltage pin, so it can be connected to VIN directly for auto
start-up.
I2C address set-up. Connect a resistor divider from VCC to A0 to set different I2C
addresses.
Power good indication. PG is an open-drain structure. PG is de-asserted if the output
voltage is out of the regulation window.
System power ground. PGND is the reference ground of the regulated output voltage.
PGND requires special consideration during the PCB layout. Connect PGND to the
ground plane with copper traces and vias.
Supply voltage. The MP8869S operates from a 2.85V to 18V input rail. Decouple the
input rail with a ceramic capacitor. Connect VIN using a wide PCB trace.
Output voltage sense. Connect VOUT to the positive terminal of the load.
Feedback. Connect FB to the tap of an external resistor divider from the output to GND
to set the output voltage.
Soft-start set-up. Connect a capacitor from SS to ground to set the soft-start time.
Internal LDO regulator output. Decouple VCC with a 0.47µF capacitor.
Signal ground. If AGND is not connected to PGND internally, ensure that AGND is
connected to PGND during the PCB layout.
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 2: Functional Block Diagram
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
OPERATION
Pulse-Width Modulation (PWM) Operation
The MP8869S is a fully integrated, synchronous,
rectified, step-down, switch-mode converter.
The MP8869S uses constant-on-time (COT)
control to provide fast transient response and
ease loop stabilization. Figure 3 shows the
simplified ramp compensation block.
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns on whenever the
ramp voltage (VRamp) is below the error amplifier
output voltage (VEAO), which indicates an
insufficient output voltage. The on period is
determined by both the output voltage and input
voltage to make the switching frequency fairly
constant over the input voltage range.
After the on period elapses, the HS-FET enters
the off state. By cycling the HS-FET between
the on and off states, the converter regulates
the output voltage. The integrated low-side
MOSFET (LS-FET) turns on when the HS-FET
is in its off state to minimize conduction loss.
Shoot-through occurs when both the HS-FET
and LS-FET are on at the same time, causing a
dead short between input and GND, reducing
efficiency dramatically. The MP8869S prevents
shoot-through by generating a dead-time (DT)
internally between the HS-FET off and LS-FET
on period and the LS-FET off and HS-FET on
period. The MP8869S enters either heavy-load
operation or light-load operation depending on
the amplitude of the output current.
Switching Frequency
The MP8869S uses constant-on-time (COT)
control, and there is no dedicated oscillator in
the IC. The input voltage is fed into the oneshot on-timer through the internal frequency
resistor. The duty ratio is VOUT/VIN, and the
switching frequency is fairly constant over the
input voltage range.
The MP8869S’s switching frequency can be
adjusted by setting the two bits D[5:4] in
register 02 through I2C communication. When
the output voltage setting is low and the input
voltage is high, the switching on-time may be
limited by the internal minimum on-time limit,
and switching frequency decreases. Table 1
shows the maximum switching frequency vs.
the output voltage when VIN = 12V and VIN =
5V.
Table 1: Maximum Frequency Selecting vs.
Output Voltage
Maximum Frequency Selecting
Vo (V)
5
3.3
2.5
1.8
1.5
1.2
1
0.9
0.6
VIN = 12V
1.25MHz
1.25MHz
1.25MHz
1.25MHz
1.25MHz
1MHz
750kHz
750kHz
500kHz
VIN = 5V
/
1.25MHz
1.25MHz
1.25MHz
1.25MHz
1.25MHz
1.25MHz
1.25MHz
1.25MHz
Forced PWM Operation
When the MP8869S works in forced pulsewidth modulation (PWM) mode, the MP8869S
enters continuous conduction mode (CCM),
where the HS-FET and LS-FET repeat the
on/off operation, even if the inductor current is
zero or a negative value. The switching
frequency (fSW) is fairly constant (see Figure 4).
TON is constant
VIN
Figure 3: Simplified Compensation Block
VSW
IL
Whenever VRAMP drops
below VEAO, the HS-FET
is turned ON
IOUT
VRAMP
VEAO
HS-FET
Driver
LS-FET
Driver
Figure 4: Forced PWM Operation
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
Light-Load Operation
When the MP8869S works in auto-PWM, autopulse-frequency modulation (PFM) mode, or
light-load operation, the MP8869S reduces the
switching frequency automatically to maintain
high efficiency, and the inductor current drops
almost to zero. When the inductor current
reaches zero, the LS-FET driver goes into tristate (Hi-Z) (see Figure 5). The output
capacitors discharge slowly to GND through R1
and R2. This operation improves device
efficiency greatly when the output current is low.
Ton is constant
Current Modulator Time
VIN
VSW
VOUT
IL
IOUT
VRAMP
VEAO
Figure 5: Light-Load Operation
Light-load operation is also called skip mode
since the HS-FET does not turn on as
frequently as it does during heavy-load
condition. The frequency at which the HS-FET
turns on is a function of the output current. As
the output current increases, the current
modulator regulation time period becomes
shorter, the HS-FET turns on more frequently,
and the switching frequency increases. The
output current reaches critical levels when the
current modulator time is zero and can be
determined with Equation (1):
IOUT
(VIN VOUT ) VOUT
2 L FSW VIN
(1)
The MP8869S reverts to PWM mode once the
output current exceeds the critical level. The
switching frequency then remains fairly
constant over the output current range.
The MP8869S can operate in PFM mode under
light load to improve efficiency (low-power
mode). The MP8869S can also operate in
forced PWM mode at any load condition. This
mode is selectable through the I2C control. To
enable low-power mode, set the mode bit to 0.
To disable low-power mode, set the mode bit to
1, and the converter will work in forced PWM
mode. The mode bit is set to 0 (PFM) by default.
Operating without an External Ramp
The traditional COT control scheme is
intrinsically unstable if the output capacitor’s
ESR is not large enough to be an effective
current-sense resistor. Ceramic capacitors
cannot be used as output capacitors, typically.
The MP8869S has built-in, internal ramp
compensation to ensure that the system is
stable, even without the help of the output
capacitor’s ESR. The pure ceramic capacitor
solution can reduce the output ripple, total BOM
cost, and board area significantly.
VCC Regulator
A 3.5V internal regulator powers most of the
internal circuitries. A 470nF decoupling
capacitor is needed to stabilize the regulator
and reduce ripple. This regulator takes the VIN
input and operates in the full VIN range. After
EN is pulled high and VIN is greater than 3.5V,
the output of the regulator is in full regulation.
When VIN is lower than 3.5V, the output
voltage decreases and follows the input voltage.
A 0.47μF ceramic capacitor is required for
decoupling.
Error Amplifier (EA)
The error amplifier (EA) compares the FB
voltage against the internal reference voltage
and outputs a PWM signal. The reference
voltage can be programmed from 0.6V to
1.108V via the I2C. The optimized internal ramp
compensation
minimizes
the
external
component count and simplifies the control loop
design.
Enable (EN)
EN is a digital control pin that turns the
regulator, including the I2C block, on and off.
Drive EN high to turn on the regulator; drive EN
low to turn off the regulator. An internal 1.5MΩ
resistor is connected from EN to ground. EN
can operate with an 18V input voltage, which
allows EN to be connected to VIN directly for
automatic start-up. When the external EN is
high, set the EN bit to 0 in register 01 to stop
the HS-FET and LS-FET from switching. The
MP8869S resumes switching by setting the EN
bit to 1.
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The MP8869S UVLO comparator monitors the
input voltage, VIN, and output voltage of the
VCC regulator. The MP8869S is active when
the voltages exceed the UVLO rising threshold.
Soft-Start (SS) and Pre-Bias Start-Up
Soft start (SS) prevents the converter output
voltage from overshooting during start-up.
When the chip starts up, the internal circuitry
generates a soft-start voltage that ramps up
from 0V to VCC. When SS is lower than REF,
the error amplifier uses SS as the reference.
When SS is higher than REF, the error amplifier
uses REF as the reference.
The approximate typical soft-start time can be
calculated with Equation (2):
t ss (ms)
Vref (V) Css (nF)
7A
(2)
Where Vref is reference voltage.
If the output of the MP8869S is pre-biased to a
certain voltage during start-up, the IC disables
the switching of both the HS-FET and LS-FET
until the voltage on the internal SS capacitor
exceeds the sensed output voltage at FB.
The MP8869S also provides a selectable softstop function which defines the output
discharge behavior after an EN shutdown. By
default, the output is not controlled after EN
shutdown. If setting the soft-stop control bit D[3]
to 1 in register 02 via the I2C, the output is
discharged linearly to zero in a quarter of the
soft-start time.
Over-Current Protection (OCP)
The MP8869S has a default, hiccup, cycle-bycycle, over-current limiting control. The currentlimit circuit employs both a high-side current
limit and a low-side valley current-sensing
algorithm. The MP8869S uses the RDS(ON) of the
LS-FET as a current-sensing element for the
valley current limit. If the magnitude of the highside current-sense signal is above the currentlimit threshold, the PWM on pulse is terminated,
and the LS-FET is turned on. Afterward, the
inductor current is monitored by the voltage
between GND and SW. GND is used as the
positive current sensing node, so GND should
be connected to the source terminal of the
bottom MOSFET. PWM is not allowed to initiate
a new cycle before the inductor current falls to
the valley threshold.
After the cycle-by-cycle over-current limit
occurs, the output voltage drops until VOUT is
below the under-voltage (UV) threshold
(typically 60% below the reference). Once UV is
triggered, the MP8869S enters hiccup mode to
restart the part periodically. This protection
mode is especially useful when the output is
dead shorted to ground. The average shortcircuit current is reduced greatly to alleviate
thermal issues and protect the regulator. The
MP8869S exits hiccup mode once the overcurrent condition is removed.
Short the output to ground first, and then power
on the part. The MP8869S’s I2C is disabled in
this condition. The I2C resumes operation after
the short circuit is removed. When the hiccup
over-current protection (OCP) bit D[1] in
register 01 is set to 0 by the I2C, a latch-off
occurs if OCP is triggered, and FB undervoltage protection (UVP) is triggered.
Power Good (PG)
The power good (PG) pin indicates whether the
output voltage is in the normal range compared
to the internal reference voltage. PG is an
open-drain structure. An external pull-up supply
is required. During power-up, the PG output is
pulled low. This indicates to the system to
remain off and keep the load on the output to a
minimum. This helps reduce in-rush current at
start-up.
When the output voltage is higher than 90%
and lower than 115% of the internal reference
voltage, and the soft start is finished, then the
PG signal is pulled high. When the output
voltage is lower than 85% after the soft start
finishes, the PG signal remains low. When the
output voltage is higher than 115% of the
internal reference, PG is switched low. The PG
signal rises back to high after the output voltage
drops below 105% of the internal reference
voltage.
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
PG implements an adjustable deglitch time via
the I2C whenever VOUT crosses the undervoltage and over-voltage (UV, OV) rising and
falling threshold. This guarantees the correct
indication when the output voltage is scaled
through the I2C.
The PG output is pulled low immediately when
EN UVLO, input UVLO, OCP, or overtemperature protection (OTP) are triggered.
Input Over-Voltage Protection (VIN OVP)
The MP8869S monitors VIN to detect an input
over-voltage event. This function is active only
when the output is in OV or a soft-stop
condition. When the output is in the overvoltage protection (OVP) state or soft stop is
enabled, output discharge is enabled to charge
the input voltage high. When the input voltage
exceeds the input OVP threshold, both the HSFET and LS-FET stop switching.
Output Over-Voltage Protection (OVP)
The MP8869S monitors both FB and VOUT to
detect an over-voltage event. When the FB
voltage becomes higher than 125% of the
internal reference voltage, an internal
comparator monitors FB, and the controller
enters dynamic regulation mode. The input
voltage may be charged up during this time.
When input OVP is triggered, the IC stops
switching. If OVP mode is set to auto retry in
the I2C, the IC begins switching once the input
voltage drops below the VIN OVP recover
threshold. Otherwise, the MP8869S latches off.
OVP auto-retry mode or latch-off mode occurs
only if the soft start has finished.
Dynamic regulation mode can be operated by
turning on the low side until the low-side
negative current limit is triggered. Then the
body diode of the HS-FET free-wheels the
current.
The output power charges the input, which may
trigger the VIN OVP function. In VIN OVP,
neither the HS-FET or LS-FET turn on and stop
charging VIN. If the output is still over-voltage
and the input voltage drops below the VIN OVP
threshold, repeat the operation. If the output
voltage is below 110% of the internal reference
voltage, then output OVP is exited.
Output Absolute Over-Voltage Protection
(OVP_ABS)
The MP8869S’s VOUT can be adjusted by the
feedback reference voltage and the external
resistor dividers. But MP8869S’s output voltage
must be set lower than the absolute OVP
threshold (typically 6.5V).
The MP8869S monitors VOUT to detect
absolute OVP. When VOUT is larger than 6.5V,
the controller enters dynamic regulation mode if
the OVP retry bit is set to 1 in the I2C register
01. Otherwise, the MP8869S latches off when
output OVP and input OVP are both triggered.
Absolute OVP works once both the input
voltage and EN are higher than their rising
thresholds. This means that this function can
work even during a soft start.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed 160°C, the entire chip shuts down.
When the temperature is less than its lower
threshold (typically 140°C), the chip is enabled
again.
The D[1] and D[2] bits can be monitored in
register 06 for more information about the IC
silicon temperature.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.4V with a 150mV
hysteresis. The bootstrap capacitor voltage is
regulated by VIN internally through D1, M1, C4,
L1, and C2 (see Figure 6). If VBST - VSW exceeds
3.3V, U1 regulates M1 to maintain a 3.3V BST
voltage across C4.
Figure 6: Internal Bootstrap Charging Circuit
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
Start-Up and Shutdown
If VIN, VCC, and EN exceed their respective
thresholds, the chip starts up. The reference
block starts first, generating stable reference
voltages and currents, and then the internal
regulator is enabled. The regulator provides a
stable supply for the remaining circuitries.
Several events can shut down the chip: EN low,
VIN low, VCC low, thermal shutdown, OVP
latch, and OCP latch. In the shutdown
procedure, the signaling path is blocked first to
avoid any fault triggering. VEAO and the internal
supply rail are then pulled down.
I2C Control and Default Output Voltage
When the MP8869S is enabled, the output
voltage is determined by the FB resistors with a
programmed soft-start time. After that, the I2C
bus can communicate with the master. If the
chip does not receive an I2C communication
signal continuously, it can work well through FB
and perform behavior similar to a traditional
non-I2C part. The output voltage is determined
by the resistor dividers R1, R2, and FB
reference voltage. VOUT can be calculated using
Equation (3):
VOUT VREF (
R1 R2
)
R2
(3)
Note that the output voltage cannot be set
higher than an absolute OVP threshold
(typically 6.5V).
I2C Slave Address
To support multiple devices used on the same
I2C bus, A0 can be used to select four different
addresses. A resistor divider from VCC to GND
can achieve an accurate reference voltage.
Connect A0 to this reference voltage to set a
different I2C slave address (see Figure 7). The
internal circuit changes the I2C address
accordingly. When the master sends an 8-bit
address value, the 7-bit I2C address should be
followed by 0/1 to indicate a write/read
operation. Table 2 shows the recommended I2C
address selection by the A0 voltage.
Figure 7: I2C Slave Address Selection Set-Up
Table 2: Recommended I2C Slave Address
Selection by A0 Resistor Divider
A0 Upper
Resistor
RA0_up(kΩ)
A0 Lower
Resistor
RA0_down(kΩ)
I2C Slave Address
Binary
Hex
No connect
No connect
110 0001
61H
500
300
110 0011
63H
300
500
110 0101
65H
100
No connect
110 0111
67H
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER
I2C INTERFACE
I2C Serial Interface Description
The I2C is a 2-wire, bidirectional, serial interface
consisting of a data line (SDA) and a clock line
(SCL). The lines are pulled to a bus voltage
externally when they are idle. When connecting
to the line, a master device generates the SCL
signal and device address and arranges the
communication sequence. The MP8869S
interface is an I2C slave. The I2C interface adds
flexibility to the power supply solution. The
output voltage, transition slew rate, and other
parameters can be controlled by the I2C
interface instantaneously.
Data Validity
One clock pulse is generated for each data bit
transferred. The data on the SDA line must be
stable during the high period of the clock. The
high or low state of the data line can only
change when the clock signal on the SCL line is
low (see Figure 8).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 8: Bit Transfer on the I2C Bus
Start and stop are signaled by the master
device, which signifies the beginning and the
end of the I2C transfer. The start condition is
defined as the SDA signal transitioning from
high to low while the SCL is high. The stop
condition is defined as the SDA signal
transitioning from low to high while the SCL is
high (see Figure 9).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Figure 9: Start and Stop Conditions
Start (S) and stop (P) conditions are always
generated by the master. The bus is considered
to be busy after the start condition and is
considered to be free again after a minimum of
4.7μs after the stop condition. The bus remains
busy if a repeated start (Sr) is generated
instead of a stop condition. The start and
repeated start conditions are identical
functionally.
Transfer Data
Every byte put on the SDA line must be eight
bits long. Each byte must be followed by an
acknowledge bit. The acknowledge-related
clock pulse is generated by the master. The
transmitter releases the SDA line (high) during
the acknowledge clock pulse. The receiver
must pull down the SDA line during the
acknowledge clock pulse so that it remains at
stable low during the high period of this clock
pulse.
Data transfers follow the format shown in Figure
10. After the start condition, a slave address is
sent. This address is seven bits long followed
by an eighth bit data direction bit (r/w). A zero
indicates a transmission (write), and a one
indicates a request for data (read). A data
transfer is always terminated by a stop
condition generated by the master. However, if
a master still wishes to communicate on the bus,
it can generate a repeated start condition and
address another slave without first generating a
stop condition.
SDA
SCL
1
7
8
9
R/W
ACK
1
7
8
9
1
7
8
9
P
S
START
condition
ADDRESS
DATA
ACK
DATA
ACK
STOP
condition
Figure 10: Complete Data Transfer
The MP8869S requires a start condition, a valid
I2C address, a register address byte, and a data
byte for a single data update. After receiving
each byte, the MP8869S acknowledges by
pulling the SDA line low during the high period
of a single clock pulse. A valid I2C address
selects the MP8869S. The MP8869S performs
an update on the falling edge of the LSB byte.
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
I2C WRITE AND READ SEQUENCE EXAMPLE
I2C Write Example–Write Single Register
I2C Read Example–Read Single Register
MP8869S Rev. 1.05
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
REGISER DESCRIPTION
Register Map
The MP8869S contains seven write or read
registers. Register 00 is the feedback reference
voltage selection register. Register 01 is the
first system control register and can be used to
set the slew rate, hiccup OCP, etc. Register 02
is the second system control register and can
be used to set the switching frequency, current
limit, etc.
ADD
00
NAME
VSEL
R/W
r/w
D7
Reserved
D6
01
SysCntlreg1
r/w
EN
GO_BIT
02
SysCntlreg2
r/w
03
04
05
06
Output
current
Output
voltage
ID1
Status
Register 03 and register 04 are output current
and output voltage indicating registers. Register
05 is the IC ID register. Register 06 is the IC
status indication register and can be used to
check if the IC is in over-current protection,
over-temperature protection status, etc. The
register map is shown below.
D5
PG deglitch time
D4
D3
D2
D1
D0
Feedback reference
Retry
Hiccup
Slew rate
Mode
OVP
OCP
Switching
Soft
Current limit adjust
frequency
stop
r
Output current
r
Output voltage
r
r
Vendor ID
Reserved
1) Reg00 VSEL
Register 00 is the feedback reference voltage
selection register. The MP8869S default
feedback reference voltage is 0.72V, so the
MP8869S’s default output voltage is determined
by the FB resistor divider and 0.72V default
reference after power start-up or EN start-up.
The reference voltage is adjustable from 0.6V
to 1.108V. Before adjusting the feedback
reference voltage, the bit GO_BIT of the first
system control register 01 should be set to 1,
and then the reference voltage can be adjusted
by the lower seven bits of register 00.
NAME
BITS
DEFAULT
Reserved
D[7]
0
Feedback
reference
D[6:0]
001 1110
OC
Die ID
OTEW
OT
PG
When the feedback reference voltage setting
command is finished, GO_BIT auto-resets to 0
to prevent false operation of the VOUT scaling.
GO_BIT should be set to 1 before adjusting the
feedback reference voltage via the I2C.
Table 3 shows the feedback reference voltage
selection chart from 0.6V to 1.108V via the I2C.
DESCRIPTION
Reserved for further use.
Set the feedback reference voltage from 0.6V to 1.108V (see Table 3).
The default value is 0.72V.
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
D[6:0]
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
001 0010
001 0011
001 0100
001 0101
001 0110
001 0111
001 1000
001 1001
001 1010
001 1011
001 1100
001 1101
001 1110
001 1111
VREF(V)
0.6
0.604
0.608
0.612
0.616
0.62
0.624
0.628
0.632
0.636
0.64
0.644
0.648
0.652
0.656
0.66
0.664
0.668
0.672
0.676
0.68
0.684
0.688
0.692
0.696
0.7
0.704
0.708
0.712
0.716
0.72
0.724
Table 3: Feedback Reference Voltage Selection Chart
D[6:0]
VREF (V)
D[6:0]
VREF (V)
010 0000
0.728
100 0000
0.856
010 0001
0.732
100 0001
0.86
010 0010
0.736
100 0010
0.864
010 0011
0.74
100 0011
0.868
010 0100
0.744
100 0100
0.872
010 0101
0.748
100 0101
0.876
010 0110
0.752
100 0110
0.88
010 0111
0.756
100 0111
0.884
010 1000
0.76
100 1000
0.888
010 1001
0.764
100 1001
0.892
010 1010
0.768
100 1010
0.896
010 1011
0.772
100 1011
0.9
010 1100
0.776
100 1100
0.904
010 1101
0.78
100 1101
0.908
010 1110
0.784
100 1110
0.912
010 1111
0.788
100 1111
0.916
011 0000
0.792
101 0000
0.92
011 0001
0.796
101 0001
0.924
011 0010
0.8
101 0010
0.928
011 0011
0.804
101 0011
0.932
011 0100
0.808
101 0100
0.936
011 0101
0.812
101 0101
0.94
011 0110
0.816
101 0110
0.944
011 0111
0.82
101 0111
0.948
011 1000
0.824
101 1000
0.952
011 1001
0.828
101 1001
0.956
011 1010
0.832
101 1010
0.96
011 1011
0.836
101 1011
0.964
011 1100
0.84
101 1100
0.968
011 1101
0.844
101 1101
0.972
011 1110
0.848
101 1110
0.976
011 1111
0.852
101 1111
0.98
2) Reg01 SysCntlreg1
Register 01 is the first system control register.
The highest bit, EN, can be used to turn the
part on or off when the external EN is high.
When the external EN is high, the MP8869S
shuts down by setting the EN bit to 0, and then
the HS-FET and LS-FET stop switching. The
MP8869S resumes switching by setting the EN
bit to 1 again. When the external EN is low, the
converter is off, and the I2C shuts down.
Set GO_BIT to 1 to enable the I2C’s authority to
write the feedback reference. When the
command is finished, GO_BIT auto-resets to 0
to prevent false operation of the VOUT scaling.
D[6:0]
110 0000
110 0001
110 0010
110 0011
110 0100
110 0101
110 0110
110 0111
110 1000
110 1001
110 1010
110 1011
110 1100
110 1101
110 1110
110 1111
111 0000
111 0001
111 0010
111 0011
111 0100
111 0101
111 0110
111 0111
111 1000
111 1001
111 1010
111 1011
111 1100
111 1101
111 1110
111 1111
VREF(V)
0.984
0.988
0.992
0.996
1
1.004
1.008
1.012
1.016
1.02
1.024
1.028
1.032
1.036
1.04
1.044
1.048
1.052
1.056
1.06
1.064
1.068
1.072
1.076
1.08
1.084
1.088
1.092
1.096
1.1
1.104
1.108
The IC switches to forced PWM mode when
GO_BIT is set to 1 to achieve a smooth output
waveform during the output dynamic scaling.
After the output scaling is complete, GO_BIT is
set to 0 automatically, and the IC operation
mode switches to the original mode set by the
Mode bit.
The 3-bit slew rate D[5:3] is used for slew rate
selection during the output voltage dynamic
scaling. A proper slew rate reduces the inrush
current, as well as voltage overshoot and
undershoot. Eight different slew rate levels can
be selected.
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
The bit retry OVP defines the protection mode
when OVP is triggered. When retry OVP is set
to 1, the part enters auto-recovery when OVP is
removed. When retry OVP is set to 0, the
MP8869S latches off once output OVP occurs,
and VIN OVP is triggered until VIN or EN are
toggled.
The lowest bit, mode, is used for selecting
forced PWM or auto PFM/PWM mode at light
load. When mode is set to 0, auto-PFM/PWM
mode is enabled at light load. When mode is
set to 1, forced PWM mode is enabled at light
load.
The bit hiccup OCP defines the OCP mode.
When hiccup OCP is set to 1, the MP8869S
enters hiccup mode when OCP and UVP are
both triggered. When hiccup OCP is set to 0,
the MP8869S enters latch-off when OCP and
UVP are both triggered.
NAME
BITS
DEFAULT
EN
D[7]
1
GO_BIT
D[6]
0
DESCRIPTION
I2C controlled turn-on or turn-off of the part. When the external EN is low, the
converter is off, and the I2C shuts down. When EN is high, the EN bit takes
over. The default EN bit is 1.
Switch bit of the I2C writing authority for the feedback reference command
only. Set GO_BIT = 1 to enable the I2C’s authority to write the feedback
reference. When the command is finished, GO_BIT auto-resets to 0 to
prevent false operation of the Vref scaling.
Voltage scaling examples:
1) Set GO_BIT = 1.
2) Write register 00: set the feedback reference.
3) Read back the GO_BIT value to see if the output scaling is finished. If
GO_BIT = 0, the voltage scaling is done. Otherwise, Vref is still in
adjustment.
4) Set GO_BIT = 1 if the output voltage scaling is needed a second time.
5) Write register 00: set the feedback reference.
The slew rate during the I2C-controlled voltage changing is defined by three
bits. The output voltage changes linearly from the previous voltage to the
new set voltage with a slew rate (see below). This helps reduce inrush
current, voltage overshoot, and voltage undershoot greatly.
D[5:3]
Slew Rate
D[5:3]
Slew Rate
000
40mV/μs
100
5mV/μs
001
30mV/μs
101
2.5mV/μs
010
20mV/μs
110
1.25mV/μs
011
10mV/μs
111
0.625mV/μs
FB or Vref OVP mode selection bit. 1 means the part auto-recovers when
OVP is removed. 0 means the part latches off once output OVP and VIN
OVP are both triggered until VIN or EN is power reset.
Slew rate
D[5:3]
100
Retry
OVP
D[2]
1
Hiccup
OCP
D[1]
1
Over-current protection mode selection. 1 means hiccup mode OCP. 0
means latch-off type OCP.
Mode
D[0]
0
Set mode to 0 to enable PFM mode; set mode to 1 to disable autoPFM/PWM mode. Default is auto-PFM/PWM mode for light load.
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
3) Reg02 SysCntlreg2
Register 02 is the second system control
register.
The highest two bits of the PG deglitch time
D[7:6] defines the PG signal rising and falling
edge delay times. When output OVP or UVP is
triggered, the PG signal turns low or high after a
delay time. There are four levels of PG delay
time that can be programmed by the I2C in
different conditions.
NAME
PG Deglitch
Time
BITS
D[7:6]
DEFAULT
11
Switching
Frequency
D[5:4]
00
Soft Stop
D[3]
0
Current Limit
Adjust
D[2:0]
001
The two switching frequency bits D[5:4] are
used for switching frequency selection. The
MP8869S supports up to 1.25MHz of switching
frequency by setting the two bits to 11. The
MP8869S maximum programmable switching
frequency is limited by internal minimum ontime (see Table 1).
DESCRIPTION
Power good signal rising and falling edges’ delay time. When FB or
VOUT is out of regulation window, the PG comparator is triggered, but
needs a delay time before the PG signal can turn high or low.
D[7:6]
PG Deglitch
D[7:6]
PG Deglitch
00
50%
In these cases, add an external BST diode from
VCC to BST (see Figure 13).
PCB Layout Guidelines (9)
Efficient PCB layout is critical for stable
operation. A four-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure
14 and follow the guidelines below.
1. Place the high-current paths (PGND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
2. Keep the VIN and PGND pads connected
with large copper planes.
3. Use at least two layers for the VIN and
PGND trace to achieve better thermal
performance.
4. Add several vias close to the VIN and
PGND pads to help with thermal dissipation.
Figure 13: Optional External Bootstrap Diode to
Enhance Efficiency
5. Place the input capacitors as close to VIN
and PGND as possible.
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1µF.
6. Place the decoupling capacitor as close to
VCC and PGND as possible.
Connect VCC to VIN at a Low Input Voltage
VCC can be connected to VIN directly when
VIN is lower than 3.5V. This helps improve the
MP8869S’s low input voltage efficiency
performance. To use this application set-up, the
VIN spike voltage must be limited below 4V,
otherwise VCC may be damaged.
7. Place the external feedback resistors next
to FB.
8. Ensure that there is no via on the FB trace.
9. Keep the switching node SW short and
away from the feedback network.
10. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
NOTE:
9) The recommended layout is based on
Application circuit on page 37 to page 39.
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the
Typical
35
MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
RPG
C4
R1
C3
R4
C
Figure 14: Recommended Layout
Design Example
Table 7 is a design example following the
application guidelines for the specifications
below.
Table 7: Design Example
5V
VIN
1.8V
VOUT
12A
IO
The detailed application schematics are shown
in Figure 15 through Figure 21. The typical
performance and circuit waveforms are shown
in the Typical Performance Characteristics
section. For more device applications, please
refer to the related evaluation board datasheets.
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (10)
Figure 15: VIN = 12V, VOUT = 1V, IOUT = 12A
Figure 16: VIN = 12V, VOUT = 1.2V, IOUT = 12A
Figure 17: VIN = 12V, VOUT = 1.5V, IOUT = 12A
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 18: VIN = 12V, VOUT = 1.8V, IOUT = 12A
Figure 19: VIN = 12V, VOUT = 2.5V, IOUT = 12A
Figure 20: VIN = 12V, VOUT = 3.3V, IOUT = 12A
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 21: VIN = 12V, VOUT = 5V, IOUT = 12A
NOTE:
10) All circuits are based on a 0.72V default reference voltage. The MP8869S’s output voltage can be adjusted by the feedback reference
voltage and external resistor dividers. However, the MP8869S’s output voltage must be set lower than the absolute over-voltage
protection threshold (typically 6.5V).
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-14 (3mmx4mm)
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MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
Revision History
Revision #
1.05
Revision
Date
Description
08/04/2020 Update the page4 for EC table, add 2.3 to INUVVth_f min.
Pages
Updated
Page 4
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
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