MP8869W
3V - 18V, 12A, High-Efficiency, Wide-Input,
Synchronous Step-Down Converter with
Integrated Telemetry via I2C Interface
FEATURES
DESCRIPTION
The
MP8869W
is
a
high-frequency,
synchronous, rectified, step-down, switch-mode
converter with an I2C control interface. It offers a
fully integrated solution that achieves 12A of
continuous and 15A of peak output current with
excellent load and line regulation over a wide
input supply range.
In the I2C control loop, the output voltage level
can be controlled on-the-fly through an I2C serial
interface. The voltage range can be adjusted
from 0.6V to 1.55V in 7.5mV steps. Voltage slew
rate, frequency, current limit, hiccup/latch-off
protection, enable, and power saving mode are
also selectable through the I2C interface.
Constant-on-time (COT) control operation
provides fast transient response. An open-drain
power good (PG) pin indicates that the output
voltage is in the nominal range. Full protection
features include over-voltage protection (OVP),
over-current protection (OCP), and thermal
shutdown.
Wide 3V to 18V Operating Input Range
12A Continuous/15A Peak Output Current
1% Internal Reference Accuracy
I2C Programmable Output Range from 0.6V
to 1.55V in 7.5mV Steps with Slew Rate
Control
5% Accuracy Output Voltage and Output
Current Monitoring via I2C
Selectable PFM/PWM Mode, Adjustable
Frequency and Current Limit through I2C
4 Different Selectable I2C Addresses
External Soft Start
Open-Drain Power Good Indication
Output Over-Voltage Protection (OVP)
Hiccup/Latch-Off OCP
Available in a QFN-14 (3mmx4mm)
Package
APPLICATIONS
The MP8869W is available in a QFN-14
(3mmx4mm) package.
Solid-State Drive (SSD)
Flat-Panel Television and Monitors
Digital Set-Top Boxes
Distributed Power Systems
Networking/Server
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
R2
120k
R1
80.6k
AGND
VCC
FB
C5
470nF
VOUT
A0
2
I C Bus
{
C6
22nF
SDA
MP8869W
SCL
PG
SS
EN
BST
3V-18V
VIN
VIN
C1
22µFx2
PG
EN
C3
100nF
R3
10W L1
1.5µH
SW
PGND
C2
22µFx4
VO
1V/12A
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
1
MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number
MP8869WGL*
EVKT-8869W
Package
QFN-14 (3mmx4mm)
Evaluation Kit
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP8869WGL–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
8869W: First five digits of the part number
LLL: Lot number
EVALUATION KIT EVKT-8869W
EVKT-8869W Kit contents: (Items can be ordered separately).
#
Part Number
Item
Quantity
1
EV8869W-L-00A
2
EVKT-USBI2C-02
3
Tdrive-8869W
MP8869WGL evaluation board
Includes one USB to I2C dongle, one USB cable, and one
ribbon cable
USB flash drive that stores the GUI installation file
supplemental documents
1
1
1
Order direct from MonolithicPower.com or our distributors
Input Power
Supply
Input
GUI
USB Cable
Ribbon Cable
USB to I2C Dongle
EV8869W-L-00A
Output
Load
Figure 1: EVKT-8869W Evaluation Kit Set-Up
MP8869W Rev. 1.1
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6/2/2020
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE REFERENCE
TOP VIEW
AGND
14
BST
1
SW
2
VCC
SS
FB
VOUT
13
12
11
10
3
4
5
6
7
SCL
SDA
EN
A0
PG
9
VIN
8
PGND
QFN-14 (3mmx4mm)
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
VIN ................................................... -0.3V to 19V
VSW ................................ -0.6V (-7V for 2V
0
0.4
0
0.4
VCC < 2V
0
0.2VCC
0
0.2VCC
-
3
-
3
mA
-
50
-
50
Ω
Hysteresis of Schmitt trigger
inputs
VHYS
Low-level output voltage
(open drain) at 3mA sink
current
VOL
Low-level output current
IOL
V
V
Transfer gate on resistance
for currents between SDA
and SCAH, or SCL and
SCLH
RonL
VOL level, IOL = 3mA
Transfer gate on resistance
between SDA and SCAH, or
SCL and SCLH
RonH
Both signals (SDA and
SDAH, or SCL and SCLH)
at VCC level
50
-
50
-
kΩ
Pull-up current of the SCLH
current source
Ics
SCLH output levels
between 0.3Vcc and
0.7VCC
2
6
2
6
mA
Capacitive load from 10pF
to 100pF
10
40
ns
Capacitive load of 400pF
20
80
ns
Capacitive load from 10pF
to 100pF
10
40
ns
Capacitive load of 400pF
20
80
20
250
ns
Capacitive load from 10pF
to 100pF
10
80
-
-
ns
Capacitive load of 400pF
20
160
20
250
ns
Capacitive load from 10pF
to 100pF
10
80
-
-
ns
Capacitive load of 400pF
20
160
20
250
ns
Rise time of the SCLH or
SCL signal
Fall time of the SCLH or SCL
signal
Rise time of SDAH signal
Fall time of SDAH signal
τrCL
τfCL
τrDA
τfDA
Output rise time (current
source enabled) with an
external pull-up current
source of 3mA
Output fall time (current
source enabled) with an
external pull-up current
source of 3mA
MP8869W Rev. 1.1
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6/2/2020
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6
MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
I/O LEVEL CHARACTERISTICS (continued)
Parameter
Pulse width of spikes that
must be suppressed by the
input filter
Symbol Condition
tSP
Input current each I/O pin
Ii
Capacitance for each I/O pin
Ci
Input voltage between
0.1VCC and 0.9VCC
HS-Mode
LS-Mode
Units
Min
Max
Min
Max
0
10
0
50
ns
-
10
-10
+10
µA
-
10
-
10
pF
MP8869W Rev. 1.1
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6/2/2020
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
I2C PORT SIGNAL CHARACTERISTICS
Parameter
Symbol
SCLH and SCL clock
frequency
Set-up time for a
repeated start condition
Hold time (repeated)
start condition
Low period of the SCL
clock
High period of the SCL
clock
Data set-up time
Data hold time
Rise time
signal
of
SCLH
Rise time of SCLH
signal after a repeated
START condition and
after an acknowledge
bit
Fall time of SCLH signal
Rise time of SDAH
signal
Fall time of SDAH
signal
Set-up time for stop
condition
Bus free time between a
stop and start condition
Data valid time
Data valid acknowledge
time
Capacitive load for each
bus line
Noise margin at the low
level
Noise margin at the
high level
Condition
fSCHL
Cb = 100pF
Min
Max
Cb = 400pF
Min
Max
Units
0
3.4
0
0.4
MHz
τSU;STA
160
-
600
-
ns
τHD;STA
160
-
600
-
ns
τLOW
160
-
1300
-
ns
τHIGH
60
-
600
-
ns
10
0
70
100
0
-
ns
ns
10
40
20*0.1Cb
300
ns
10
80
20*0.1Cb
300
ns
τfCL
10
40
20*0.1Cb
300
ns
τfDA
10
80
20*0.1Cb
300
ns
τfDA
10
80
20*0.1Cb
300
ns
τSU;STO
160
-
600
-
ns
τBUF
160
-
1300
-
ns
-
16
-
90
ns
-
160
-
900
ns
-
100
-
400
pF
-
400
-
400
pF
-
0.1VCC
0.1VCC
-
V
-
0.2VCC
0.2VCC
-
V
τSU:DAT
τHD;DAT
τrCL
τfCL1
τVD;DAT
τVD;ACK
Cb
Ci
VnH
SDAH and SCLH line
SDAH + SDA line
and SCLH + SCL line
For each connected
device
For each connected
device
NOTE:
VCC is the I2C bus voltage, 1.8V to 3.6V range, and used for 1.8V, 2.5V, and 3.3V bus voltage.
MP8869W Rev. 1.1
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6/2/2020
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
12
MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 12V, VOUT = 1V, L = 1.5µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 3V, VOUT = 0.9V, L = 0.47µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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© 2020 MPS. All Rights Reserved.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Performance waveforms are tested on the evaluation board.
VIN = 3V, VOUT = 0.9V, L = 0.47µH, FS = 500kHz, auto PFM/PWM mode, TA = 25°C, unless otherwise
noted.
MP8869W Rev. 1.1
www.MonolithicPower.com
6/2/2020
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
QFN-14
Pin#
Name
1
BST
Bootstrap. A capacitor is required between SW and BST to form a floating supply across
the high-side switch driver.
2
SW
Switch output. Connect SW using a wide PCB trace.
3
SCL
I2C serial clock.
4
SDA
I2C serial data.
5
EN
6
A0
7
PG
8
PGND
9
VIN
10
VOUT
11
FB
Feedback. Connect FB to the tap of an external resistor divider from the output to GND to
set the output voltage before the I2C takes control.
12
SS
Soft-start set-up. Connect a capacitor from SS to ground to set the soft-start time.
13
VCC
14
AGND
Description
Enable. Set EN high to enable the MP8869W. EN has a 1.5MΩ internal pull-down resistor
to GND. EN is a high-voltage pin, so it can be connected to VIN directly for auto start-up.
I2C address set-up. Connect a resistor divider from VCC to A0 to set different I2C
addresses.
Power good indication. PG is an open-drain structure. PG is de-asserted if the output
voltage is out of the regulation window.
System power ground. PGND is the reference ground of the regulated output voltage
and requires special consideration during PCB layout. Connect PGND to the ground plane
with copper traces and vias.
Supply voltage. The MP8869W operates from a 3V-to-18V input rail. Decouple the input
rail with a ceramic capacitor. Connect VIN using a wide PCB trace.
Output voltage sense. Connect VOUT to the positive terminal of the load.
Internal LDO regulator output. Decouple VCC with a 0.47µF capacitor.
Signal ground. If AGND is not connected to PGND internally, ensure that AGND is
connected to PGND during the PCB layout.
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
SCL
I2C IF &
Registers
DAC
On Timer
SDA
A0
COT
Control
EN
1.5MΩ
VOUT
PGND
FB
SS
AGND
PG
Figure 2: Functional Block Diagram
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
PWM Operation
The MP8869W is a fully-integrated, synchronous,
rectified, step-down, switch-mode converter.
The MP8869W uses constant-on-time (COT)
control to provide fast transient response and
easy loop stabilization. Figure 3 shows the
simplified ramp compensation block. At the
beginning of each cycle, the high-side MOSFET
(HS-FET) turns on whenever the ramp voltage
(VRamp) is lower than the error amplifier output
voltage (VEAO), which indicates an insufficient
output voltage. The on period is determined by
both the output voltage and input voltage to
make the switching frequency fairly constant
over the input voltage range.
After the on period elapses, the HS-FET enters
the off state. By cycling the HS-FET between the
on and off states, the converter regulates the
output voltage. The integrated low-side
MOSFET (LS-FET) turns on when the HS-FET
is in its off state to minimize conduction loss.
Shoot-through occurs when both the HS-FET
and LS-FET are turned on at the same time,
causing a dead short between input and GND
and reducing efficiency dramatically. The
MP8869W prevents this by generating a deadtime (DT) internally between when the HS-FET
is off and the LS-FET is on, and when the LSFET is off and the HS-FET is on. The device
enters either heavy-load operation or light-load
operation depending on the amplitude of the
output current.
VIN
HS
driver
REF
FB/VOUT
On Timer
L
Logic
Control
VOUT
SW
RAMP
RESR
R1
LS
driver
Cout
R2
Switching Frequency
The MP8869W uses constant-on-time (COT)
control, so there is no dedicated oscillator in the
IC. The input voltage is fed into the on-time oneshot timer through the internal frequency resistor.
The duty ratio is VOUT/VIN, and the switching
frequency is fairly constant over the input voltage
range.
The MP8869W’s switching frequency can be
adjusted by setting the two bits D[5:4] in register
02 through I2C communication. When the output
voltage setting is low, and the input voltage is
high, the switching on-time may be limited by the
internal minimum on-time limit, and switching
frequency decreases. Table 1 shows the
maximum switching frequency vs. the output
voltage when VIN = 12V and VIN = 5V.
Table 1: Maximum Frequency Selecting vs.
Output Voltage
Maximum Frequency Selecting
Vo (V)
VIN = 12V
VIN = 5V
5
1.25MHz
/
3.3
1.25MHz
1.25MHz
2.5
1.25MHz
1.25MHz
1.8
1.25MHz
1.25MHz
1.5
1.25MHz
1.25MHz
1.2
1MHz
1.25MHz
1
750kHz
1.25MHz
0.9
750kHz
1.25MHz
0.6
500kHz
1.25MHz
Forced PWM Operation
When the MP8869W works in forced PWM mode,
the MP8869W enters continuous conduction
mode (CCM) where the HS-FET and LS-FET
repeat the on/off operation, even if the inductor
current is zero or a negative value. The switching
frequency (FSW) is fairly constant. Figure 4 shows
the timing diagram during this operation.
Figure 3: Simplified Compensation Block
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
The MP8869W can operate in pulse frequency
modulation (PFM) mode under light load to
improve efficiency (low-power mode). The
MP8869W can also operate in forced PWM
mode at any load condition. This mode is
selectable through the I2C control. To enable
low-power mode, set the Mode bit to 0. To
disable low-power mode, set the mode bit to 1,
and the converter will work in forced PWM mode.
The Mode bit is set to 0 (PFM) by default.
Figure 4: Forced PWM Operation
Light-Load Operation
When the MP8869W works in auto PFM/PWM
mode or light-load operation, the MP8869W
reduces the switching frequency automatically to
maintain high efficiency, and the inductor current
drops almost to zero. When the inductor current
reaches zero, the LS-FET driver goes into tristate (high-Z) (see Figure 5). The output
capacitors discharge slowly to GND through R1
and R2. This operation improves device
efficiency greatly when the output current is low.
Ton is constant
Current Modulator Time
VIN
VSW
VOUT
IL
IOUT
VRAMP
VEAO
Figure 5: Light-Load Operation
Light-load operation is also called skip mode
because the HS-FET does not turn on as
frequently during heavy-load condition. The
frequency at which the HS-FET turns on is a
function of the output current. As the output
current increases, the time period that the
current modulator regulates becomes shorter,
the HS-FET turns on more frequently, and the
switching frequency increases. The output current
reaches critical levels when the current
modulator time is zero and can be determined
with Equation (1):
IOUT
(VIN VOUT ) VOUT
2 L FSW VIN
(1)
The device reverts to PWM mode once the
output current exceeds the critical level.
Afterward, the switching frequency remains fairly
constant over the output current range.
Operating without an External Ramp
The traditional constant-on-time control scheme
is unstable intrinsically if the output capacitor’s
ESR is not large enough to be an effective
current-sense resistor. Ceramic capacitors
cannot be used as output capacitors, usually.
The MP8869W has built-in, internal ramp
compensation to ensure that the system is stable,
even without the help of the output capacitor’s
ESR. The pure ceramic capacitor solution can
reduce the output ripple, total BOM cost, and
board area significantly.
VCC Regulator
A 3.5V internal regulator powers most of the
internal circuitries. A 470nF decoupling capacitor
is needed to stabilize the regulator and reduce
ripple. This regulator takes the VIN input and
operates in the full VIN range. After EN is pulled
high, and VIN is greater than 3.5V, the output of
the regulator is in full regulation. When VIN is
lower than 3.5V, the output voltage decreases
and follows the input voltage. A 0.47μF ceramic
capacitor is required for decoupling.
Error Amplifier (EA)
The error amplifier (EA) compares the FB
voltage against the internal 0.6V reference (REF)
for non-I2C mode and outputs a PWM
modulation signal. In I2C mode, FB is opened,
and VOUT is connected to the EA non-inverter
input. The reference voltage can be programmed
from 0.6V to 1.55V in the I2C control loop. The
optimized
internal
ramp
compensation
minimizes the external component count and
simplifies the control loop design.
Enable (EN)
EN is a digital control pin that turns the
MP8869W Rev. 1.1
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6/2/2020
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
regulator, including the I2C block, on and off.
Drive EN high to turn on the regulator; drive EN
low to turn off the regulator. An internal 1.5MΩ
resistor is connected from EN to ground. EN can
operate with an 18V input voltage, which allows
EN to be directly connected to VIN for automatic
start-up. When the external EN is high, set the
EN bit to 0 in register 01 to stop the HS-FET and
LS-FET from switching. The MP8869W resumes
switching by setting the EN bit to 1.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The MP8869W UVLO comparator monitors the
input voltage, VIN, and output voltage of the
VCC regulator. The MP8869W is active when
the voltages exceed the UVLO rising threshold.
Soft-Start (SS) and Pre-Bias Start-Up
The soft start (SS) prevents the converter output
voltage from overshooting during start-up. When
the chip starts up, the internal circuitry generates
a soft-start voltage that ramps up from 0V to VCC.
When SS is lower than REF, the error amplifier
uses SS as the reference. When SS is higher
than REF, the error amplifier uses REF as the
reference.
The approximate typical soft-start time can be
calculated with Equation (2):
tss (ms)
Vref (V ) Css (nF )
7 A
(2)
Where Vref is reference voltage of the FB loop or
I2C loop.
If the output of the MP8869W is pre-biased to a
certain voltage during start-up, the IC disables
the switching of both the HS-FET and LS-FET
until the voltage on the internal SS capacitor
exceeds the sensed output voltage at FB or
VOUT(7).
NOTE:
V_BOOT = 1, sense FB voltage. V_BOOT = 0, sense VOUT
voltage.
The MP8869W also provides a selectable softstop function which defines the output discharge
behavior after EN shutdown. By default, the
output is not controlled after EN shutdown. If
setting the soft-stop control bit D[3] to 1 in
register 02 via the I2C, the output is discharged
linearly to zero in a quarter of the soft-start time.
Over-Current-Protection (OCP)
The MP8869W has a default, hiccup, cycle-bycycle, over-current limiting control. The currentlimit circuit employs both high-side current limit
and a low-side "valley" current-sensing algorithm.
The part uses the RDS(ON) of the LS-FET as a
current-sensing element for the valley current
limit. If the magnitude of the high-side currentsense signal is above the current-limit threshold,
the PWM on pulse is terminated, and the LS-FET
is turned on. Afterward, the inductor current is
monitored by the voltage between GND and SW.
GND is used as the positive current sensing
node, so GND should be connected to the
source terminal of the bottom MOSFET. PWM is
not allowed to initiate a new cycle before the
inductor current falls to the valley threshold.
After the cycle-by-cycle over-current limit occurs,
the output voltage drops until VOUT is below the
under-voltage (UV) threshold, typically 60%
below the reference. Once UV is triggered, the
MP8869W enters hiccup mode to restart the part
periodically. This protection mode is especially
useful when the output is dead shorted to ground.
The average short-circuit current is greatly
reduced to alleviate thermal issues and to
protect the regulator. The MP8869W exits hiccup
mode once the over-current condition is
removed.
Short the output to ground first, and then power
on the part. The MP8869W’s I2C is disabled in
this condition. The I2C resumes operation after
the short circuit is removed. When hiccup OCP
bit D[1] in register 01 is set to 0 by the I2C, a
latch-off occurs if OCP is triggered, and FB UVP
is triggered.
POWER GOOD (PG)
The power good (PG) indicates whether the
output voltage is in the normal range compared
to the internal reference voltage. PG is an opendrain structure. An external pull-up supply is
required. During power-up, the PG output is
pulled low. This indicates to the system to remain
off and keep the load on the output to a minimum.
This helps reduce in-rush current at start-up.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
When the output voltage is higher than 90% and
lower than 115% of the internal reference
voltage, and the soft start is finished, then the PG
signal is pulled high. When the output voltage is
lower than 85% after the soft start finishes, the
PG signal remains low. When the output voltage
is higher than 115% of the internal reference, PG
is switched low; The PG signal rises back to high
after the output voltage drops below 105% of the
internal reference voltage.
PG implements an adjustable deglitch time via
the I2C whenever VOUT crosses the UV/OV
rising and falling threshold. This guarantees the
correct indication when the output voltage is
scaled through the I2C.
The PG output is pulled low immediately when
EN UVLO, input UVLO, OCP, or OTP are
triggered.
Input Over-Voltage Protection (VIN OVP)
The MP8869W monitors VIN to detect an input
over-voltage event. This function is active only
when the output is in OV or soft-stop condition.
When the output is in OVP state, or soft stop is
enabled, output discharge is enabled to charge
the input voltage high. When the input voltage
exceeds the input OVP threshold, both the HSFET and LS-FET stop switching.
Output Over-Voltage Protection (OVP)
The MP8869W monitors both FB and VOUT to
detect an over-voltage event. When setting the
V_BOOT bit to 1, an internal comparator
monitors FB. When setting the V_BOOT bit to 0,
the internal comparator monitors VOUT. When
the FB or VOUT voltage becomes higher than
125% of the internal reference voltage, the
controller enters dynamic regulation mode, and
the input voltage may be charged up during this
time. When input OVP is triggered, the IC stops
switching. If OVP mode is set to “Auto Retry” in
the I2C, the IC begins switching once the input
voltage drops below the VIN OVP recover
threshold. Otherwise, the MP8869W latches off.
OVP auto-retry mode or latch-off mode occurs
only if the soft start has finished.
The output power charges the input, which may
trigger the VIN OVP function. In VIN OVP,
neither the HS-FET or LS-FET turn on and stop
charging VIN. If the output is still over-voltage
and the input voltage drops below the VIN OVP
threshold, repeat the operation. If the output
voltage is below 110% of the internal reference
voltage, then output OVP is exited.
Output Absolute Over-Voltage Protection
(OVP_ABS)
The MP8869W monitors the VOUT voltage to
detect absolute over-voltage protection. When
VOUT is larger than 6.5V, the controller enters
dynamic regulation mode if the OVP retry bit is
set to 1 in the I2C register 01. Otherwise, the
MP8869W latches off when output OVP and
input OVP are both triggered. Absolute overvoltage protection works once both the input
voltage and EN are higher than their rising
thresholds. This means that this function can
work even during a soft start.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed 160°C, the entire chip shuts down. When
the temperature is less than its lower threshold
(typically 140°C), the chip is enabled again.
The D[1] and D[2] bits can be monitored in
register 06 for more information about IC silicon
temperature.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. This UVLO’s
rising threshold is 2.4V with a 150mV hysteresis.
The bootstrap capacitor voltage is regulated by
VIN internally through D1, M1, C4, L1, and C2
(see Figure 6). If VBST - VSW exceeds 3.3V, U1
regulates M1 to maintain a 3.3V BST voltage
across C4.
Dynamic regulation mode can be operated by
turning on the low side until the low-side negative
current limit is triggered. Then the body diode of
the HS-FET free-wheels the current.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
D1
VIN
M1
BST
U1
3.3V
C4
VOUT
SW
L1
C2
Figure 6: Internal Bootstrap Charging Circuit
START-UP AND SHUTDOWN
If VIN, VCC, and EN exceed their respective
thresholds, the chip starts up. The reference
block starts first, generating stable reference
voltages and currents, and then the internal
regulator is enabled. The regulator provides a
stable supply for the remaining circuitries.
Several events can shut down the chip: EN low,
VIN low, VCC low, thermal shutdown, OVP latch,
and OCP latch. In the shutdown procedure, the
signaling path is first blocked to avoid any fault
triggering. VEAO and the internal supply rail are
then pulled down.
I2C Control and Default Output Voltage
When the MP8869W is enabled, the output
voltage is determined by the FB resistors with a
programmed soft-start time. After that, the I2C
bus can communicate with the master. If the chip
does not receive I2C communication signal
continuously, it can works well through FB and
performs behavior similar to a traditional non-I2C
part. The output voltage is determined by the
resistor dividers R1, R2, and FB reference
voltage. VOUT can be calculated using Equation
(3):
R1
Vout(V) 0.6 (1
)
(3)
R2
The FB loop VREF is 0.6V. The FB loop reference
voltage is a fixed value that cannot be adjusted
by the I2C.
Loop Switch
There is no output slew rate control during the
FB loop to the I2C loop. When the output voltage
setting is much larger or smaller than the present
voltage, it is recommended to take two steps to
finish the loop switch and output voltage setting.
During the FB loop to the I2C loop, first set the
output voltage in the I2C loop to the present
output voltage, and then set V_BOOT = 0 to
switch the FB loop to the I2C loop. Second,
change the output voltage to the target with slew
rate control in the I2C loop. Please refer to the
Output Voltage Dynamic Scaling section on
page 30 for details.
In the I2C control loop, the output voltage is
determined by the I2C control, and the FB
feedback loop is disabled. After the MP8869W
receives a valid data byte of the output voltage
setting, the MP8869W adjusts the DAC output as
the reference voltage with a controlled slew rate.
The slew rate is determined by three bits D[5:3]
in register 01.
I2C Slave Address
To support multiple devices used on the same
I2C bus, A0 can be used to select four different
addresses. A resistor divider from VCC to GND
can achieve an accurate reference voltage.
Connect A0 to this reference voltage to set a
different I2C slave address (see Figure 7). The
internal circuit changes the I2C address
accordingly. When the master sends an 8-bit
address value, the 7-bit I2C address should be
followed by 0/1 to indicate a write/read operation.
Table 2 shows the recommended I2C address
selection by the A0 voltage.
VCC
RA0_up
A0
RA0_down
2MΩ
Figure 7: I2C Slave Address Selection Set-Up
Table 2: Recommended I2C Slave Address
Selection by A0 Resistor Divider
A0 Upper
Resistor
RA0_up(kΩ)
A0 Lower
Resistor
RA0_down(kΩ)
I2C Slave Address
Binary
Hex
No connect
No connect
110 0000
60H
500
300
110 0010
62H
300
500
110 0100
64H
100
No connect
110 0110
66H
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
I2C INTERFACE
2
I C Serial Interface Description
The I2C is a 2-wire, bidirectional, serial interface
consisting of a data line (SDA) and a clock line
(SCL). The lines are pulled to a bus voltage
externally when they are idle. When connecting
to the line, a master device generates the SCL
signal and device address and arranges the
communication sequence. The MP8869W
interface is an I2C slave. The I2C interface adds
flexibility to the power supply solution. The
output voltage, transition slew rate, and other
parameters can be controlled by the I2C interface
instantaneously.
Data Validity
One clock pulse is generated for each data bit
transferred. The data on the SDA line must be
stable during the high period of the clock. The
high or low state of the data line can only change
when the clock signal on the SCL line is low (see
Figure 8).
Start and stop conditions are always generated
by the master. The bus is considered to be busy
after the start condition, and is considered to be
free again after a minimum of 4.7μs after the stop
condition. The bus remains busy if a repeated
start (Sr) is generated instead of a stop condition.
The start (S) and repeated start (Sr) conditions
are functionally identical.
Transfer Data
Every byte put on the SDA line must be eight bits
long. Each byte has to be followed by an
acknowledge bit. The acknowledge-related
clock pulse is generated by the master. The
transmitter releases the SDA line (high) during
the acknowledge clock pulse. The receiver must
pull down the SDA line during the acknowledge
clock pulse so that it remains stable low during
the high period of this clock pulse.
Data transfers follow the format shown in Figure
10. After the start condition (S), a slave address
is sent. This address is 7 bits long followed by an
eighth bit data direction bit (R/W). A zero
indicates a transmission (write), and a one
indicates a request for data (read). A data
transfer is always terminated by a stop condition
(P) generated by the master. However, if a
master still wishes to communicate on the bus, it
can generate a repeated start condition (Sr) and
address another slave without first generating a
stop condition.
Figure 8: Bit Transfer on the I2C Bus
Start and stop are signaled by the master device,
which signifies the beginning and the end of the
I2C transfer. The start condition is defined as the
SDA signal transitioning from high to low while
the SCL is HIGH. The stop condition is defined
as the SDA signal transitioning from low to high
while the SCL is high (see Figure 9).
Figure 9: Start and Stop Conditions
Figure 10: Complete Data Transfer
The MP8869W requires a start condition, a valid
I2C address, a register address byte, and a data
byte for a single data update. After receiving
each byte, the MP8869W acknowledges by
pulling the SDA line low during the high period of
a single clock pulse. A valid I2C address selects
the MP8869W. The MP8869W performs an
update on the falling edge of the LSB byte.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
I2C Write and Read Sequence Example
8 bits
8 bits
S Slave Address
8 bits
WR A Register Address K A Write Data A P
Master to Slave
A = Acknowledge (SDA = LOW)
S = Start Condition
WR Write = 0
Slave to Master
NA = NOT Acknowledge (SDA = HIGH)
P = Stop Condition
RD Read = 1
I2C Write Example --- Write Single Register
8 bits
8 bits
8 bits
S Slave Address
WR A Register Address K A Write Data K A Write Data K+1 A
Write Data K+N A P
Multi byte write executed from current register location
(the read only register will be skipped)
Master to Slave
A = Acknowledge (SDA = LOW)
S = Start Condition
WR Write = 0
Slave to Master
NA = NOT Acknowledge (SDA = HIGH)
P = Stop Condition
RD Read = 1
I2C Write Example --- Write Multi Register
8 bits
8 bits
S Slave Address
WR A Register Address K A Sr
Register address to read specified
8 bits
8 bits
Slave Address
RD
A Read Data K NA P
Read register data from current register location
Master to Slave
A = Acknowledge (SDA = LOW)
S = Start Condition
Slave to Master
NA = NOT Acknowledge (SDA = HIGH)
P = Stop Condition
Sr = Repeat
Start Condition
WR Write = 0
RD Read = 1
I2C Read Example --- Read Single Register
8 bits
S Slave Address
8 bits
WR A Register Address K A Sr Slave Address
Register address to read specified
8 bits
8 bits
RD
A Read Data K A
Read Data K+N NA P
Multi byte read executed from current
register location until Master respond NA
Master to Slave
A = Acknowledge (SDA = LOW)
S = Start Condition
Slave to Master
NA = NOT Acknowledge (SDA = HIGH)
P = Stop Condition
Sr = Repeat
Start Condition
WR Write = 0
RD Read = 1
I2C Read Example --- Read Multi Register
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
REGISER DESCRIPTION
Register Map
The MP8869W contains six write or read registers.
Register 00 is the output voltage selection register.
Register 01 is the first system control register, and
users can use it to set the slew rate, hiccup OCP,
etc. Register 02 is the second system control
register, and users can use it to set the switching
frequency, current limit, etc.
ADD
00
NAME
VSEL
R/W
R/W
D7
V_BOOT
D6
01
SysCntlreg1
R/W
EN
GO_BIT
02
SysCntlreg2
R/W
03
04
05
06
Output
current
Output
voltage
ID1
Status
Register 03 and register 04 are output current and
output voltage indicating registers. Register 05 is
the IC ID register. Register 06 is the IC status
indication register, and users can use it to check if
the IC is in over-current protection, overtemperature protection status, etc. The register
map is shown below.
D5
PG deglitch time
D4
D3
D2
D1
D0
Output Reference
Retry
Hiccup
Slew rate
Mode
OVP
OCP
Switching
Soft
Current limit adjust
frequency
stop
R
Output current
R
Output voltage
R
R
Vendor ID
Reserved
OC
Die ID
OTEW
OT
PG
Register Description
1) Reg00 VSEL
Register 00 is the output voltage selection register.
The MP8869W default output voltage is
determined by the FB resistor divider after the
MP8869W power start-up or EN start-up. The
reference voltage in the FB control loop is fixed at
0.6V.
After the MP8869W starts up, the output voltage
can be controlled by the I2C through setting the
highest bit V_BOOT = 0. Before adjusting the
output reference voltage, the bit GO_BIT of the
NAME
BITS
DEFAULT
V_BOOT
D[7]
1
Output
reference
D[6:0]
001 1110
first system control Register 01 should be set to 1,
and then the output reference voltage can be
adjusted by the lower seven bits of register 00 in
the I2C loop. When the output reference voltage
setting command is finished, GO_BIT auto-resets
to 0 to prevent false operation of the VOUT scaling.
GO_BIT should be set to 1 before adjusting the
output reference voltage in the I2C loop.
Table 3 shows the output voltage selection chart
from 0.6V to 1.55V in the I2C control loop.
DESCRIPTION
FB control loop enable bit. V_BOOT = 1 means the output voltage is
determined by the resistor divider connecting to FB. The FB reference
voltage is fixed at 0.6V. V_BOOT = 0 means the output voltage is controlled
by I2C through VOUT. This bit is helpful for the default output voltage setting
before the I2C signal is active. If the I2C is not used, the part works well with
FB.
Set the output voltage from 0.6V to 1.55V (see Table 3). The default value is
0.825V.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
D[6:0]
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
001 0010
001 0011
001 0100
001 0101
001 0110
001 0111
001 1000
001 1001
001 1010
001 1011
001 1100
001 1101
001 1110
001 1111
VOUT(V)
0.6
0.6075
0.615
0.6225
0.63
0.6375
0.645
0.6525
0.66
0.6675
0.675
0.6825
0.69
0.6975
0.705
0.7125
0.72
0.7275
0.735
0.7425
0.75
0.7575
0.765
0.7725
0.78
0.7875
0.795
0.8025
0.81
0.8175
0.825
0.8325
Table 3: Output Voltage Selection Chart
D[6:0]
VOUT(V)
D[6:0]
VOUT(V)
010 0000
0.84
100 0000
1.08
010 0001
0.8475
100 0001
1.0875
010 0010
0.855
100 0010
1.095
010 0011
0.8625
100 0011
1.1025
010 0100
0.87
100 0100
1.11
010 0101
0.8775
100 0101
1.1175
010 0110
0.885
100 0110
1.125
010 0111
0.8925
100 0111
1.1325
010 1000
0.9
100 1000
1.14
010 1001
0.9075
100 1001
1.1475
010 1010
0.915
100 1010
1.155
010 1011
0.9225
100 1011
1.1625
010 1100
0.93
100 1100
1.17
010 1101
0.9375
100 1101
1.1775
010 1110
0.945
100 1110
1.185
010 1111
0.9525
100 1111
1.1925
011 0000
0.96
101 0000
1.2
011 0001
0.9675
101 0001
1.2075
011 0010
0.975
101 0010
1.215
011 0011
0.9825
101 0011
1.2225
011 0100
0.99
101 0100
1.23
011 0101
0.9975
101 0101
1.2375
011 0110
1.005
101 0110
1.245
011 0111
1.0125
101 0111
1.2525
011 1000
1.02
101 1000
1.26
011 1001
1.0275
101 1001
1.2675
011 1010
1.035
101 1010
1.275
011 1011
1.0425
101 1011
1.2825
011 1100
1.05
101 1100
1.29
011 1101
1.0575
101 1101
1.2975
011 1110
1.065
101 1110
1.305
011 1111
1.0725
101 1111
1.3125
D[6:0]
110 0000
110 0001
110 0010
110 0011
110 0100
110 0101
110 0110
110 0111
110 1000
110 1001
110 1010
110 1011
110 1100
110 1101
110 1110
110 1111
111 0000
111 0001
111 0010
111 0011
111 0100
111 0101
111 0110
111 0111
111 1000
111 1001
111 1010
111 1011
111 1100
111 1101
111 1110
111 1111
VOUT(V)
1.32
1.3275
1.335
1.3425
1.35
1.3575
1.365
1.3725
1.38
1.3875
1.395
1.4025
1.41
1.4175
1.425
1.4325
1.44
1.4475
1.455
1.4625
1.47
1.4775
1.485
1.4925
1.5
1.5075
1.515
1.5225
1.53
1.5375
1.545
1.5525
2) Reg01 SysCntlreg1
Register 01 is the first system control register.
The highest bit, EN, can be used to turn the part
on or off when the external EN is high. When the
external EN is high, after part shuts down by
setting the EN bit to 0, and then the HS-FET and
LS-FET stop switching. The part resumes
switching by setting the EN bit to 1 again. When
the external EN is low, the converter is off, and the
I2C shuts down.
The bit GO_BIT is only used for output reference
setting in the I2C loop. Set GO_BIT to 1 to enable
the I2C authority of writing the output reference.
When the command is finished, GO_BIT autoresets to 0 to prevent false operation of the VOUT
scaling.
The IC switches to forced PWM mode when the
GO_BIT is set to 1 to achieve a smooth output
waveform during the output dynamic scaling. After
the output scaling is complete, GO_BIT is set to 0
automatically, and the IC operation mode switches
to the original mode set by the MODE bit.
The 3-bit slew rate D[5:3] is used for slew rate
selection during the output voltage dynamic
scaling when the output voltage is controlled by
the I2C loop. A proper slew rate reduces the inrush
current, as well as voltage overshoot and
undershoot. Eight different slew rate levels can be
selected.
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
The bit Retry OVP defines the protection mode
when OVP is triggered. When Retry OVP is set to
1, the part enters auto-recovery when OVP is
removed. When Retry OVP is set to the part
latches off once output OVP occurs, and VIN OVP
is triggered until VIN or EN are toggled.
The lowest bit, Mode, is used for selecting forced
PWM or auto PFM/PWM mode at light load. When
Mode is set to 0, auto-PFM/PWM mode is enabled
at light load. When Mode is set to 1, forced PWM
mode is enabled at light load.
The bit Hiccup OCP defines the over-current
protection mode. When Hiccup OCP is set to 1,
the part enters hiccup mode when OCP and UVP
are both triggered. When Hiccup OCP is set to 0,
the part enters latch-off when OCP and UVP are
both triggered.
NAME
BITS
DEFAULT
EN
D[7]
1
GO_BIT
D[6]
0
Slew rate
D[5:3]
100
Retry
OVP
D[2]
1
Hiccup
OCP
D[1]
1
Mode
D[0]
0
DESCRIPTION
I2C controlled turn-on or turn-off of the part. When the external EN is low, the
converter is off and I2C shuts down. When EN is high, the EN bit takes over.
The default EN bit is 1.
Switch bit of the I2C writing authority for output reference command only. Set
GO_BIT = 1 to enable the I2C authority of writing the output reference. When
the command is finished, GO_BIT auto-resets to 0 to prevent false operation
of the VOUT scaling. Write the GO_BIT = 1 first, then write the output
reference voltage and change the V_BOOT status.
Voltage scaling examples:
1) Set GO_BIT = 1.
2) Write register 00: set V_BOOT = 0 and set the output reference.
3) Read back the GO_BIT value to see if the output scaling is finished. If
GO_BIT = 0, the voltage scaling is done. Otherwise, VOUT is still in
adjustment.
4) Set GO_BIT = 1 if output voltage scaling is needed a second time.
5) Write register 00: set V_BOOT = 0 and set the output reference.
The slew rate during the I2C-controlled voltage changing is defined by three
bits. The output voltage changes linearly from the previous voltage to the new
set voltage with a below slew rate. This helps to reduce the inrush current,
voltage overshoot, and voltage undershoot greatly.
D[5:3]
Slew Rate
D[5:3]
Slew Rate
000
40mV/μs
100
5mV/μs
001
30mV/μs
101
2.5mV/μs
010
20mV/μs
110
1.25mV/μs
011
10mV/μs
111
0.625mV/μs
FB or VOUT over-voltage protection mode selection bit. 1 means the part
auto-recovers when OVP is removed. 0 means the part latches off once output
OVP and VIN OVP are both triggered until VIN or EN is power reset.
Over-current protection mode selection. 1 means hiccup mode OCP. 0 means
latch-off type OCP.
Set Mode to 0 to enable PFM mode; set Mode to 1 to disable auto-PFM/PWM
mode. Default is auto-PFM/PWM mode for light load.
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
3) Reg02 SysCntlreg2
Register 02 is the second system control register.
The highest two bits of the PG deglitch time D[7:6]
defines the power good signal rising and falling edge
delay times. When output OVP or UVP is triggered,
the PG signal turns low or high after a delay time.
There are four levels of PG delay time that can be
programmed by the I2C in different conditions.
The two switching frequency bits D[5:4] are used for
switching frequency selection. The MP8869W
supports up to 1.25MHz of switching frequency by
setting the two bits to 11. The MP8869W maximum
programmable switching frequency is limited by
internal minimum on-time (see Table 1).
NAME
BITS
DEFAULT
PG deglitch
time
D[7:6]
11
Switching
frequency
D[5:4]
00
Soft stop
D[3]
0
Current limit
adjust
D[2:0]
001
The bit Soft Stop defines the output voltage
discharge behavior after EN shutdown. When Soft
Stop is set to 0, the output voltage is not controlled
after EN shutdown. When Soft Stop is set to 1, the
output voltage is discharged linearly to zero with the
set soft-stop time.
The lowest three bits, Current Limit Adjust D[2:0],
are used for peak and valley current-limit selection.
There are eight levels of current limit that can be
selected for different application conditions.
DESCRIPTION
Power good signal rising and falling edges’ delay time. When FB or VOUT
is out of regulation window, the PG comparator is triggered, but needs a
delay time before the PG signal can turn high or low.
D[7:6]
PG Deglitch
D[7:6]
PG Deglitch
00
50%
In these cases, add an external BST diode from
VCC to BST (see Figure 13).
MP8869W
Figure 13: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is IN4148,
and the recommended BST capacitor value is
0.1ST to 1cap
Connect VCC to VIN at a Low Input
Voltage
VCC can be connected to VIN directly when VIN
is lower than 3.5V. This helps improve the
MP8869W’s low input voltage efficiency
performance. To use this application set-up, the
VIN spike voltage must be limited below 4V,
otherwise VCC may be damaged.
NOTE:
9) The recommended layout is based on the Typical Application
circuit on page 34.
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
DO NOT CONNECT
TO PGND HERE
R2
AGND KELVIN
CONNECT TO PGND
AT VCC CAP
14
C3
ANGD
AGND
13
12
11
10
VCC
SS
FB
VOUT
RPG
C4
C5
R1
R4
C
C6
R3
1BST
VIN
VIN
9
PGND
8
2 SW
VIN
C1
SW
At least two layers
should be applied
for Vin and PGND
and place >20 vias
close to the part for
a better thermal
performance
3
10
L1
SCL
SDA
EN
A0
PG
3
4
5
6
7
--Top Layer
--Inner PGND Layer
--Inner Layer2
--Bottom Vin Layer
VOUT
--Bottom Layer
C2
--Via
PGND
--Via For AGND
Figure 14: Recommend Layout
Design Example
Table 7 is a design example following the
application guidelines for the specifications
below.
Table 7: Design Example
VIN
VOUT
IO
12V
1V
12A
The detailed application schematics are shown
in Figure 15 through Figure 21. The typical
performance and circuit waveforms are shown in
the Typical Performance Characteristics section.
For more device applications, please refer to the
related evaluation board datasheets.
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (10)
R3
10Ω
C3
0.1µF
1
VIN
12V
C1
22µF
9
C1A
22µF
L1
1.5µH
BST
VIN
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
Vcc
NS
6
EN
RA0_down
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
RA0_up
(I2C slave address setup
by A0 resistor divider)
VOUT
C2
22µF
VCC
RPG
100kΩ
EN
PG
1V/12A
2
SS
AGND
NS
11
R1
80.6kΩ
C4
22pF
R2
120kΩ
12
PGND
14
8
C6
22nF
Figure 15: VIN = 12V, VOUT = 1V, IOUT = 12A
R3
10Ω
C3
0.1µF
1
VIN
12V
C1
22µF
9
C1A
22µF
L1
1.5µH
BST
VIN
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
VCC
NS
6
VCC
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
RA0_up
(I2C slave address setup
by A0 resistor divider)
VOUT
C2
22µF
EN
RPG
100kΩ
EN
PG
1.2V/12A
2
SS
AGND
RA0_down
11
R1
80.6kΩ
C4
22pF
R2
80.6kΩ
12
PGND
14
8
C6
22nF
Figure 16: VIN = 12V, VOUT = 1.2V, IOUT = 12A
R3
10Ω
C3
0.1µF
1
VIN
12V
C1
22µF
9
C1A
22µF
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
EN
PG
7
SDA
SCL
3
VCC
NS
RA0_up
RA0_down
6
1.5V/12A
2
VOUT
C2
22µF
EN
VCC
RPG
100kΩ
4
(I2C slave address setup
by A0 resistor divider)
L1
1.5µH
BST
VIN
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
SS
AGND
14
11
R1
80.6kΩ
C4
22pF
R2
53.6kΩ
12
PGND
8
C6
22nF
Figure 17: VIN = 12V, VOUT = 1.5V, IOUT = 12A
NOTE:
10) All circuits are based on a 0.6V default reference voltage.
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
R3
10Ω
C3
0.1µF
1
VIN
12V
9
C1
22µF
C1A
22µF
L1
1.5µH
BST
VIN
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
VCC
NS
6
VCC
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
RA0_up
(I2C slave address setup
by A0 resistor divider)
VOUT
C2
22µF
EN
RPG
100kΩ
EN
PG
1.8V/12A
2
SS
AGND
R1
80.6kΩ
C4
22pF
R2
40.2kΩ
12
PGND
14
RA0_down
11
8
C6
22nF
Figure 18: VIN = 12V, VOUT = 1.8V, IOUT = 12A
R3
10Ω
C3
0.1µF
1
VIN
12V
9
C1
22µF
C1A
22µF
L1
2.2µH
BST
VIN
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
VCC
NS
6
EN
VCC
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
RA0_up
(I2C slave address setup
by A0 resistor divider)
VOUT
C2
22µF
RPG
100kΩ
EN
PG
2.5V/12A
2
SS
AGND
RA0_down
11
R1
80.6kΩ
C4
22pF
R2
25.5kΩ
12
PGND
14
8
C6
22nF
Figure 19: VIN = 12V, VOUT = 2.5V, IOUT = 12A
R3
10Ω
C3
0.1µF
1
VIN
12V
C1
22µF
9
C1A
22µF
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
EN
PG
SDA
SCL
RA0_up
RA0_down
VOUT
EN
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
7
PG
4
SDA
SCL
A0
6
3.3V/12A
2
C2
22µF
VCC
RPG
100kΩ
3
NS
VCC
(I2C slave address setup
by A0 resistor divider)
L1
2.2µH
BST
VIN
FB
SS
AGND
14
R4
10kΩ
11
R1
80.6kΩ
C4
22pF
R2
17.8kΩ
12
PGND
8
C6
22nF
Figure 20: VIN = 12V, VOUT = 3.3V, IOUT = 12A
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
R3
10Ω
C3
0.1µF
1
12V
VIN
9
C1
22µF
C1A
22µF
L1
3.3µH
BST
VIN
R5
499kΩ
C1B
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
VCC
NS
6
VCC
VOUT
C2A
22µF
C2C
22µF
C2B
22µF
10
MP8869W
FB
SDA
SCL
A0
SS
AGND
RA0_down
R1
80.6kΩ
R4
10kΩ
PG
RA0_up
(I2C slave address setup
by A0 resistor divider)
VOUT
C2
22µF
EN
RPG
100kΩ
EN
PG
5V/12A
2
11
C4
22pF
R2
11kΩ
12
PGND
14
8
C6
22nF
Figure 21: VIN = 12V, VOUT = 5V, IOUT = 12A(11)
NOTE:
11) Based on evaluation board test results at 25°C ambient temperature. A lower input voltage will trigger over-temperature protection with full
load.
R3
10Ω
C3
0.1µF
1
VIN
3V
9
C1 C1A
220µF 22µF
C1B
22µF
L1
0.47µH
BST
VIN
R5
499kΩ
C1C
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
Vcc
NS
6
EN
RA0_down
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
RA0_up
(I2C slave address setup
by A0 resistor divider)
VOUT
C2
22µF
VCC
RPG
100kΩ
EN
PG
0.9V/12A
2
SS
AGND
NS
11
R1
80.6kΩ
C4
NS
R2
162kΩ
12
PGND
14
8
C6
22nF
Figure 22: VIN = 3V, VOUT = 0.9V, IOUT = 12A
R3
10Ω
C3
0.1µF
1
VIN
3V
9
C1 C1A
220µF 22µF
C1B
22µF
R5
499kΩ
C1C
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
Vcc
NS
6
RA0_up
RA0_down
NS
1.2V/12A
2
VOUT
C2
22µF
EN
VCC
RPG
100kΩ
EN
PG
(I2C slave address setup
by A0 resistor divider)
L1
0.47µH
BST
VIN
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
SS
AGND
14
11
R1
80.6kΩ
C4
NS
R2
80.6kΩ
12
PGND
8
C6
22nF
Figure 23: VIN = 3V, VOUT = 1.2V, IOUT = 12A
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
R3
10Ω
C3
0.1µF
1
VIN
3V
9
C1 C1A
220µF 22µF
C1B
22µF
R5
499kΩ
C1C
0.1µF
SW
5
13
C5
0.47μF
7
4
SDA
SCL
3
Vcc
NS
6
RA0_up
RA0_down
NS
1.8V/12A
2
VOUT
C2
22µF
EN
VCC
RPG
100kΩ
EN
PG
(I2C slave address setup
by A0 resistor divider)
L1
0.47µH
BST
VIN
VOUT
C2A
22µF
C2B
22µF
C2C
22µF
10
MP8869W
R4
10kΩ
PG
FB
SDA
SCL
A0
SS
AGND
14
11
R1
80.6kΩ
C4
NS
R2
40.2kΩ
12
PGND
8
C6
22nF
Figure 24: VIN = 3V, VOUT = 1.8V, IOUT = 12A
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-14 (3mmx4mm)
PIN 1 ID
MARKING
PIN 1 ID
0.125x45° TYP.
PIN 1 ID INDEX
AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.125x45°
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS
MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP8869W Rev. 1.1
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MP8869W – 3V - 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
Revision History
Revision #
1.1
Revision Date
5/26/2020
Description
Update typical application circuit and PCB
layout guide line
Pages Updated
1,35,37,38.39,40
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP8869W Rev. 1.1
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6/2/2020
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