MPC1100A-54-0000
High-Efficiency, Non-Isolated, Fixed Ratio,
300W, Digital DC/DC Power Module
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
DESCRIPTION
FEATURES
The MPC1100A-54-0000 is a high-efficiency,
non-isolated LLC-DCX power card module with
a fixed 10:1 transformer turns ratio. The device
operates from a 40V to 60V DC primary bus and
a 4V to 6V output voltage. It can deliver up to
300W of power.
•
•
•
•
The MPC1100A-54-0000 employs MPS’s
MP2981 (a digital LLC controller) and MP8500
(a smart synchronous rectifier). These devices
can adjust the PWM to optimize the MPC1100A54-0000, and ensure that the MPC1100A-540000 works at the resonant frequency.
•
•
Up to 60A Continuous Secondary Current
PMBus/I2C Compatible
Built-In MTP to Store Custom
Configurations
Monitoring for Input Voltage, Output
Voltage, Output Current, Output Power, and
Temperature
Protections Including VIN UVLO, Output
OVP/UVP, OCP_TDC, OCP_SPIKE, and
OTP
Available in a Surface-Mount
(27mmx18mmx6mm) Package
The built-in multiple-time programmable (MTP)
memory can store and restore device
configurations. The fault status, input and output
voltage, current, and temperature can be easily
monitored via the PMBus/I2C interface.
APPLICATIONS
The MPC1100A-54-0000 is available in a
surface-mount (27mmx18mmx6mm) package.
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
•
•
•
Datacenters
DC Power Distribution
High-End Computing Systems
TYPICAL APPLICATION
3.3V
5V
VCC5V
VCC33
PG
PG
SDA
SCL
GND
EN
SDA
SCL
GND
MPC1100A54-0000
EN
VIN
VOUT
VIN
VOUT
GND ADDR PSYS GND
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
1
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
ORDERING INFORMATION
Part Number*
MPC1100A-54-0000
Package
Surface-Mount
Top Marking
MPC1100A-54
MSL Rating
3
*For Tape & Reel, add suffix –Z (e.g. MPC1100A-54-0000–Z).
TOP MARKING
Date code
Vendor’s serial number
LOT ID
MPC1100A-54
PACKAGE REFERENCE
TOP VIEW
13
14
15
16
17
18
VOUT
GND
VOUT
GND
VOUT
GND
PG
EN
3.3V GND
12 11 10
9
5V
8
VIN GND ADDR GND SDA SCL PSYS
7
6
5
4
3
2
1
Surface-Mount (27mmx18mmx6mm)
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
2
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PIN FUNCTIONS
Pin #
Name
I/O
1
PSYS
A[O]
2
3
5
7
SCL
SDA
ADDR
VIN
D[I/O]
D[I]
A[I]
Power
8
5V
Power
10
3.3V
Power
11
EN
D[I]
12
PG
13, 15, 17 VOUT
4, 6, 9, 14,
GND
16, 18
D[O]
Description
Output power indicator. Current-source output. Connect a resistor from PSYS
to GND to convert this current to a voltage signal.
PMBus/I2C clock signal.
PMBus/I2C data signal.
PMBus/I2C address 4-LSB pin setting.
Input main power supply.
5V power supply input. 5V is the power supply for the primary-side driver.
Connect a 1µF capacitor from 5V to ground.
3.3V power supply input. 3.3V is the power supply for the controller (MP2981)
and synchronous rectifier (MP8500). Connect a 4.7µF capacitor from 3.3V to
ground.
Enable control.
Power good output. The output of PG is an open-drain signal.
Power
Secondary-side power output.
Power
Power ground.
ABSOLUTE MAXIMUM RATINGS (1)
Recommended Operating Conditions (2)
Supply voltage (VIN) ......................-0.3V to +80V
Aux voltage (VCC33) ......................-0.3V to +4.0V
Aux voltage (VCC5V) ......................-0.3V to +6.5V
Address pin (ADDR) ....................-0.3V to +2.0V
Output voltage (VOUT) ...................-0.3V to +7.0V
All other pins ..................... -0.3V to VCC33 + 0.3V
Junction temperature ................................150°C
Lead temperature .....................................260°C
Supply voltage (VIN) .......................... 40V to 60V
Aux voltage (VCC33) ..................... 3.15V to 3.45V
Aux voltage (VCC5V) ......................... 4.5V to 5.5V
Operating junction temp (TJ) .....-40°C to +125°C
Notes:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its operating
conditions.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
3
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
ELECTRICAL CHARACTERISTICS
VCC33 = 3.3V, VCC5V = 5V, VIN = 54V, fSW = 813kHz, current going into the pin is positive, typical
values are at TA = 25°C, unless otherwise noted.
Parameter
Input
Input voltage
Input current (VIN quiescent
current)
Input current at no load
Auxiliary 3.3V Supply
Supply voltage
Supply current (VCC33
quiescent current)
Supply current at no load
Auxiliary 5V Supply
Supply voltage
Supply current (VCC5V
quiescent current)
Supply current at no-load
Symbol
Condition
VIN
IVIN_Q
IVIN_NO_LOAD
IVCC33_NO_LOAD
IVCC5V_NO_
LOAD
Max
Units
40
54
59.5
V
200
µA
28
3.15
Disabled, VIN = 54V, EN low,
VCC33 = 3.3V, VCC5V = 5V
Enabled, VIN = 54V, EN high,
VCC33 = 3.3V, VCC5V = 5V
VCC5V
IVCC5V_Q
Typ
Disabled, VIN = 54V, EN low,
VCC33 = 3.3V, VCC5V = 5V
Enabled, VIN = 54V, EN high,
VCC33 = 3.3V, VCC5V = 5V
VCC33
IVCC33_Q
Min
4.5
Disabled, VIN = 54V, EN low,
VCC33 = 3.3V, VCC5V = 5V
Enabled, VIN = 54V, EN high,
VCC33 = 3.3V, VCC5V = 5V
3.3
mA
3.45
V
35
mA
142
mA
5
5.5
V
280
µA
26
mA
Output
Transformer ratio
K
Continuous output current (3)
IOUT_DC
(3)
Output current pulse
IOUT_DC_PULSE
(3)
Output resistance
RLL
Switching frequency
fSW
Ambient efficiency
η
Protections
Input voltage under-voltage
VIN_UVLO
lockout (UVLO)
Input voltage over-voltage
VIN_OVP
protection (OVP)
Output voltage UVP
VOUT_UVP
Output voltage OVP
VOUT_OVP
Output current over-current
IOUT_OC
protection (OCP) (3)
Over-temperature (OT)
TOTP
shutdown threshold (3)
TOTP_HYS
OT recovery hysteresis (3)
Protection recovery delay
time (3)
Primary side to secondary side,
VIN = 54V, IOUT = 0A, K = VOUT / VIN
VIN = 54V, TA = 25°C
500µs pulse, 40V < VIN < 59.5V
VIN = 54V, IOUT = 15A
PMBus/I2C reading tON, VIN, IOUT = 1A
VIN = 54V, IOUT = 7.5A, TA = 25°C
IOUT = 0A
Latch mode, IOUT = 0A
Latch mode, IOUT = 0A
Latch mode, IOUT = 0A
1/10
47
A
A
mΩ
kHz
%
90
3
813
94
35.5
37
39.5
V
60
63
66
V
3.0
7.2
Latch mode
V
V
140
A
130
°C
30
°C
tPRO_DELAY
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
12.7
ms
4
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
ELECTRICAL CHARACTERISTICS (continued)
VCC33 = 3.3V, VCC5V = 5V, VIN = 54V, fSW = 813kHz, current going into the pin is positive, typical
values are at TA = 25°C, unless otherwise noted.
Parameter
EN
Low-voltage input
Symbol
Condition
Min
Typ
Max
Units
0.4
V
3
8
V
µA
0.8
1
ms
VIL(EN)
High-voltage input
Enable high leakage
Enable delay (3)
VIH(EN)
IIH(EN)
tA
PSYS
PSYS output voltage (3)
PG Output
PG low voltage
PG high leakage current
PMBus/I2C DC Characteristics
High-voltage input (3)
(3)
Low-voltage input
Input leakage current
Pin capacitance (3)
VPSYS
0.8
EN high to soft start begins,
VOUT = 10%
VIN = 54V, IOUT = 47A, RSYS = 20kΩ
0.634
V
0.1
V
µA
ILPG
IPG = 20mA
VPG = 3.3V
-3
VIH
SCL, SDA
1.35
VIL
SCL, SDA
SCL, SDA, ALT#
-10
0.8
+10
10
V
µA
pF
10
1000
kHz
CPIN
+3
V
2
PMBus/I C Timing Characteristics (3) (4)
Operating frequency range
fPMB
Bus free time
Holding time
Repeated start condition setup time
tBUF
Between stop and start condition
tHD_STA
0.5
0.26
µs
µs
tSU_STA
0.26
µs
Stop condition set-up time
tSU_STO
0.26
µs
Data hold time
Data set-up time
Clock low timeout
Clock low period
Clock high period
Clock/data falling time
Clock/data rising time
tHD_DAT
tSU_DAT
tTIMEOUT
tLOW
tHIGH
tF
tR
10
50
25
0.5
0.26
ns
ns
ms
µs
µs
ns
ns
35
50
120
120
Notes:
3) Guaranteed by design or characterization data. Not tested in production.
4) The device supports 100kHz, 400kHz, and 1MHz bus speeds. The PMBus/I2C timing parameters in this table are for operation at 400kHz
and 1MHz. If the PMBus/I2C operating frequency is 100kHz, refer to SMBus specifications for the timing parameters
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
5
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Efficiency vs. Output Current
Power Loss vs. Output Current
0.98
18
16
POWER LOSS (W)
EFFICIENCY (%)
0.97
0.96
Vin=40V
0.95
Vin=48V
0.94
Vin=54V
20
12
Vin=48V
10
Vin=54V
8
Vin=60V
6
4
0
0.93
10
Vin=40V
2
Vin=60V
0
14
30
40
IOUT (A)
50
60
0
10
20
30
IOUT (A)
40
50
60
Output Voltage vs. Output
Current
7
V OUT (V)
6
5
4
Vin=40V
3
Vin=48V
Vin=54V
2
Vin=60V
1
0
10
20
30
IOUT (A)
40
50
60
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
6
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = 25°C, unless otherwise noted.
Start-Up through VIN
Start-Up through VIN
VIN = 54V, IOUT = 0A
VIN = 54V, IOUT = 60A, full load
CH2: VOUT
CH2: VOUT
CH2: VIN
CH2: VIN
Remote On
Remote On
VIN = 54V, IOUT = 0A, EN on
VIN = 54V, IOUT = 60A, EN on
CH4: VOUT
CH4: VOUT
CH2: EN
CH2: EN
Transient Response
Transient Response
VIN = 54V, 1A/µs step change in load from
100% to 75% of IO_MAX
VIN = 54V, 1A/µs step change in load from 75%
to 100% of IO_MAX
CH4:
CH4:
VOUT/AC
VOUT/AC
CH3: IOUT
CH3: IOUT
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
7
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
FUNCTIONAL BLOCK DIAGRAM
Single Integrated
Magnetic Core
MP8500 x 2
SR
VIN = 40V to 60V
VOUT = 4V to 6V
VIN
VCC5V
SR
Driver
CR
MP8500 x2
SR
LR
VIN
Driver
SR
GND
PWMS2
VCC33V
Temp
PWMS1
CS2
PWMP1
PWM
Control
SR
Control
CS1
PWMP2
SCL SDA
MP2981
Figure 1: Functional Block Diagram
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
8
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
OPERATION
The MPC1100A-54-0000 incorporates four
MP8500 devices. The MP8500 supports
accurate current-sense (CS) functionality. Its CS
pin sources a current that is proportional to the
output current (5µA/A), and generates a voltage
by connecting a resistor to GND. The MP2981
can use this signal to monitor and report the
output current (IOUT), as well as protect the
MPC1100A-54-0000 power card module.
The MPC1100A-54-0000 is a full-bridge LLCDCX power converter module with a 10:1
transformer turns ratio. The device incorporates
the MP2981, a digital LLC controller that
provides two PWM channels for primary-side
control as well as two PWM channels for
secondary-side control.
The LLC circuit is most efficient when working at
the resonant frequency (see Figure 2). LR and CR
have tolerances and temperature shifts that may
cause the operating frequency to shift away from
the resonant frequency.
The MP8500 can also send a zero-current
detection (ZCD) signal to the MP2981 once a 0A
current is detected. Then the MP2981 aligns the
PWM off time and ZCD signal by fine-tuning the
PWM on time (tON) to let the MPC1100A-54-0000
operate at the resonant frequency.
The resonant frequency (fR) can be calculated
with Equation (1):
fR =
1
2π LR CR
During the dead time, the transformer’s
magnetizing inductor current discharges the
FET’s output capacitor to zero before the FET
turns on. This helps the FET achieve zerovoltage switching (ZVS) on its primary side. The
MP8500 turns off after ZCD, and then zerocurrent switching (ZCS) is implemented.
(1)
With MPS’s MP8500 (a smart synchronous
rectifier), the MPC1100A-54-0000 can be
optimized to work at the resonant frequency,
which improves the module’s efficiency.
PWM1
IR
PWM1
PWM2
PWM2
IR
IM
IM
V DS1
tDEAD
IREC
I D1
ID2
VC
t0 t1
t2 t3 t4
t5 t6
Figure 2: LLC Waveform
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
9
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Power-On Sequence
MTP operation can be easily accomplished with
MPS’s GUI software, downloaded from the MPS
Multiple-Time Programmable (MTP) Memory
website. The MTP can be subjected to more than
Operation
100,000 erase and write cycles.
The
MP2981
uses
the
multiple-time
programmable (MTP) memory to store the
Start-Up Sequence
configuration
parameters,
including
the
After VDD33 is ready, the internal reset of the
switching frequency (fSW), soft-start time (tSS),
MP2981 is released and the clock starts ticking
and protection parameters. Default values are
(see Figure 4). The MP2981 begins to copy data
preconfigured during manufacturing. Data can
regardless of the EN pin’s state. Then the
be reconfigured using the STORE_USER_ALL
MPC1100A-54-0000 can be powered on by
command (17h) or STORE_ALL command (15h)
turning on EN, pulling VIN high, or by receiving
via the PMBus/I2C interface.
an ON command.
The configurations are restored by the MTP
during the power-on sequence, or by receiving a
VDD3V3
RESTORE_USER_ALL (18h) command or
RESTORE_ALL (16h) command from the
VDD1V8
PMBus/I2C. Figure 3 shows the device’s system
state machine. ENABLE_CMD means that the
VDD3V3_UVLO
MSB of 01H is 1. MEMORY_OK means that the
VDD1V8_UVLO
MTP has no signature error or CRC error, or that
an MTP fault state has been cleared after
VDD3V3_OK
copying the MTP.
VDD1V8_OK
Pll_200M
Rest
NRST
POR
EN Pin
MTP Copy Start Delay
Copy NVM
NVM
Faults
Data Invalid
VOUT
Figure 4: MP2981 Start-Up Sequence
Waiting
Fault Clear
System
Initialization
MEMORY_OK
Start Wait
Wait B
Retry
Delay
The first dead time value is (TON_MIN +
DEAD_TIME (1Bh) - TON_MIN_LIM). Then it
drops to DEAD_TIME (1Bh), which is the normal
working value. The frequency remains the same.
TON_DELAY
Power Out
Wait A
Wait C
Soft Start
The MP2981 adopts pulse-width modulation
(PWM) mode for the first PWM cycle during soft
start. During the first tON increasing stage, PWM
runs at the maximum frequency. The PWM on
time begins at TON_MIN_LIM (1Fh), bits[13:8]
and increases to TON_MIN (1Ch).
Wait B
~ENABLE
_CMD
~ENABLE
_CMD
Figure 3: System State Machine
During the second tON increasing stage, the
PWM frequency is reduced from its maximum
value to the resonant frequency. tON increases
from TON_MIN (1Ch) to TON_NORMAL (1Eh),
and the dead time is fixed. This helps reduce the
inrush current during the first PWM cycles during
soft start compared to traditional soft start
methodology.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
10
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Primary ZCD Loop
TON_ZCDLOOP_DEC (0Fh), bits[11:8] if
ZCDLOOP_LATCHTON_EN (0Ch), bit[5] is
The MP2981 detects the ZCD signal from the
enabled.
synchronous rectifier (SR), and adjusts the PWM
frequency to its resonant value according to
Fault Monitoring and Protections
ZCD. ZCD going high (or low, selected by
The MPC1100A-54-0000 monitors the input
SEL_ZCD_NEG (0Fh), bit[14]), means that the
voltage (VIN), output voltage (VOUT), output
SR current goes negative. Both phases have
current (IOUT), MP8550 temperature, and
their own ZCD, which can be enabled together
MP2981 die temperature.
or separately (0Fh, bits[6:5]).
The MPC1100A-54-0000 also supports various
The valid area for detecting ZCD is set by
fault monitoring and protections, including VIN
register 0Bh. For more details, see the
under-voltage lockout (UVLO), VIN over-voltage
ZCD_TIME_SET (0Bh) section on page 24. If the
protection (OVP), over-current protection (OCP)
ZCD edge is within the valid setting area, tON falls
spike, OCP thermal design current (TDC), output
by WEIGHTN_ZCD (29h), bits[15:8]. If not, tON
OVP, under-voltage protection (UVP), overincreases by WEIGHTP_ZCD (29h), bits[6:0].
temperature protection (OTP), and DrMOS fault
The adjusting speed is determined by register
protection.
29h. After 256 continuous valid ZCD pulses
VIN Under-Voltage Lockout (UVLO) and Over(including phase 1 and phase 2), tON drops by
Voltage Protection (OVP)
5ns. If no valid ZCD occurs within 256
continuous PWM pulses (including phase 1 and
VIN is sensed and monitored by the analog-tophase 2), then tON increases by 5ns.
digital converter (ADC). The ADC-sensed input
voltage is converted to an unsigned binary
This function can be limited by the sampled SR
format (READ_VIN (0.125V/LSB, 88h)) using
current. The TDC current must be within the
the value set by VIN_CAL_GAIN (3Ah), which is
light-load and heavy-load limitations defined by
proportional to the input voltage divider.
register 0Ch if the load limit is enabled (0Ch,
bits[4]).
The READ_VIN value is compared with the
VIN_ON (35h) and VIN_OFF (36h) values to
If LOADLOW_ZCDLOOP_EN (0Ch), bit[15] is
control the VIN UVLO threshold. If VIN is below or
not enabled, the ZCD adjusting frequency can be
equal to VIN_ON when the device is off (PWM is
held. The frequency can be held if any of the
not generated during this time) or VIN drops
following conditions are met:
below VIN_OFF at any time, then VIN UVLO
• The
CS1
pin
current
is
below
occurs (see Figure 5). The only exception is
CMP_CS1_ENTERFREQ (1Ah), bit[8], and
when the MTP is copying at start-up.
1Ah, bits[3:0] is in the corresponding valid
area
VIN_ON
•
The TDC current is below or equal to the
level set by MFR_IOUT_LEVEL_L (49h),
bits[7:0]
Under these conditions, the ZCD adjusting
frequency is held since the SR’s ZCD is not
accurate under light-load conditions.
If the tON difference between neighboring PWM
periods is within ZCDLOOP_HYS (0Bh),
bits[10:8] for 256 PWM periods, the frequency is
stable unless the load changes. tON can be
locked if ZCDLOOP_LATCHTON_EN (0Ch),
bit[5] is high. The synchronized ZCD in the
MP2981 is delayed from SR current ZCD timing.
The
final
tON
can
be
fixed
by
VIN_OFF
VIN
Start
Copy MTP Delay
Start
Delay
VIN_UVLO
PWM
...
Figure 5: VIN UVLO
VIN UVLO is also enabled when both
DISABLE_ALL_PRO
(68h),
bit[0]
and
RST_VIN_PRO (68h), bit[4] are low. VIN UVLO
resets all shutdown protections.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
11
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
If VIN ramps up, EN turns on, and there is no off
the low-pass filter, and are then outputted on the
command, then the MPC100A-54-0000 restarts
IMON pin after a three-time buffer.
and resumes normal operation.
The ADC samples the IMON voltage (see Figure
If VIN exceeds VIN_OV_FLT_LIM (40h), then VIN
7).
Then
the
digital
part
calculates
OVP occurs and the chip shuts down. OVP does
IOUT_CAL_GAIN
(38h)
and
not occur when the MTP is being restored during
IOUT_CAL_OFFSET (39h), as well as
start-up. It is controlled by registers 68h, bits[5:4]
READ_IOUT (8Ch) from the ADC result (9Bh),
and 68h, bit[0].
which is compared to the output current limit
(register 6Ah) to determine whether an overVOUT Under-Voltage Protection (UVP) and
current (OC) condition has occurred.
Over-Voltage Protection (OVP)
If the thermal design current (TDC) remains high
Output OVP and UVP are designed to protect
for longer than the set time (6Ah), this protection
the output fault statuses. If VOUT exceeds the
shuts down the module.
VOUT_MAX value, the chip shuts down
immediately. Based on the mode set by the
ADC
VOUT_OVP_MAX_LATCH
bit,
the
part
responds by going into latch-off or hiccup mode.
CS1
1MΩ
x3
IMON
It can also take no action if OVP is disabled.
The OVP_MAX threshold (OVP1) has eight
options ranging between 1V and 1.7V, with
0.1V/step. The over-voltage threshold (OVP2)
has four tracking options: 110%, 120%, 130%,
and 140% of the reference voltage (VREF).
If VOUT drops quickly and falls below the
UVP_MIN threshold, the device shuts down after
a short delay time (6Dh, bits[5:0]) (see Figure 6).
The under-voltage threshold has four tracking
options: 90%, 80%, 70%, and 60% of the
reference voltage (VREF). Level 2 UVP (UVP2),
also called VOUT low protection, has four
thresholds: 0.3V, 0.4V, 0.5V, and 0.6V.
VOSEN
RCS1
CS2
RCS2
Figure 7: IMON Pin
Over-Current Protection (OCP) Spike
OCP is designed to limit the output current when
the load consumes more current than the circuit
can handle. The MP8500’s CS pin sources a
current that is proportional to IOUT (5µA/A), and
generates a voltage by connecting a resistor to
GND. The CS pins (CS1 and CS2) of both
phases are compared to the peak CS levels
(OCSPK_H and OCSPK_L) (see Figure 8).
OV1
3
DAC
OV1_LIMIT
OC_SPIKE_H
CS1
OV2
VREF
2
OCSPK_H_1
6Ch,
bits[15:8]
VOSEN
VREF
1MΩ
OV2_LIMIT
DAC
OCSPK_H_2
2
UV_LIMIT
UV
VOSEN
Figure 6: OVP1, OVP2, and UVP Protection
Circuits
Over-Current Protection (OCP) and Thermal
Design Current (TDC)
All parallel SR DrMOS currents of the same
phase flow together into their own CS resistor
(RCS). Two-phase CS voltages are added after
OC_SPIKE_L
CS2
OCSPK_L_1
6Ch,
bits[7:0]
DAC
OCSPK_L_2
Figure 8: OC Spike Comparators
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
12
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
If the current drops to the lower level, the tON
system enters the MTP fault state and waits for
accumulator decreases by the value of
the error to be cleared.
WEIGHT_OCSPK_L (32h) (see Figure 9). After
Communication Failure
dropping to a sufficient value, tON decreases by
A data transmission fault occurs when
5ns. The minimum tON value is TON_MIN (1Ch).
information is not properly transferred between
In each PWM cycle, the tON values for both
the devices. There are several data transmission
phases are the same.
faults:
OCSPK_L
tON
WEIGHT_
WEIGHT_
OCSPK_L OCSPK_L_INC
Figure 9: OCSPK_L
The two OC spikes cannot shut off the chip
directly.
When the OC conditions are removed, tON
gradually increases to the original value of
WEIGHT_OCSPK_H or WEIGHT_OCSPK_L.
The greater OC value has the higher priority.
The SR_PWM pins (PWM pins for the MP8500)
are designed to turn off later than the PWMP
pins (PWM signal for the primary edge) on the
MP2981 during an OC spike to reduce the SR
current flowing through the diodes. This is set by
register 08h, bits[15:12], and bits[6:4]. See the
CTRL_OC (08h) section on page 23 for more
details.
Over-Temperature Protection (OTP)
The SR temperature and controller die
temperature are both sensed by the ADC. These
values trigger different responses that are
independent from one another. However, the
device enters latch-off or hiccup mode if either
condition is triggered.
The MP8500 sends the temperature-sense
signal for the MP2981’s TEMP pin. If the
MP8500 triggers a CS fault and enters a
protection mode, it pulls the TEMP pin to 3.3V.
The MP2981 must have a half-divider on the
TEMP pin so that the MP2981 can send the
signal to the comparator and the ADC.
MTP Fault
If the data in the MTP is determined to be invalid
by the cyclic redundancy check (CRC), then the
•
•
•
•
•
•
Sending too little data
Reading too little data
Host sending too many bytes
Reading too many bytes
Improperly set read bit in the address byte
Unsupported command codes
PMBus/I2C Communication
The MPC1100A-54-0000 supports real-time
monitoring for the VR operation parameters and
status with PMBus/I2C.interface. Table 1 lists the
monitored parameters.
Table 1: PMBus/I2C Monitored Parameters
Parameter
VOUT
IOUT
Temperature
VIN
Die temperature
OVP
UVP
OCP
OTP
VIN UVLO
VIN OV
CML
PMBus/I2C
62.5mV/LSB
0.25A/LSB
1°C
0.125V/LSB
1°C
✓
✓
✓
✓
✓
✓
✓
PMBus/I2C Interface
To support multiple VR devices using the same
PMBus/I2C interface, the MFR_ADDR_PMBus
register or the ADDR pin can configure the
PMBus/I2C address.
The address is a 7-bit code. The 3MSB are set
by the register. The 4LSB bit address can either
be set by the register or by the ADDR voltage.
The 00h address is reserved as an all call
address, which can be set for a single chip.
The ADDR voltage is set by the voltage divider
from the VDD18 voltage.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
13
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Table 2 shows the resistor values for different
There are a total of five transmission structures,
2
PMBus/I C addresses when the 3MSB are set to
listed below:
3’b010.
1. Send command only
Table 2: Setting the PMBus/I2C Address (4LSB)
2. Write byte
PMBus/I2C
Setting
RTOP
RBOTTOM
3. Write word
Address
Point (V) (kΩ) 1%
(kΩ) 1%
4. Read byte
20h
0
0
5. Read word
21h
0.031
33.2
0.576
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
0.055
0.084
0.115
0.156
0.203
0.266
0.338
0.432
0.542
0.677
0.845
1.049
1.301
1.549
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
1.05
1.62
2.26
3.16
4.22
5.76
7.68
10.5
14.3
20.0
29.4
46.4
86.6
20.5
To read or write to the MPC1100A-54-0000
registers, the PMBus/I2C or I2C command must
be compliant with the corresponding register and
byte number.
The PMBus/I2C communication frequency can
support 1MHz.
Figure 10 shows the supported PMBus/I2C
transmission structure without packet error
checking (PEC).
Figure 11 shows the supported PMBus/I2C
transmission structure with PEC.
The PMBus/I2C or I2C commands and register
map of the MPC1100A-54-0000 is the same as
the MP2981. Refer to the MP2981 datasheet for
additional details.
1)
S
Slave Address
Wr
A
Command Code
A
2)
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
P
3)
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
Data Byte High
4)
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte
5)
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte Low
P
S = Start
Master to Slave
P = Stop
Slave to Master
A = Acknowledge (ACK)
Wr = Write (Bit Value = 0)
NA = Not Acknowledge (NACK)
Rd = Read (Bit Value = 1)
A
P
NA P
A
Data Byte High
NA P
Figure 10: Supported PMBus/I2C Transmission Structure without PEC
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
14
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
1)
S
Slave Address
Wr
A
Command Code
A
PEC Byte
A
2)
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
PEC Byte
A
3)
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
Data Byte High
A
4)
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte
A
PEC Byte
5)
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte Low
A
Data Byte High
P
P
PEC Byte
A
PEC Byte
S = Start
Master to Slave
P = Stop
Slave to Master
A = Acknowledge (ACK)
Wr = Write (Bit Value = 0)
NA = Not Acknowledge (NACK)
Rd = Read (Bit Value = 1)
P
NA P
A
NA P
Figure 11: Supported PMBus/I2C Transmission Structure with PEC
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
15
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PMBUS/I2C MEMORY PAGE 0 COMMANDS/REGISTERS
Command Code
0x00
0x01
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0b
0x0c
0x0e
0x0f
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x21
0x22
0x25
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x38
0x39
Command Name
PAGE
OPERATION
CLEAR_FAULTS
CTRL_PWM
MFR_ADC_HOLD_TIME
CTRL_VR
CTRL_MTP
CTRL_OC
LOW_POWER_SET_BIT
ZCD_TIME_SET
ZCD_LOOP_SET
SKIP_SR_PWM_SET
CTRL_PWM_BK
STORE_ALL
RESTORE_ALL
STORE_USER_ALL
RESTORE_USER_ALL
MFR_VOUT_SEL
MFR_IOUT_SEL
DEAD_TIME
TON_MIN
TON_MAX
TON_NORMAL
TON_MIN_LIM
MFR_REF_CONFIG
VOUT_TRIM
TRANSFORMER_RATIO
WEIGHT_ZCD
SR_PWM_SETA_PRIDRV
SS_SRNEG_SET
SR_PWM_SETB
MFR_SLOPE_SR
MFR_SLOPE_BLK
PRISETBLK_WEIGHT_SS
WEIGHT_2_1
WEIGHT_4_3
WEIGHT_OCSPK_L_N
WEIGHT_OCSPK_INC
MFR_VIN_DROP_SET
VIN_ON
VIN_OFF
IOUT_CAL_GAIN
IOUT_CAL_OFFSET
Type
R/W
R/W
Send
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Send
Send
Send
Send
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
Bytes
1
1
0
2
1
2
2
2
1
2
2
2
2
0
0
0
0
2
2
1
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
16
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PMBUS/I2C MEMORY PAGE 0 COMMANDS/REGISTERS (continued)
Command Code
0x3A
0x3B
0x40
0x42
0x43
0x44
0x45
0x46
0x49
0x4B
0x4C
0x50
0x51
0x52
0x53
0x5A
0x5B
0x5E
0x5F
0x60
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x80
0x81
0x82
Command Name
VIN_CAL_GAIN
VOUT_CAL_GAIN
VIN_OV_FLT_LIM
TEMP_GAIN_OFFSET
DIETEMP_GAIN_OFFSET
MFR_USER_PWD
MFR_MTP_WP
SKIPDRMOS_SR_ERARLI
MFR_IOUT_LEVEL
MFR_VCAL_I_MAX
DC_TRIM
MPS_CODE
PRODUCT_CODE
CONFIG_ID
CONFIG_REV
CALVO_LOW_TON_SS_L
TON_SS_H
POWER_GOOD_ON
POWER_GOOD_OFF
PROTECT_DELAY
PWRGD_DELAY
START_DELAY
OFF_DELAY
MFR_OTP_SET
MFR_DIE_OTP_SET
PMBUS/I2C_ADDR_SET
MFR_PROTECT_CFG
OVP_UVP_VID_SET
OCP_TDC_SET
OCP_SPIKE_TIMES_SET
OCP_SPIKE_LEVEL
UVP_MIN_SET
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
PROTECT_SIG_GRP
STATUS_TEMP
STATUS_CML
SYS_STATE_DBG
FINAL_PMBUS/I2C_ADDR
REG_LAST_FAULT_MTP
Type
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bytes
2
2
2
2
2
2
1
2
2
2
1
2
2
2
2
2
2
2
2
1
1
2
2
2
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
2
2
2
2
2
1
2
1
1
2
1
1
1
1
R
2
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
17
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PMBUS/I2C MEMORY PAGE 0 COMMANDS/REGISTERS (continued)
Command Code
Command Name
Type
Bytes
0x88
0x8B
0x8C
0x8D
0x8E
0x90
0x96
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xF1
0xF2
0xF3
0xF4
READ_VIN
READ_VOUT
READ_IOUT
READ_TEMP
READ_DIE_TEMP
USER_KEY_INPUT
READ_POUT
VIN_SENSE
VOUT_SENSE
IOUT_SENSE
TEMP_SENSE
DIE_TEMP_SENSE
TON_PWMP
TON_SR_PWM
CLR_LAST_FAULT_WMTP
READ_LAST_FAULT_TRIG
CLEAR_STORE_FAULTS
CLEAR_MTP_FAULTS
R
R
R
R
R
W
R
R
R
R
R
R
R
R
Send
Send
Send
Send
2
2
2
1
1
2
2
2
2
2
2
2
2
2
0
0
0
0
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
18
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PAGE 0 REGISTER MAP
PAGE (00h)
The PAGE command configures, controls, and monitors the device through only one physical address to
support normal operation, testing mode, and debugging mode.
Command
Format
Bit
Access
Function
7
R/W
6
R/W
PAGE
Unsigned binary
4
3
R/W
R/W
5
R/W
2
R/W
1
R/W
PAGE
Bits
Bit Name
Description
7:2
RESERVED
Reserved. Bits[7:2] must set to 0 when changing bits[1:0].
1:0
0
R/W
2’b00: Page 0. Normal and trim registers (read/write registers) can be stored in
the MTP
2’b01: Page 1. Unused
2’b10: Page 2. Each PMBus/I2C command (not including (00h)) directly
reads/writes to the MTP cells
2’b11: Page 3. Debugging/testing registers. Not stored in the MTP
PAGE
Users should only use Page 0 to avoid unintentionally entering test mode.
OPERATION (01h)
The OPERATION command turns the output on or off by working with the EN pin. The MPC1100A-540000 remains in the commanded operating mode until another different OPERATION command is sent,
or the state of EN changes.
Command
Format
Bit
Access
Function
Bits
7
R/W
6
R/W
OPERATION
Unsigned binary
4
3
R/W
R/W
5
R/W
2
R/W
1
R/W
Bit Name
Description
7
OPERATION
1’b1: Turn on
1’b0: Turn off
6:0
RESERVED
Reserved. R/W bits are available, but do not change the device.
0
R/W
CLEAR_FAULTS (03h)
The CLEAR_FAULTS command clears any fault bit in the following status registers: STATUS_WORD
(79h), STATUS_VOUT (7Ah), STATUS_IOUT (7Bh), STATUS_TEMP (7Dh), and STATUS_CML (7Eh).
This command is write-only. There is no data byte for this command.
CTRL_PWM (04h)
The CTRL_PWM command controls PWM operation. The positive and negative edges of the SR_PWM
pins (SR_PWMs) can be adjusted using the PWMP pins. The SR_PWMs can be made to turn off earlier
or later than the time set by the PWMP pins.
Command
CTRL_PWM
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
19
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
15
Bit Name
Description
RESERVED
Reserved. R/W bits are available, but do not change the device.
Enables setting the MP2981’s SKIP_EN pin high during soft start.
14
SKIP_SS_EN
13
VOUT_SKIP_EN
12
CLOSE_LOOP_EN
11
ZCD_LOOP_EN
1’b1: Enabled. The SKIP_EN pin is pulled high during soft start
1’b0: Disabled. The SKIP_EN pin is pulled low during soft start
Enables VOUT skipping. Determines what happens after VOUT ramps above
VOUT_SKIP_H (19h), bits[3:2], and before VOUT ramps below VOUT_SKIP_L
(19h), bits[1:0].
1’b1: Shut down both SR_PWM pins during the dead time and after soft start. If
04h, bit[10] = 0, the primary PWMs also shut off
1’b0: No PWM shuts off
Enables the primary closed loop.
1’b1: Enabled
1’b0: Disabled
Enables the primary zero-current detection (ZCD) loop.
10
9
8:7
VOUT_SKIP_PWMP_EN
SKIPSR_VIN_DROP_EN
RESERVED
1’b1: Enabled
1’b0: Disabled
Determines how the part responds when VOUT skipping is enabled and VOUT
exceeds its limit.
1’b1: PWMP remains on when VOUT exceeds its limit during skip mode
1’b0: PWMP turns off when VOUT exceeds its limit during skip mode
Shuts off SR_PWM if the chip detects that VIN is dropping quickly, or VOSEN
exceeds the VIN ADC value.
1’b1: Enabled
1’b0: Disabled
Reserved. R/W bits are available, but do not change the device.
Adjusts whether the SR_PWMs turn on/off before or after the PWMP pins.
6
5
SR_ADJ_NORMAL_EN
SR_NEG_ADJ_SS_EN
1’b1: Enabled. If 0Fh, bit[15] and 04h, bits[4:1] are set to 1’b1, then this bit should
be set to 1’b1
1’b0: Disabled. If 0Fh, bit[15] and 04h, bits[4:1] are set to 1’b0, then this bit should
be set to 1’b0
Shuts off SR_PWM after or before PWMP during soft start, according to tON. This
bit is related to registers 5Ah, 5Bh, and 2Bh.
1’b1: Enabled
1’b0: Disabled
Shuts off SR_PWM a fixed time before PWMP. Related to register 2Ah.
4
SR_FIXED_DEC_EN
1’b1: Enabled
1’b0: Disabled
Shuts off SR_PWM a fixed time after PWMP. Related to register 2Ah.
3
SR_FIXED_EXT_EN
1’b1: Enabled
1’b0: Disabled
Shuts off SR_PWM a fixed time before the next PWMP. Related to register 2Ch.
2
SR_NEG_ADJ_EN
1
SR_POS_DEC_EN
1’b1: Enabled
1’b0: Disabled
Turns on SR_PWM after PWMP. Related to register 2Ch.
1’b1: Enabled
1’b0: Disabled
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
20
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
0
Makes SR_PWM equal to PWMP if no other adjusting function is enabled. Only
enabled when the part is not in soft start, and 04h, bit[6] = 0.
SR_EN
1’b1: SR_PWM = PWMP
1’b0: SR_PWM = 0
MFR_ADC_HOLD_TIME (05h)
The MFR_ADC_HOLD_TIME command sets the waiting time between finishing one channel sampling
and starting the next channel sampling.
Command
Format
Bit
Access
Function
Bits
7
6:0
7
R
X
6
R/W
MFR_ADC_HOLD_TIME
Unsigned binary
4
3
2
R/W
R/W
R/W
MFR_ADC_HOLD_TIME
5
R/W
1
R/W
0
R/W
Bit Name
Description
RESERVED
Not defined. Read-only.
MFR_ADC_HOLD_TIME
The time after one channel finishes, and before the next channel starts.
100ns/LSB.
CTRL_VR (06h)
The CTRL_VR command configures certain chip functions, excluding pulse-width modulation (PWM).
Command
CTRL_VR
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15
Bit Name
Description
RESERVED
Reserved. R/W bits are available, but do not change the device.
Controls the analog output to enable bandgap (BG) chop.
14
CHOP_BG
1’b1: Enabled
1’b0: Disabled
Selects the PSYS current rate by sending different READ_POUT (96h) data.
1’b1: 2 with LSB, send READ_POUT (96h), bits[10:1] to the 10-bit PSYS digitalto-analog converter (DAC)
1’b0: 1 with LSB, send READ_POUT (96h), bits[9:0] to the DAC
13
PSYS_SEL_2W
12
DC_CAL_EN
11
DIE_TEMP_RATE_NEG
1’b1: Negative
1’b0: Positive
RESERVED
Reserved. R/W bits are available, but do not change the device.
PMBUS/I2C_ADDR_
KEEP_SAMP
1’b1: The ADC constantly samples the ADDRP pin
1’b0: The ADC samples ADDRP only seven times after the MTP address reaches
8’h20
PMBUS/I2C_FILTER_SET
PMBus/I2C filter on the digital side. 10ns/LSB.
Enables the DC loop.
1’b1: Enabled
1’b0: Disabled
Selects the die temperature’s voltage vs. temperature (V-T) rate.
10:9
8
7:4
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
21
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
1’b1: Wait until VIN is ready (READ_VIN > VIN_ON) before ramping VREF and
generating PWMs
1’b0: Do not wait until VIN is ready (READ_VIN > VIN_ON) before ramping VREF
and generating PWMs
3
WAIT_VIN_START
2
SEL_PWRGD_1REF_
0TON
1
MFR_ONOFFDLY_CLK_
1L0S
Selects VREF ramping or tON increasing to act as the PG reference.
1’b1: VREF
1’b0: tON
Selects the counting clock for START_DELAY and OFF_DELAY during start-up
and shutdown.
1’b1: 20kHz
1’b0: 50kHz
Determines the VOUT threshold before increasing tON during soft start.
0
KEEP_TON_MIN_LMT_SS
1’b1: tON stays at the TON_MIN_LIM (1Fh) value and does not increase until VOUT
exceeds VOUT UVP_MIN (19h)
1’b0: tON does not stay at the TON_MIN_LIM (1Fh) value, and begins increasing
before VOUT exceeds VOUT UVP_MIN (19h)
CTRL_MTP (07h)
The CTRL_MTP command sets the MTP parameters. It is recommended to use the vendor’s preset
configurations.
Command
CTRL_MTP
Format
Bit
Access
Function
Bits
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
Bit Name
Description
Enables cyclic redundancy check (CRC) for the MTP user.
15
CRC_FAULT_USER_EN
14
CRC_FAULT_TRIM_EN
1’b1: Enabled
1’b0: Disabled
Enables CRC for the MTP trim.
13
12
CRC_FAULT_TOT_EN
MTP_FAULT_BLOCK_
EN
1’b1: Enabled
1’b0: Disabled
Enables CRC for the total MTP. Do not set this bit to 1 when using 17h
(STORE_USER_ALL) to write to the MTP.
1’b1: Enabled
1’b0: Disabled
Determines whether an MTP fault prevents start-up, including the signature fault
and CRC fault.
1’b1: Enabled. If an MTP fault occurs, the chip enters the MTP fault state, and a
CLEAR_MTP_FAULTS (F4h) command must be sent to exit the state
1’b0: Disabled. The chip starts up if an MTP fault occurs
Prevents start-up if the data read from the MTP LAST_FAULT_ADDR is not 0.
11
10:6
LAST_FAULT_BLOCK_
EN
1’b1: Enabled. If the last fault exists, the chip must receive a
CLEAR_STORE_FAULTS (F3h) command to start up
1’b0: Disabled. The chip starts up, even if the last fault exists
RESERVED
Reserved. R/W bits are available, but do not change the device.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
22
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
5
CAL_FAULT_CRC_DIS
1’b1: Do not include MTP_FAULT_RECORD_ADDR (the 2 bytes in the MTP that
store protection faults, such as OVP) when calculating CRC_TOT
1’b0: Include MTP_FAULT_RECORD_ADDR when calculating CRC_TOT
4
NO_FAULT_STORE
1’b1: Store 00h data to MTP_FAULT_RECORD_ADDR
1’b0: Store the value of MEMORY_ADDR (7Ah) to
MTP_FAULT_RECORD_ADDR when storing is not triggered by a fault
3
FAULT_SINGLE_EN
1’b1: Only store the 2-byte MTP_FAULT_RECORD_ADDR
1’b0: Store the whole third section of the MTP when storing FAULT_RECORD
2
RESERVED
Reserved. R/W bits are available, but do not change the device.
1
PROTECT_FAULT_
RECORD_EN
0
Enables FAULT_RECORD.
1’b1: Enabled
1’b0: Disabled
MFR_MTP_COPY_EN
Reads the MTP (16h or 18h or F6h) when the device outputs power; ineffective
for the READ_LAST_FAULT command (F2h) or the reading MTP commands (16h
or 18h or F6h) on Page 2.
1’b1: Enabled
1’b0: Disabled
CTRL_OC (08h)
The CTRL_OC command configures the over-current (OC) spike function. The PWM tON is reduced when
an OC spike occurs, and recovers after the OC spike condition is removed (see Figure 12). This
protection cannot directly shut down the chip.
PWMP1
Valid Area
TON_MIN_
OCSPK_H
PWMP2
TON_MIN_
OCSPK_H
Valid Area
Figure 12: OCSPK_H
Command
CTRL_OC
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:12
SR_DLY_OCSPK
Sets the time lengths of the SR_PWM pins’ wait period before turning off after the
PWMP pins when an over-current (OC) spike occurs. If any bit between bits[6:4]
of this command is high, there must be a 2Ah, bits[3:0]
Valid
Area
Figure 14: Valid Skip Area
Command
SKIP_SR_PWM_SET
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
SEL
Bit Name
SKIP_SR_PWM_BLKN_SEL
SKIP_SR_PWM_BLKN
Description
Turns off SR_PWM when CS is low.
15
14:12
11
SKIP_SR_PWM_EN
1’b1: Enabled
1’b0: Disabled
SKIP_SR_PWM_NUM
Sets the off time for the SR_PWM periods. After the skip delay, the
SKIP_SR_PWM_NUM and SR_PWM periods (phase 1 and 2) are skipped.
RESERVED
Reserved. R/W bits are available, but do not change the device.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
26
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
10
9:4
SKIP_SR_PWM_BLKN_
SEL
SKIP_SR_PWM_BLKP
Selects the valid area of SKIP_SR_PWM before or after the PWM1 pull-down
pulse.
1’b1: The valid area is before the PWM1 pull-down pulse
1’b0: The valid area is after the PWM1 pull-down pulse
Sets the blanking time of the valid area after a PWM1 pull-up pulse. The blanking
time can be estimated with the equation below:
Skip blank time = (SKIP_SR_PWM_BLKP x 10ns + 5ns)
3:0
SKIP_SR_PWM_BLKN
Sets the blanking time for the valid area border to the PWM1 pull-down pulse. If
SKIP_SR_PWM_BLKN_SEL = 1, the valid area border ahead of the PWM1 pulldown pulse is SKIP_SR_PWM_BLKN x 10ns. If SKIP_SR_PWM_BLKN_SEL = 0,
the valid area border after the PWM1 pull-down pulse changes is based on the
following scenarios:
• SKIP_SR_PWM_BLKN = 0: 5ns
• 0 < SKIP_SR_PWM_BLKN < 2Ah, bits[3:0]: (2Ah, bits[3:0] + 2 x
SKIP_SR_PWM_BLKN) x 5ns
• SKIP_SR_PWM_BLKN > 2Ah, bits[3:0]: (2Ah, bits[3:0] + 2) x 5ns
CTRL_PWM_BK (0Fh)
The CTRL_PWM_BK command sets the PWM working options.
Command
CTRL_PWM_BK
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
TON_ZCDLOOP_DEC
Bit Name
Description
Turns on SR_PWM before PWMP. Related to 46h.
15
SR_POS_EARLIERER
_EN
14
SEL_ZCD_NEG
1’b1: ZCD negative edge effective
1’b0: ZCD positive edge effective
13
CALVOUT_LOW_LMT_
TONL
1’b1: Disable the function that makes the SR_PWMs turn off after the PWMP pins
when READ_VOUT, bits[8:1] exceeds CALVOUT_LOW_LVL, bits[5:0]
1’b0: Enable the SR_PWMs to always turn off after the PWMPs
12
RM_VOUTLOW_SS_
TONLOW
1’b1: Disable the turn off later function during the VOUT low stage. The VOUT low area
(VOSEN < level, tON keeps TON_MIN_LIM) during soft start is not included in TONLL
or TONL
1’b0: Enable the SR_PWM pins to turn off after the PWMP pins
11:8
TON_ZCDLOOP_DEC
1’b1: Enabled
1’b0: Disabled
If ZCDLOOP_LATCHTON_EN is enabled, tON is fixed to the tON value at the 256th
cycle. 5ns/LSB. tON can be calculated with the following equation:
tON - TON_ZCDLOOP_DEC x 5ns
7
RESERVED
Reserved. R/W bits are available, but do not change the device.
Enables ZCD1.
6
ZCD1_EN
5
ZCD2_EN
1’b1: Enabled
1’b0: Disabled
Enables ZCD2.
1’b1: Enabled
1’b0: Disabled
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
27
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
4
3:0
SR_ZCD_SEPARATE
1’b1: ZCD2 = ZCD2 pin
1’b0: ZCD2 = ZCD1 pin
RESERVED
Reserved. R/W bits are available, but do not change the device.
STORE_ALL (15h)
The STORE_ALL command instructs the PMBus/I2C slave device to copy the R/W contents from the
Page 0 registers of the operating memory to the matching locations in the MTP when the command is
sent for Page 0, Page 1, or Page 3 (not for Page 2).
This command can be used while the device is outputting power.
This command is write-only. There is no data byte for this command. Other unused MTP addresses are
written to 0.
RESTORE_ALL (16h)
The RESTORE_ALL command instructs the PMBus/I2C slave device to copy the contents of the MTP to
the matching locations in the operating memory. The values in the operating memory are overwritten by
the value retrieved from the MTP. Any items that do not have matching locations in the operating memory
are ignored.
This command cannot be used while the device is outputting power, unless MFR_MTP_COPY_EN
(register 07h, bit[0] on Page 0) is set to 1.
This command is write-only. There is no data byte for this command.
STORE_USER_ALL (17h)
The STORE_USER_ALL command instructs the PMBus/I2C slave device to copy the read and write
Page 0 registers of the operating memory (except the trim registers) to the matching locations in the MTP
(inside MTP address 8’h00 to 8’hDF) when the command is sent for Page 0, Page 1, or Page 3 (not for
Page 2).
This command can be used while the device is outputting power.
This command is write-only. There is no data byte for this command. Other unused MTP addresses inside
the MTP addresses 8’h00 to 8’hDF are written to 0.
RESTORE_USER_ALL (18h)
The RESTORE_USER_ALL command instructs the PMBus/I2C slave device to copy the R/W contents
of the MTP addresses 8’h00 to 8’hDF to the matching locations in the operating memory. The values in
the operating memory are overwritten by the value retrieved from the MTP. Any items that do not have
matching locations in the operating memory are ignored.
This command cannot be used while the device is outputting power, unless MFR_MTP_COPY_EN
(register 07h, bit[0] on Page 0) is set to 1.
This command is write-only. There is no data byte for this command.
MFR_VOUT_SEL (19h)
The MFR_VOUT_SEL command configures VOUT_OVP_MAX, OVP_VID, UVP_VID, UVP_MIN, and
VOUT_SKIP, then compares these values to the VOSEN pin.
Command
MFR_VOUT_SEL
Format
Bit
Access
Function
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OVP_MAX
OVP_VID
UVP_VID
UVP_MIN
SKIP_H
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
SKIP_L
28
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
15:13
RESERVED
Reserved. R/W bits are available, but do not change the device.
12:10
OVP_MAX_LVL_SEL
9:8
OVP_VID_LVL_SEL
7:6
UVP_VID_LVL_SEL
5:4
UVP_MIN_LVL_SEL
3:2
VOUT_SKIP_H_SEL
1:0
VOUT_SKIP_L_SEL
See the tables below for more information.
The VREF level in OVP_VID, UVP_VID, and VOUT_SKIP is the VOUT reference
DAC output (e.g. 21h, bits[7:0] x 6.25mV).
OVP_MAX_LVL_SEL
OVP_MAX Level (V)
0
1
Level Select
OVP_VID_LVL_SEL,
OVP_VID level (V)
UVP_VID_LVL_SEL,
UVP_VID level (V)
UVP_MIN_LVL_SEL,
UVP_MIN level (V)
VOUT_SKIP_H_SEL,
VOUT_SKIP_H level (V)
VOUT_SKIP_L_SEL,
VOUT_SKIP_L level (V)
1
1.1
2
1.2
3
1.3
4
1.4
5
1.5
6
1.6
7
1.7
0
1
2
3
140% of VREF
130% of VREF
120% of VREF
110% of VREF
90% of VREF
80% of VREF
70% of VREF
60% of VREF
0.3
0.4
0.5
0.6
VREF + 50mV
VREF + 40mV
VREF + 30mV
VREF + 20mV
VREF + 40mV
VREF + 30mV
VREF + 20mV
VREF + 10mV
MFR_IOUT_SEL (1Ah)
The MFR_IOUT_SEL command configures the light-load levels (CMP_CS1_EXITSKIP and
CMP_CS1_ENTERFREQ), which are compared to the CS1 pin. After CS1 exceeds
CMP_CS1_EXITSKIP, the DrMOS stops skipping (SKIP_DRMOS_EN). When CS1 drops below
CMP_CS1_ENTERFREQ, the SR_PWMs skip after a delay (SKIP_SR_PWM_EN) for a configurable
number of PWM periods.
Command
MFR_IOUT_SEL
Format
Unsigned binary
Bit
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:11
RESERVED
Reserved. R/W bits are available, but do not change the device.
10:9
CMP_CS1_EXITSKIP_
GAIN
Selects the current level’s analog buffer gain when exiting skip mode.
8
7:4
3:0
CMP_CS1_ENTERFREQ
_GAIN
CMP_CS1_EXITSKIP_
SEL
CMP_CS1_ENTERFREQ
_SEL
2’b0x: Gain = 1
2’b10: Gain = 2
2’b11: Gain = 4
Selects the current level’s analog buffer gain when entering skip mode.
1’b1: Gain = 2
1’b0: Gain = 1
The final level is determined by bits[7:4], multiplied by the buffer gain.
The final level is determined by bits[3:0], multiplied by the buffer gain.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
29
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Table 3 lists the values for CMP_CS1_EXITSKIP. Table 4 lists the values for CMP_CS1_ENTER.
Table 3: CMP_CS1_EXITSKIP Values
CMP_CS1_
EXITSKIP (V)
Table 4: CMP_CS1_ENTER Values
CMP_CS1_
ENTERFREQ_GAIN,
CMP_CS1_
Bit[8]
ENTERFREQ (V)
0
1
CMP_CS1_
ENTERFREQ_SEL,
Mul 1
Mul 2
Bits[3:0]
CMP_CS1_EXITSKIP_
GAIN, Bits[10:9]
0 or 1
2
3
CMP_CS1_
EXITSKIP_SEL,
Bits[3:0]
Mul 1
Mul 2
Mul 4
0
0.08
0.160
0.320
0
0.03
0.06
1
0.085
0.170
0.340
1
0.035
0.070
2
0.09
0.180
0.360
2
0.04
0.080
3
0.095
0.190
0.380
3
0.045
0.090
4
0.1
0.200
0.400
4
0.05
0.100
5
0.105
0.210
0.420
5
0.055
0.110
6
0.11
0.220
0.440
6
0.06
0.120
7
0.115
0.230
0.460
7
0.065
0.130
8
0.12
0.240
0.480
8
0.07
0.140
9
0.125
0.250
0.500
9
0.075
0.150
10
0.13
0.260
0.520
10
0.08
0.160
11
0.135
0.270
0.540
11
0.085
0.170
12
0.14
0.280
0.560
12
0.09
0.180
13
0.145
0.290
0.580
13
0.095
0.190
14
0.15
0.300
0.600
14
0.1
0.200
15
0.155
0.310
0.620
15
0.105
0.21
DEAD_TIME (1Bh)
The DEAD_TIME command sets the normal working dead time. During soft start, tON begins at
TON_MIN_LIM (1Fh), bits[13:8], and the dead time is (TON_MIN (1Ch) + DEAD_TIME (1Bh) TON_MIN_LIM). After VOUT reaches UVP_MIN and the KEEP_TON_MIN_LMT_SS bit (06h, bit[0]) is set
high, tON starts increasing. At the same time, the dead time decreases but remains at the same frequency
(see Figure 15 on page 31).
If KEEP_TON_MIN_LMT_SS is not enabled, then tON and the dead time start immediately. When tON
reaches TON_MIN, the dead time is DEAD_TIME (1Bh). The dead time remains at this value, tON keeps
ramping until tON equals TON_NORMAL (1Eh), and soft start completes. For more details on the tON
increasing speed, see the PRISETBLK_WEIGHT_SS section on page 36.
Command
Format
Bit
Access
Function
Bits
7
R
X
6
R/W
5
R/W
DEAD_TIME
Unsigned binary
4
3
R/W
R/W
DEAD_TIME
2
R/W
Bit Name
Description
7
RESERVED
Not defined. Read-only.
6:0
DEAD_TIME
The real normal working dead time = ([6:0] + 1) x 5ns.
1
R/W
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
0
R/W
30
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Dead Time
TON_MIN + DEAD_TIME (1Bh) TON_MIN_LIM
DEAD_TIME (1Bh)
Time
tON
TON_NORMAL
Frequency
Decreasing
Fixed Frequency
TON_MIN
TON_MIN_LIM
VOUT Reaches
UVP_MINl
Time
Figure 15: Soft Start tON and Dead Time
TON_MIN (1Ch)
The TON_MIN command sets the minimum tON in the zero-current detection (ZCD) loop and primary
closed loop. It is also the end of soft start’s first stage. For more details, see the DEAD_TIME (1Bh)
section on page 30.
Command
TON_MIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
Bits
15:10
9:0
TON_MIN
Bit Name
Description
RESERVED
Not defined. Read-only.
TON_MIN
5ns/LSB.
TON_MAX (1Dh)
The TON_MAX command sets the maximum tON. In the zero-current detection (ZCD) loop and primary
closed loop, tON is adjusted according to ZCD and the set signals. The adjusting process is limited
between TON_MIN (1Ch) and TON_MAX (1Dh).
Command
TON_MAX
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
Bits
15:10
9:0
Bit Name
Description
RESERVED
Not defined. Read-only.
TON_MAX
5ns/LSB.
TON_MAX
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
31
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
TON_NORMAL (1Eh)
The TON_NORMAL command sets the normal working tON. It is also the final tON for soft start, and the
tON for open-loop operation.
Command
TON_NORMAL
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
Bits
15:10
9:0
TON_NORMAL
Bit Name
Description
RESERVED
Not defined. Read-only.
TON_NORMAL
The real tON is (TON_NORMAL + 1) x 5ns.
TON_MIN_LIM (1Fh)
The TON_MIN_LIM command sets the starting tON for PWM during soft start.
Command
TON_MIN_LIM
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
TON_MIN_LIM
Bit Name
Description
15:14
RESERVED
Reserved. R/W bits are available, but do not change the device.
13:8
TON_MIN_LIM
The beginning of the soft-start pulse width. Only used during soft start. The pulse
width can be calculated with the following equation:
Pulse width = (TON_MIN_LIM + 1) x 5ns
7:0
RESERVED
Reserved. R/W bits are available, but do not change the device.
MFR_REF_SR_CTRL (21h)
The MFR_REF_SR_CTRL command configures the VOUT DAC input (also called VID or VREF) and
controls its slew rate. VREF works as a reference in primary closed-loop operation, and is the base
reference for OVP_VID and UVP_VID.
Command
MFR_REF_SR_CTRL
Format
Bit
Access
Unsigned binary
15
14
13
R/W
R/W
R/W
Function
Bits
12
11
10
9
8
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VID_COUNTING_STEP
Bit Name
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
MFR_REF_SET
Description
Selects the clock counting rate.
15
CLK_COUNTING_SEL
14:8
VID_COUNTING_STEP
Every VID_COUNTING_STEP x (1µs or 0.1µs) time period, VID increases or
decreases by 6.25mV.
7:0
MFR_REF_SET
VID (V) = MFR_REF_SET x 6.25mV. 6.25mv/LSB.
1’b1: 1µs
1’b0: 0.1µs
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
32
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
VOUT_TRIM (22h)
The VOUT_TRIM command sets the value to compensate the system error between VREF and VOSEN.
The error used for the DC loop is (21h, bits[7:0] x 4 + VOUT_TRIM - VOUT_SENSE). VOUT_SENSE is
the 10-bit ADC sampling result of VOSEN.
Command
Format
Bit
Access
Function
7
R
X
6
R
X
VOUT_TRIM
Unsigned binary
4
3
R
R/W
X
5
R
X
Bits
Bit Name
Description
7:4
RESERVED
Not defined. Read-only.
3:0
VOUT_TRIM
1.5625mV/LSB.
2
1
R/W
R/W
VOUT_TRIM
0
R/W
TRANSFORMER_RATIO (25h)
The TRANSFORMER_RATIO command records the transformer ratio of the specific application.
Command
TRANSFORMER_RATIO
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:4
RESERVED
Reserved. R/W bits are available, but do not change the device.
3:0
TRANSFORMER_RATIO
Records the transformer ratio.
Table 5 lists the values for 25h, bits[3:0], as well as their respective transformer ratios.
Table 5: Transformer Ratios
25h, Bits[3:0]
Transformer
Ratio
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
1
1/2
1/3
1/4
1/5
1/6
1/7
1/8
1/9
1/10
1/11
1/12
1/13
1/14
1/15
WEIGHT_ZCD (29h)
The WEIGHT_ZCD command defines the positive and negative weights used when adjusting the
frequency set by zero-current detection (ZCD) functionality. Assume tON changes from INITIAL_TON (ns)
to FINAL_TON (ns), and the dead time remains the same (DEAD_TIME (ns)). The adjusting time can be
calculated with Equation (2):
TIME(ns) =
256 5
n −1
n (TON_INIT _D + DT _D + 2 +
)(ns)
WEIGHT _ ABS
2
(2)
Where all variables are unitless. The variables are defined below:
• TON_INIT_D = INITIAL_TON (ns) / 5ns - 1
• TON_FIN_D = FINAL_TON (ns) / 5ns - 1
• n = TON_FIN_D - TON_INIT_D + 1
• DT = DEAD_TIME (ns) / 5ns - 1
• WEIGHT_ABS is the absolute value of WEIGHTN_ZCD or WEIGHTP_ZCD
The time above does not include the 256 PWM periods during which tON stays within the tON hysteresis
(0Bh, bits[10:8]) for tON latch (0Ch, bit[5]).
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
33
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Command
WEIGHT_ZCD
Format
Bit
Access
Direct
15
14
13
R/W
R/W
R/W
Function
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEIGHTN_ZCD
WEIGHTP_ZCD
Bits
Bit Name
Description
15:8
WEIGHTN_ZCD
When zero-current detection (ZCD) occurs in a valid ZCD time (0Bh), tON
decreases by this value. Cannot be set to 0 or 0xFF.
RESERVED
Reserved. R/W bits are available, but do not change the device.
WEIGHTP_ZCD
When ZCD does not occur in a valid ZCD time (0Bh), tON increases by this value.
Cannot be set to 0 or 0x01.
7
6:0
SR_PWM_SETA_PRIDRV (2Ah)
The SR_PWM_SETA_PRIDRV command controls the SR_PWM setting and sets the simulated primary
driver chip delay. For more information, see the CTRL_PWM section on page 19.
Command
SR_PWM_SETA_PRIDRV
Format
Bit
Access
Function
Bits
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM_NEG_FIXED
PRI_DRV_DLY_SIM
Bit Name
Description
15:12
PWM_NEG_FIXED
If SR_FIXED_DEC_EN = 1 and SR_FIXED_EXT_EN = 0, SR_PWM shuts off
before the PWMP pin of its own phase, and the change is (PWM_NEG_FIXED) x
5ns. If SR_FIXED_EXT_EN = 1 and SR_FIXED_DEC_EN = 0 or 1, SR_PWM
shuts off after PWMP, and the change is (PWM_NEG_FIXED + 1) x 5ns.
11:6
RESERVED
Reserved. R/W bits are available, but do not change the device.
5
RM_PWMDEC_
REDUND
Digital internal use.
4
PWM_EXT_DN_CFG
Digital internal use.
PRI_DRV_DLY_SIM
Delays the internal PWMPs from the output PWMPs. The time length simulates the
primary-drive chip delay. The delay time can be calculated with the following
equation:
Delay time = (bits[3:0] + 1) x 5ns
3:0
SS_SRNEG_SET (2Bh)
The SS_SRNEG_SET command sets the time length that determines when the SR_PWM pin turns off
(before or after PWMP during soft start). This register works with 5Ah and 5Bh. For more information,
see the CTRL_PWM section on page 19.
Command
SS_SRNEG_SET
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15:12
Bit Name
Description
SRNEG_SS_TONHH_
DEC
If tON ≥ TON_LVL_SS_HH during soft start, then turn off SR_PWM before PWMP
by SRNEG_SS_TONHH_DEC x 5ns.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
34
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
11:8
SRNEG_SS_TONH_
DEC
If TON_LVL_SS_HH > tON ≥ TON_LVL_SS_H, then turn off SR_PWM before
PWMP by SRNEG_SS_TONH_DEC x 5ns.
7:4
SRNEG_SS_TONL_
DLY
If TON_LVL_SS_L > tON ≥ TON_LVL_SS_LL during soft start, then turn off
SR_PWM after PWMP by (SRNEG_SS_TONL_DLY + 1) x 5ns.
3:0
SRNEG_SS_TONLL_
DLY
If tON < TON_LVL_SS_LL, then turn
(SR_NEG_SS_TONLL_DLY + 1) x 5ns.
off
SR_PWM
after
PWMP
by
SR_PWM_SETB (2Ch)
The SR_PWM_SETB command controls the SR_PWM pins’ settings. For more information, see the
CTRL_PWM section on page 19.
Command
SR_PWM_SETB
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
SR_PWM_NEG_ADJ
SR_PWM_POS_DECH
SR_PWM_POS_DECL
Bit Name
Description
15:13
RESERVED
Reserved. R/W bits are available, but do not change the device
12:8
SR_PWM_NEG_ADJ
SR_PWM shuts off before or after PWMP. The time length between SR_PWM’s
negative edge and the other phase’s PWMP positive edge is
(SR_PWM_NEG_ADJ + 1) x 5ns.
7:4
SR_PWM_POS_DECH
When SR_POS_DEC_EN = 1 under conditions other than light load, SR_PWM
turns on after PWMP by (SR_PWM_POS_DECH + 1) x 5ns (the MP2981’s
SKIP_EN pin is low).
3:0
SR_PWM_POS_DECL
When SR_POS_DEC_EN = 1 under light-load conditions, SR_PWM turns on after
PWMP by (SR_PWM_POS_DECL + 1) x 5ns (the the MP2981’s SKIP_EN pin is
high).
MFR_SLOPE_SR (2Dh)
The MFR_SLOPE_SR command defines the capacitor’s slope charge number and current.
Command
MFR_SLOPE_SR
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
X
SLOPE_CURRENT
Bits
Bit Name
Description
15:9
RESERVED
Not defined. Read-only.
8:6
SLOPE_CAP_SET
The parallel capacitor number is (8 - SLOPE_CAP_SET), and each capacitor is 3.7pF.
5:0
SLOPE_CURRENT
Slope charge current. 250nA/LSB.
MFR_SLOPE_BLK (2Eh)
The MFR_SLOPE_BLK command defines the slope discharge time.
Command
MFR_SLOPE_BLK
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
MFR_SLOPE_BLK
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
35
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
15:14
RESERVED
Not defined. Read-only.
13:8
MFR_SLOPE_BLK
Discharge slope during dead time, excluding the first 5ns of dead time and the first
(MFR_SLOPE_BLK + 1) x 5ns of the PWMP pulses.
7:0
RESERVED
Reserved. R/W bits are available, but do not change the device.
PRISETBLK_WEIGHT_SS (2Fh)
The PRISETBLK_WEIGHT_SS command sets the blanking time of the primary set loop (primary closed
loop). It is a time length at the beginning of the PWMP period. During this time, tON does not adjust based
on the set loop. This command also configures how quickly tON increases during soft start. There are two
tON increasing stages: fixed frequency and decreasing frequency. The first-stage cost time (tSS1) can be
calculated with Equation (3):
t SS1 =
(TON_MIN + DEAD _ TIME + 1) 256 5ns
( TON_MIN − TON_MIN_LIM)
WEIGHT _ SS
(3)
Where DEAD_TIME = 1Bh, bits[6:0]; TON_MIN_LIM = 1Fh, bits[13:8]; and WEIGHT_SS = 2Fh, bits[6:0].
The second-stage cost time (tSS2) can be estimated with Equation (4):
t SS2 =
un +
(n − 1) n
+ (DEAD _ TIME + 1) n
2
256 5ns
WEIGHT _ SS
(4)
Where u = TON_MIN = 1Ch, bits[9:0]; n = TON_NORMAL - TON_MIN; and TON_NORMAL = 1Eh,
bits[9:0].
Command
PRISETBLK_WEIGHT_SS
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
Bits
BLK_TIME
Bit Name
Description
15:14
RESERVED
Not defined. Read-only.
13:8
BLK_TIME
Adjusts the blank PWMP tON (only primary closed loop) at the beginning of the
PWMP period. 5ns/LSB.
7
RESERVED
Reserved. R/W bits are available, but do not change the device.
6:0
WEIGHT_SS
Accumulation step during soft start.
WEIGHT_2_1 (30h)
The WEIGHT_2_1 command configures the value at which tON increases in the primary closed loop when
the set signal is received during the last two quarters of the remaining PWMP pulse, and BLK_TIME (2Fh)
is disabled.
Command
WEIGHT_2_1
Format
Bit
Access
Function
Unsigned binary
15
14
13
12
R/W
R/W
R/W
R/W
11
10
9
8
7
6
5
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEIGHT_2
3
2
1
0
R/W
R/W
R/W
R/W
WEIGHT_1
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
36
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
15
RESERVED
Reserved. R/W bits are available, but do not change the device.
14:8
WEIGHT_2
Value at which the primary closed loop tON increases when the set signal occurs
during the third quarter of the remaining PWMP period (PWMP with BLK_TIME is
disabled).
7
RESERVED
Reserved. R/W bits are available, but do not change the device.
6:0
WEIGHT_1
Value at which the primary closed loop tON increases when the set signal is
received during the final quarter (not including the last 5ns) of the remaining PWMP
period (PWMP with BLK_TIME is disabled).
WEIGHT_4_3 (31h)
The WEIGHT_4_3 command configures the value at which tON increases in the primary closed loop when
the set signal is received on the first two quarters of the remaining PWMP pulse, not including BLK_TIME
(2Fh).
Command
WEIGHT_4_3
Format
Bit
Access
Unsigned binary
15
14
13
12
R/W
R/W
R/W
R/W
Function
Bits
11
10
9
8
7
6
5
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEIGHT_4
3
2
1
0
R/W
R/W
R/W
R/W
WEIGHT_3
Bit Name
Description
15
RESERVED
Reserved. R/W bits are available, but do not change the device.
14:8
WEIGHT_4
Value at which the primary closed loop tON increases when the set signal is
received during the first quarter of the remaining PWMP period (PWMP with
BLK_TIME is disabled).
7
RESERVED
Reserved. R/W bits are available, but do not change the device.
6:0
WEIGHT_3
Value at which the primary closed loop tON increases when the set signal is
received during the second quarter of the remaining PWMP period (PWMP with
BLK_TIME is disabled).
WEIGHT_OCSPK_L_N (32h)
The WEIGHT_OCSPK_L_N command defines the tON decreasing weight of the primary closed loop and
OCSPK_L.
Command
WEIGHT_OCSPK_L_N
Format
Bit
Access
Direct
15
14
13
12
11
10
9
8
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
WEIGHT_OCSPK_L
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
WEIGHT_N
Bits
Bit Name
Description
15:8
WEIGHT_OCSPK_L
Value at which tON decreases when an over-current (OC) spike occurs on CS2
(OCSPK_L).
7:0
WEIGHT_N
Value at which the primary closed-loop tON decreases when no set pulses appear
during the PWMP period while BLK_TIME is disabled.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
37
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
WEIGHT_OCSPK_INC (33h)
The WEIGHT_OCSPK_INC command sets the tON recovering (increasing) value after an over-current
(OC) spike on CS1 or CS2 (OCSPK_H or OCSPK_L, respectively) goes low.
Command
WEIGHT_OCSPK_INC
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15
14:8
7
6:0
WEIGHT_OCSPK_H_INC
WEIGHT_OCSPK_L_INC
Bit Name
Description
RESERVED
Reserved. R/W bits are available, but do not change the device.
WEIGHT_OCSPK_H_INC
Value at which tON recovers (increases) after an over-current (OC) spike on CS1
(OCSPK_H) goes low.
RESERVED
Reserved. R/W bits are available, but do not change the device.
WEIGHT_OCSPK_L_INC
Value at which tON recovers (increases) after an OC spike on CS2 (OCSPK_L)
goes low.
MFR_VIN_DROP_SET (34h)
The MFR_VIN_DROP_SET command configures the two functions when VIN drops.
Command
MFR_VIN_DROP_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
Bits
RESERVED
VINL_VOUTH_DELTA
2
1
0
R/W
R/W
R/W
VODROP_DAC
Bit Name
Description
15:13
RESERVED
Not defined. Read-only.
12:8
RESERVED
Reserved. R/W bits are available, but do not change the device.
7:4
VINL_VOUTH_DELTA
When the MP2981’s VINSEN drops below VOSEN - VINL_VOUTH_DELTA, the
SR_PWM pins start skipping.
3:0
VODROP_DAC
When the MP2981’s VINSEN exceeds VOSEN + VODROP_DAC, the SR_PWM
pins start generating.
VIN_ON (35h)
The VIN_ON command defines the levels for VIN to start working. After VIN ramps up to VIN_ON, the
MP2981 starts to count START_DELAY (PROTECT_DELAY must finish counting before
START_DELAY) and then to generate PWMs. This level should be greater than VIN_OFF.
Command
VIN_ON
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
Access
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
X
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
VIN_ON
Bits
Bit Name
Description
15:9
RESERVED
Not defined. Read-only.
8:0
VIN_ON
If READ_VIN ≤ VIN_ON and the power is off or READ_VIN < VIN_OFF at any
moment, VIN under-voltage lockout (UVLO) occurs. 0.25V/LSB.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
38
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
VIN_OFF (36h)
The VIN_OFF command defines the VIN level when the device is on and VIN starts working. This level
should be below VIN_ON.
Command
VIN_OFF
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
X
VIN_OFF
Bits
Bit Name
Description
15:9
RESERVED
Not defined. Read-only.
8:0
VIN_OFF
If READ_VIN ≤ VIN_ON and the power is off or READ_VIN < VIN_OFF at any
time, VIN under-voltage lockout (UVLO) occurs. 0.25V/LSB.
IOUT_CAL_GAIN (38h)
The IOUT_CAL_GAIN command helps calculate READ_IOUT (8Ch), bits[9:0] (0.25A/LSB).
IOUT_CAL_GAIN can be calculated with Equation (5):
1
IOUT _ CAL _ GAIN = k CS RCS 3 214
2
(5)
Where kCS is the DrMOS current-sense (CS) gain (e.g. if the CS gain is 5µA/A, kCS = 5e - 6) (in A/A), and
RCS is the resistor connected from CS1/CS2 to GND (in Ω).
Command
IOUT_CAL_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
Bits
15:10
9:0
IOUT_CAL_GAIN
Bit Name
Description
RESERVED
Not defined. Read-only.
IOUT_CAL_GAIN
These bits help calculate READ_IOUT.
IOUT_CAL_OFFSET (39h)
The IOUT_CAL_OFFSET command calculates READ_IOUT (8Ch), bits[9:0] (0.25A/LSB). It is in signed
binary format and uses complements. READ_IOUT can be estimated with Equation (6):
READ _IOUT =
IOUT _ SENSE 205
+ IOUT _ CAL _ OFFSET
2 IOUT _ CAL _ GAIN
(6)
Where IOUT_SENSE is the 10-bit ADC sampling result on the IMON pin.
Command
IOUT_CAL_OFFSET
Format
Signed binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
X
X
X
X
Bits
Bit Name
Description
15:6
RESERVED
Not defined. Read-only.
IOUT_CAL_OFFSET
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
39
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
5:0
IOUT_CAL_OFFSET
Calculates READ_IOUT.
VIN_CAL_GAIN (3Ah)
The VIN_CAL_GAIN command calculates READ_VIN (88h), bits[9:0] (0.125V/LSB). VIN_CAL_GAIN can
be calculated with Equation (7):
VIN_ CAL _ GAIN = GAIN 214
(7)
Where GAIN is the VIN divider ratio (e.g. if a 48V VIN results in 1V on the MP2981’s VINSEN pin with the
resistor divider, then GAIN = 1/48). READ_VIN can be estimated with Equation (8):
VIN _ SENSE 205
VIN _ CAL _ GAIN
READ _ VIN =
(8)
Where VIN_SENSE is the 10-bit ADC sampling result on the VINSEN pin.
Command
VIN_CAL_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
Bits
15:10
9:0
VIN_CAL_GAIN
Bit Name
Description
RESERVED
Not defined. Read-only.
VIN_CAL_GAIN
Calculates READ_VIN.
VOUT_CAL_GAIN (3Bh)
The VOUT_CAL_GAIN command helps calculate READ_VOUT (8Bh), bits[8:0] (62.5mV/LSB).
VOUT_CAL_GAIN can be calculated with Equation (9):
VOUT _ CAL _ GAIN = GAIN 211
(9)
Where GAIN is the VOUT divider ratio (e.g. if 6V VOUT results in 1V on the VOSEN pin with the resistor
divider, then GAIN = 1/6).
READ_VOUT can then be calculated with Equation (10):
READ _ VOUT =
VOUT _ SENSE 205
4 VOUT _ CAL _ GAIN
(10)
Where VOUT_SENSE is the 10-bit ADC sampling result of the VOSEN pin.
Command
VOUT_CAL_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
Bits
15:10
9:0
Bit Name
Description
RESERVED
Not defined. Read-only.
VOUT_CAL_GAIN
Helps calculated READ_VOUT.
VOUT_CAL_GAIN
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
40
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
VIN_OV_FLT_LIM (40h)
The VIN_OV_FLT_LIM command sets the VIN over-voltage protection (OVP) fault limit. Compared to
READ_VIN (88h), bits[9:1].
Command
VIN_OV_FLT_LIM
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
X
VIN_OV_FLT_LIM
Bits
Bit Name
Description
15:9
RESERVED
Not defined. Read-only.
8:0
VIN_OV_FLT_LIM
VIN over-voltage protection (OVP) limit. 0.25V/LSB.
TEMP_GAIN_OFFSET (42h)
The TEMP_GAIN_OFFSET command calculates READ_TEMP (8Dh), bits[7:0] (1°C/LSB).
MFR_TEMP_GAIN is an unsigned binary, while MFR_TEMP_OFFSET is a signed binary that uses
complement format. READ_TEMP is calculated from the TEMP pin, and reflects the DrMOS temperature
(T (°C)). Assuming the TEMP pin voltage (V) = k x (T(°C) - a), READ_TEMP can be estimated with
Equation (11):
READ _ TEMP =
TEMP _ PIN _ SENSE MFR _ TEMP _ GAIN
+ MFR _ TEMP _ OFFSET (11)
512
Where TEMP_PIN_SENSE is the 10-bit ADC sampling result on the TEMP pin, and MFR_TEMP_GAIN
and MFR_TEMP_OFFSET can be calculated with Equation (12) and Equation (13), respectively:
0.8
k
(12)
MFR _ TEMP _ OFFSET = a
(13)
MFR _ TEMP _ GAIN =
Command
TEMP_GAIN_OFFSET
Format
Bit
Access
Unsigned binary, signed binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MFR_TEMP_GAIN
MFR_TEMP_OFFSET
Bits
Bit Name
Description
15:8
MFR_TEMP_GAIN
Proportional to the voltage vs. temperature (V-T) line gain. Unsigned binary.
7:0
MFR_TEMP_OFFSET
Proportional to the voltage value when T = 0°C. Signed binary.
DIETEMP_GAIN_OFFSET (43h)
The DIETEMP_GAIN_OFFSET command calculates READ_DIE_TEMP (8Eh), bits[7:0] (1°C/LSB).
MFR_DIE_TEMP_GAIN is an unsigned binary, while MFR_DIE_TEMP_OFFSET is a signed binary that
uses complement format. The MP2981 senses its die temperature on the chip (not the TEMP pin).
READ_DIE_TEMP can be calculated with the sensed ADC results using Equation (14):
READ _ DIE _ TEMP =
DIE _ TEMP _ SENSE GAIN
+ OFFSET
512
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
(14)
41
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
MFR_DIE_TEMP_GAIN and MFR_DIE_TEMP can be estimated with Equation (15) and Equation (16),
respectively:
0.8
k
(15)
MFR _ DIE _ TEMP _ OFFSET = a
(16)
MFR _ DIE _ TEMP _ GAIN =
Assume the voltage (V) input to ADC = k x (T(°C) - a) during positive mode (06h, bit[11] = 0), which is
the default mode. Positive mode is the default V-T wave mode. The second mode is negative mode (06h,
bit[11] = 1). In negative mode, READ_DIE_TEMP can be calculated with Equation (17):
READ _ DIE _ TEMP = −
DIE _ TEMP _ SENSE (GAIN + 256)
+ OFFSET + 350
512
(17)
Where DIE_TEMP_SENSE is the 10-bit ADC sampling result of the chip’s sensed temperature, GAIN is
short for MFR_DIE_TEMP_GAIN, and OFFSET is short for MFR_DIE_TEMP_OFFSET.
In VBE mode, MFR_DIE_TEMP_GAIN and MFR_DIE_TEMP_OFFSET can be estimated with Equation
(18) and Equation (19), respectively:
0.8
− 256
k
(18)
MFR _ DIE _ TEMP _ OFFSET = a − 350
(19)
MFR _ DIE _ TEMP _ GAIN = −
Command
DIETEMP_GAIN_OFFSET
Format
Bit
Access
Unsigned binary, signed binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MFR_DIE_TEMP_GAIN
MFR_DIE_TEMP_OFFSET
Bits
Bit Name
Description
15:8
DIE_TEMP_GAIN
Helps calculate READ_DIE_TEMP. Unsigned binary.
7:0
DIE_TEMP_OFFSET
Helps calculate READ_DIE_TEMP. Signed binary.
MFR_USER_PWD (44h)
The MFR_USER_PWD command is the configured user password for PMBus/I2C communication. Writeonly. All reads are 0.
Command
MFR_USER_PWD
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Function
Bits
Bit Name
Description
15:0
MFR_USER_PWD
Configures the user password for PMBus/I2C communication.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
42
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
MFR_MTP_WP (45h)
The MFR_MTP_WP command provides MTP write protection. The MTP store command cannot be
executed if this byte is not 8’h63.
Command
Format
Bit
Access
Function
7
R/W
6
R/W
MFR_MTP_WP
Direct
4
3
R/W
R/W
MFR_MTP_WP
5
R/W
Bits
Bit Name
Description
7:0
MFR_MTP_WP
MTP write protection.
2
R/W
1
R/W
0
R/W
SKIPDRMOS_SR_EARLI (46h)
The SKIPDRMOS_SR_EARLI command allows the device to skip the DrMOS function under light-load
conditions. It is related to registers 1Ah and 49h. This register also sets the time length at which SR_PWM
turns on before PWMP.
Command
SKIPDRMOS_SR_EARLI
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
SR_POS_EARLIER
SKIPSR_DELAY
Bit Name
Description
15:13
RESERVED
Reserved. R/W bits are available, but do not change the device.
12:8
SR_POS_EARLIER
Determines how early SR_PWM turns on before PWMP. 5ns/LSB.
RESERVED
Reserved. R/W bits are available, but do not change the device.
7
Enables bypassing the DrMOS function (the SKIP_EN pin).
6
5:0
SKIP_DRMOS_EN
1’b1: Enabled
1’b0: Disabled
SKIPSR_DELAY_TIME
If SR_PWM is triggered by SKIP_PWM_EN or SKIP_DRMOS_EN before skipping
under light-load conditions, the current must stay low for this set time. One whole
ADC sample round/LSB, which is about 18µs/LSB if MFR_ADC_HOLD_TIME
(05H) is set to 2µs.
MFR_IOUT_LEVEL (49h)
The MFR_IOUT_LEVEL command configures the TDC IOUT values to skip the DrMOS function under
light-load conditions (the MP2981’s SKIP_EN pin, 46h, and 1Ah). If the load increases and READ_IOUT
(8Ch) / 2 exceeds MFR_IOUT_LEVEL_H, then the SKIP_EN pin goes low and the DrMOS MOSFET
starts working.
The other way to exit skip mode is for the CS1 pin to exceed CMP_CS1_EXITSKIP (1Ah). The only
condition to enter DrMOS skip mode is that READ_IOUT (8Ch) / 2 ≤ MFR_IOUT_LEVEL_L for a
configured time (46h).
Command
MFR_IOUT_LEVEL
Format
Bit
Access
Function
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MFR_IOUT_LEVEL_H
MFR_IOUT_LEVEL_L
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
43
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
15:8
MFR_IOUT_LEVEL_H
Sets the TDC IOUT value to exit DrMOS skip mode.
7:0
MFR_IOUT_LEVEL_L
Sets the TDC IOUT value to enter DrMOS skip mode.
MFR_VCAL_I_MAX (4Bh)
The MFR_VCAL_I_MAX command defines the integration factor and the maximum DC loop limit.
Command
MFR_VCAL_I_MAX
Format
Bit
Access
Unsigned binary
15
14
13
R/W
R/W
R/W
Function
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MFR_VCAL_I
MFR_VO_CMPS_MAX
Bits
Bit Name
Description
15:8
MFR_VCAL_I
The integration factor of the DC loop.
7:0
MFR_VO_CMPS_MAX
The maximum limit of the value input into the VO_COMP DAC.
DC_TRIM (4Ch)
The DC_TRIM command sets the initial value of the VO_COMP DAC. The initial VO_COMP is DC_TRIM
x 8. When the DC loop is enabled, VO_COMP = DC_TRIM x 8 - (DC loop result). If the DC loop is
disabled, the data input to the VO_COMP DAC keeps the value before disabling. The DAC output is
divided by 2, then added to VOSEN. The sum signal is one input of the primary closed-loop comparator.
Command
Format
Bit
Access
Function
DC_TRIM
Direct
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
DC_TRIM
1
R/W
Bits
Bit Name
Description
7:5
RESERVED
Reserved. R/W bits are available, but do not change the device.
4:0
DC_TRIM
DC_TRIM x 8 is the initial value input into the VO_COMP DAC.
0
R/W
MPS_CODE (50h)
The MPS_CODE command is written with a code that represents MPS.
Command
MPS_CODE
Format
Bit
Access
Direct
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:0
MPS_CODE
This code represents MPS.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
44
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PRODUCT_CODE (51h)
The PRODUCT_CODE command is written with “2981” (hex code), and represents the MP2981 chip.
Command
PRODUCT_CODE
Format
Bit
Access
Direct
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:0
PRODUCT_CODE
This code represents the MP2981 chip. It is 2981 (hex radix).
CONFIG_ID (52h)
The CONFIG_ID command should be written with the specific application programming code.
Command
CONFIG_ID
Format
Bit
Access
Direct
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:0
CONFIG_ID
Write with a specific application programming code.
CONFIG_REV (53h)
The CONFIG_REV command should be written with a version of the specific application programming
code or complement programming code.
Command
CONFIG_REV
Format
Bit
Access
Direct
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
Bit Name
Description
15:0
CONFIG_REV
Write with a version of a specific application programming code or complement
programming code.
CALVO_LOW_TON_SS_L (5Ah)
The CALVO_LOW_TON_SS_L command defines the upper limit of VOUT to enable the two stages
(TONLL and TONL) of the SR_PWM pins turning off after the PWMPs during soft start. If VOUT >
CALVOUT_LOW_LVL x 0.125V, TONLL and TONL are invalid. It also sets the two t ON boundaries of
these two stages. TON_LVL_SS_L must be greater than or equal to TON_LVL_SS_LL.
Command
CALVO_LOW_TON_SS_L
Format
Bit
Access
Function
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CALVOUT_LOW_LVL
TON_LVL_SS_L
TON_LVL_SS_LL
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
45
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
CALVOUT_LOW_LVL
If READ_VOUT / 2 (8Bh) > CALVOUT_LOW_LVL, then the TONLL and TONL
stages during soft start can be disabled by setting CALVOUT_LOW_LMT_TONL
(in 0Fh) high. 125mv/LSB.
9:4
TON_LVL_SS_L
If TON_LVL_SS_L > tON ≥ TON_LVL_SS_LL during soft start, the SR_PWM pins
turn off after the PWMP pins by (SRNEG_SS_TONL_DLY + 1) x 5ns. Related to
2Bh. 5ns/LSB.
3:0
TON_LVL_SS_LL
If tON < TON_LVL_SS_LL during soft start, the SR_PWM pins turn off after the
PWMP pins by (SRNEG_SS_TONLL_DLY + 1) x 5ns. Related to 2Bh. 5ns/LSB.
15:10
TON_SS_H (5Bh)
The TON_SS_H command sets the two tON boundaries that turn the SR_PWM pins off before the PWMP
pins during soft start. TON_LVL_SS_HH must be greater than or equal to TON_LVL_SS_H.
Command
TON_SS_H
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
Bits
TON_LVL_SS_H
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
TON_LVL_SS_HH
Bit Name
Description
RESERVED
Not defined. Read-only.
14:8
TON_LVL_SS_H
If TON_LVL_SS_HH > tON ≥ TON_LVL_SS_H during soft start, then the SR_PWM
pins turn off before the PWMP pins by (SRNEG_SS_TONH_DEC x 5ns). Related
to 2Bh. 5ns/LSB.
7:0
TON_LVL_SS_HH
If tON ≥ TON_LVL_SS_HH during soft start, the SR_PWM pins turn off before the
PWMP pins by (SRNEG_SS_TONHH_DEC x 5ns). Related to 2Bh. 5ns/LSB.
15
POWER_GOOD_ON (5Eh)
The POWER_GOOD_ON command defines a VID level close to the VID target (21h, bits[7:0]). This
means that VID ramping up is almost completed, and the PG on delay starts to use VID (instead of tON)
as the PG reference (06h, bit[2]).
Command
POWER_GOOD_ON
Format
Direct
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
X
X
X
X
X
X
POWER_GOOD_ON
Bits
Bit Name
Description
15:8
RESERVED
Not defined. Read-only.
7:0
POWER_GOOD_ON
VID level that means VID ramping up is almost done. Must be set below or equal
to the VID target (21h, bits[7:0]). 6.25mV/LSB.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
46
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
POWER_GOOD_OFF (5Fh)
If VID is below or equal to this register and VID is selected as the PG reference (06h, bit[2]), then PG
goes low.
Command
POWER_GOOD_OFF
Format
Direct
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Function
POWER_GOOD_OFF
Bits
Bit Name
Description
15:8
RESERVED
Not defined. Read-only.
7:0
POWER_GOOD_OFF
Determines the VID level of PG off if VID is selected as the PG reference. Must be
set below POWER_GOOD_ON (5Eh), bits[7:0]. 6.25mV/LSB.
PROTECT_DELAY (60h)
The PROTECT_DELAY sets the delay time after a shutdown occurs. After a shutdown protection that
does not include an over-current (OC) spike (e.g. Phase OC, OCSPK_H, and OCSPK_L) occurs, the
device starts counting PROTECT_DELAY. After this delay, the chip starts to count START_DELAY (63h),
and then generates PWMs and ramps VID up again.
If the device has been configured to hiccup or retry mode, then the restart times are not completed
(VOUT_OVP_MAX, OVP_VID, UVP_VID, UVP_MIN, OCP_TDC, or OCP_SPIKE), and are reset by
VIN_UVLO.
Command
Format
Bit
Access
Function
Bits
7
6:0
7
R
X
6
R/W
5
R/W
PROTECT_DELAY
Direct
4
3
2
R/W
R/W
R/W
PROTECT_DELAY
1
R/W
0
R/W
Bit Name
Description
RESERVED
Not defined. Read-only.
PROTECT_DELAY
Sets the delay between a protection shutdown and when the device restarts.
100µs/LSB.
PWRGD_DELAY (62h)
The PWRGD_DELAY command sets the delay period between the end of PG reference (tON increasing
to TON_NORMAL (1Eh) or VID ramping up to POWER_GOOD_ON (5Eh)) ramping to when the PG pin
turns on.
Command
Format
Bit
Access
Function
Bits
7
7
R/W
6
R/W
5
R/W
Bit Name
Description
PWRGD_DELAY_SEL
1’b1: 20kHz
1’b0: 50kHz
PWRGD_DELAY
Unsigned binary
4
3
R/W
R/W
PWRGD_DELAY
2
R/W
1
R/W
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
0
R/W
47
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
6:0
After VID reaches POWER_GOOD_ON (5Eh) or tON reaches TON_NORMAL
(1Eh), this delay time starts counting. After this delay finishes, PG goes high.
PWRGD_DELAY
If 62h[7] = 1, the PWRGD_DELAY time = [6:0] x 50µs
If 62h[7] = 0, the PWRGD_DELAY time = [6:0] x 20µs
START_DELAY (63h)
The START_DELAY command sets the time length for which the EN pin must stay high during start-up,
after the MTP finishes restoring, and before VID starts slewing up and PWM switches.
Command
START_DELAY
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15:0
Bit Name
Description
START_DELAY
Determines if the device requires a continuously high EN pin during start-up. The
resolution is determined by MFR_ONOFFDLY_CLK_1L0S (06h, T). The time
length can be calculated with the following equation:
Length = 256 x T x START_DELAY[15:8] + T x START_DELAY[7:0]
OFF_DELAY (64h)
The OFF_DELAY command sets the delay time after the EN pin turns off or the PMBus/I2C sends an
OFF command. This is during normal operation, and before shutting down VID, PG, and the PWM pins.
Command
OFF_DELAY
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15:0
Bit Name
Description
OFF_DELAY
Determines the part’s delay before shutting down. The resolution is determined by
MFR_ONOFFDLY_CLK_1L0S (06h, T). The delay can be calculated with the
following equation:
Delay = 256 x T x OFF_DELAY[15:8] + T x OFF_DELAY, bits[7:0]
MFR_OTP_SET (65h)
The MFR_OTP_SET command controls the TEMP pin’s parameters if over-temperature protection (OTP)
occurs.
Command
MFR_OTP_SET
Format
Unsigned binary
Bit
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15
14:8
MFR_OTP_HYS
MFR_OTP_LIMIT
Bit Name
Description
MFR_OTP_LATCH
1’b1: Latch-off mode
1’b0: Hiccup mode
MFR_OTP_HYS
The TEMP pin’s over-temperature (OT) hysteresis limit. When READ_TEMP (8Dh)
≤ (MFR_OTP_LIMIT - MFR_OTP_HYS), the OT comparator goes low. 1°C/LSB.
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
48
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
7:0
MFR_OTP_LIMIT
TEMP pin over-temperature (OT) limit. 1°C/LSB.
MFR_DIE_OTP_SET (66h)
The MFR_DIE_OTP_SET command controls the die temperature’s parameters if over-temperature
protection (OTP) occurs.
Command
MFR_DIE_OTP_SET
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
MFR_DIE_OTP_HYS
MFR_DIE_OTP_LIMIT
Bit Name
Description
MFR_DIE_OTP_LATCH
1’b1: Latch-off mode
1’b0: Hiccup mode
14:8
MFR_DIE_OTP_HYS
Hysteresis of the die temperature’s over-temperature (OT) limit. When
READ_TEMP (8Dh) ≤ (MFR_DIE_OTP_LIMIT - MFR_DIE_OTP_HYS), the OT
comparator goes low. 1°C/LSB.
7:0
MFR_DIE_OTP_LIMIT
Die temperature over-temperature (OT) limit. 1°C/LSB.
15
PMBUS/I2C_ADDR_SET (67h)
The PMBUS/I2C_ADDR_SET command configures the 7-bit PMBus/I2C slave address (the chip’s
PMBus/I2C address).
Command
Format
Bit
Access
Function
7
R/W
6
R/W
5
R/W
PMBUS/I2C_ADDR_SET
Unsigned binary
4
3
R/W
R/W
2
R/W
1
R/W
0
R/W
Bits
Bit Name
Description
7:0
PMBUS/I2C_ADDR_SET
Final PMBus/12C address = 67h, bits[6:4]. If bit[7] = 1, then the final PMBus/I2C
address bits[3:0] comes from sampling the ADDRP pin. If bit[7] = 0, then the final
PMBus/I2C address [6:0] = 67h, bits[6:0].
MFR_PROTECT_CFG (68h)
The MFR_PROTECT_CFG command controls certain device protections.
Command
MFR_PROTECT_CFG
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
15
14:12
Bit Name
Description
UVLO_STARTUP_MTP_EN
1’b1: Only store VIN under-voltage lockout (UVLO) conditions that occur
when power is being delivered to the MTP
1’b0: Store all VIN UVLO occurrences in the MTP
RESERVED
Reserved. R/W bits are available, but do not change the device.
Selects the trigger mode for DrMOS over-current protection (OCP).
11
DrMOS_OC_LATCH
1’b1: Latch-off mode
1’b0: Hiccup mode
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
49
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Enables DrMOS OCP.
10
DrMOS_OC_EN
9
VOUT_OVP_MAX_LATCH
8
VOUT_OVP_MAX_EN
1’b1: Enabled
1’b0: Disabled
Selects the VOUT_OVP_MAX protection mode.
1’b1: Latch-off mode
1’b0: Hiccup mode
Enables VOUT_OVP_MAX protection.
1’b1: Enabled
1’b0: Disabled
Enables DIE_TEMP protection.
7
DIE_TEMP_PRO_EN
6
TEMP_PRO_EN
1’b1: Disable DIE_TEMP protection
1’b0: Enable DIE_TEMP protection
1’b1: Disable over-temperature protection (OTP) from the TEMP pin (not
including DrMOS OC or DIE_TEMP)
1’b0: Enable OTP from the TEMP pin
Determines how the device responds when a VIN protection is enabled
(RST_VIN_PRO = 0).
5
MFR_VIN_OVP_LATCH
4
RST_VIN_PRO
1’b1: Disable VIN protection, including VIN UVLO and VIN over-voltage
protection (OVP)
1’b0: Enable VIN protection, including VIN UVLO and VIN OVP
3
UVLO_STARTUP_STATUS
_EN
1’b1: Only store VIN UVLO occurrences while power is delivered to
STATUS_WORD
1’b0: Store all VIN UVLO occurrences to STATUS_WORD.
2
1
1’b1: Latch-off mode
1’b0: Hiccup mode
Enables resetting STATUS_XX during a restart, after the EN pin is off, and
when operation is off.
RST_STATUS_EN
1’b1: Reset STATUS_XX during a restart
1’b0: Do not reset STATUS_XX during a restart
Select the clock counting the 4-clock delay after tON reaches TON_NORMAL,
before OVP_VID, UVP_VID, and UVP_MIN can be enabled.
SS_EXT_CLK_SEL
1’b1: 20kHz
1’b0: 50kHz
1’b1: Disable all protection features
1’b0: Enable all protection features
0
There are two protections that cannot be controlled by this bit:
DISABLE_ALL_PRO
•
•
PWM tON change during over-current (OC) spikes on the CS1 or CS2
pins (OCSPK_H and OCSPK_L, respectively)
Counting of OC spikes on CS1 (OCSPK_H) before the device shuts
down
OVP_UVP_VID_SET (69h)
The OVP_UVP_VID_SET command controls VOUT_OVP_VID and UVP_VID protection. Their levels are
defined in 19h.
Command
OVP_UVP_VID_SET
Format
Bit
Access
Function
Unsigned binary
15
14
13
12
R/W
R/W
R/W
R/W
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OVP_VID_DELAYTIME
UVP_VID_DELAYTIME
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
50
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
OVP_VID_MODE
2’b00: No action
2’b01: Latch-off mode
2’b10: Hiccup mode
2’b11: Retry 3 times or 6 times based on OVP_VID_RETRY_TIMES
OVP_VID_RETRY_TIMES
1’b1: Retry 3 times
1’b1: Retry 6 times, when MFR_OVP_SET_MODE is 11b
OVP_VID_DELAYTIME
If VOUT stays high for a set time, VOUT over-voltage protection (OVP) is triggered.
200ns/LSB.
7:6
UVP_VID_MODE
2’b00: No action
2’b01: Latch-off mode
2’b10: Hiccup mode
2’b11: Retry 6 times
5:0
UVP_VID_DELAYTIME
If VOUT stays low for the set time, VOUT under-voltage protection (UVP) is
triggered. 20µs/LSB.
15:14
13
12:8
OCP_TDC_SET (6Ah)
The OCP_TDC_SET command controls TDC over-current protection (OCP).
Command
OCP_TDC_SET
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Bits
OCP_TDC_DELAYTIME
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
OCP_TDC_LEVEL
Bit Name
Description
15:14
OCP_TDC_MODE
2’b00: No action
2’b01: Latch-off mode
2’b10: Hiccup mode
2’b11: Retry 6 times
13:8
OCP_TDC_DELAYTIME
If the TDC current stays high for this set time, over-current protection (OCP) is
triggered. 100µs/LSB.
7:0
OCP_TDC_LEVEL
1A/LSB.
OCP_SPIKE_TIMES_SET (6Bh)
The OCP_SPIKE_TIMES_SET command controls the over-current (OC) spike time, which can shut down
the chip.
Command
OCP_SPIKE_TIMES_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
X
X
Bits
15:14
13
12:8
OCP_SPIKE_RANGE
OCP_SPIKE_TIMES
Bit Name
Description
RESERVED
Not defined. Read-only.
DIS_OCP_SPIKE_SS
1’b1: Disable the OCP_SPIKE_TIMES protection during soft start
1’b0: Enable the OCP_SPIKE_TIMES protection during soft start
OCP_SPIKE_RANGE
The time length in which to count over-current (OC) spikes on CS1 (OCSPK_H),
and the time length before starting one OCSPK_H pulse. 1 PWMP period/LSB.
The set time can be calculated with the following equation:
Time length = (PWM1 tON + PWM2 tON + 2 dead time) x [12:8]
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
51
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
7:6
5:0
OCP_SPIKE_MODE
2’b00: No action
2’b01: Latch-off mode
2’b10: Hiccup mode
2’b11: Retry 6 times
OCP_SPIKE_TIMES
If the pulse time of OC spikes on CS1 (OCSPK_H) (both PWM1 and PWM2)
exceeds OCP_SPIKE_TIMES during OCP_SPIKE_RANGE, a protection is
triggered. If the OCSPK_H (both PWM1 and PWM2) pulse time is below
OCP_SPIKE_TIMES during OCP_SPIKE_RANGE, then OCSPK_H pulses are
recounted from 0. The next OC pulse and the detection time window
(OCP_SPIKE_RANGE) also restart.
OCP_SPIKE_LEVEL (6Ch)
The OCP_SPIKE_LEVEL command sets the higher and lower OCP_SPIKE levels. Both levels are
compared with the CS1 and CS2 pins.
Command
OCP_SPIKE_LEVEL
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
HIGHER_SPIKE_LVL
LOWER_SPIKE_LVL
Bits
Bit Name
Description
15:8
HIGHER_SPIKE_LVL
Digital value of the higher OCP_SPIKE DAC. 2V range, 8-bit DAC. The DAC output
is HIGHER_SPIKE_LVL x 2V / 256.
7:0
LOWER_SPIKE_LVL
Digital value of the lower OCP_SPIKE DAC. 2V range, 8-bit DAC. The DAC output
is LOWER_SPIKE_LVL x 2V / 256.
UVP_MIN_SET (6Dh)
The UVP_MIN_SET command controls the VOUT UVP_MIN protection.
Command
Format
Bit
Access
Function
Bits
7
6
R/W
R/W
UVP_MIN_MODE
UVP_MIN_SET
Unsigned binary
4
3
2
R/W
R/W
R/W
UVP_MIN_DELAY
5
R/W
1
R/W
0
R/W
Bit Name
Description
7:6
UVP_MIN_MODE
2’b00: No action
2’b01: Latch-off mode
2’b10: Hiccup mode
2’b11: Retry 6 times
5:0
UVP_MIN_DELAY
If VOUT stays low for this time length, the protection is triggered. 0.4µs/LSB.
STATUS_WORD (79h)
The STATUS_WORD command records general protections and the real-time on/off state. It is reset by
an EN or OPERATION restarting if the RST_STATUS_EN bit (68h), bit[2] is high, by sending the
CLEAR_FAULTS command (03h in Page 0, Page 1, or Page 3), or by cycling the power on VCC3V3.
Command
STATUS_WORD
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
52
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
15
Bit Name
Description
VOUT OVP or UVP
VOUT_OVP_MAX, OVP_VID, UVP_VID, and UVP_MIN fault indicator. If output
over-voltage protection (OVP) or under-voltage protection (UVP) occurs, this bit is
set and latched. The specific protection is determined by STATUS_VOUT (7Ah).
1’b0: No VOUT over-voltage (OV) or under-voltage (UV) fault has occurred
1’b1: A VOUT OV or UV fault has occurred
14
OCP
OCP_TDC or OCP_SPIKE_TIMES fault indicator. If either of these IOUT protections
occur, or an UV fault occurs at the beginning of OCP_TDC, this bit is set and
latched. The specific protection can be viewed by STATUS_IOUT (7Bh).
1’b0: No IOUT over-current (OC) fault has occurred
1’b1: An IOUT OC fault has occurred
VIN under-voltage lockout (UVLO) protection indicator. If READ_VIN ≤ VIN_ON
while the device is off, or READ_VIN < VIN_OFF at any time except during the
reset all protection stages, then this bit is pulled high.
13
VIN_UVLO_FLAG
12
VIN_OVP
11
PG
PG pin state indicator. PG is set high after PWRGD_DELAY. When any protection
or fault occurs during normal operation (power out state), PG is pulled down.
10
RESERVED
Reserved. Reads are always 0.
DrMOS_OCP
DrMOS over-current protection (OCP) fault indicator. If the TEMP pin reaches
VCC3V3 (which means DrMOS OCP fault has occurred), this bit is set and latched.
Specific protections can be viewed by PROTECT_SIG_GRP (7Ch).
VIN OVP fault indicator. If input OVP occurs, this bit is set and latched.
9
1’b0: No VIN OV fault has occurred
1’b1: A VIN OV fault has occurred
1’b0: No DrMOS OC fault has occurred
1’b1: A DrMOS OC fault has occurred
8:7
RESERVED
Reserved. Reads are always 0.
Chip working state indicator.
6
5
EN_SS
OVP_MAX/OVP_VID_
POS
1’b1: The chip is not outputting PWMs or VREF, and the state is off
1’b0: The state is on, and PWMs are switching
VOUT OV positive edge fault indicator. If output OVP_MAX or VID positive edge
protection occurs, this bit is set and latched. Unlike STATUS_VOUT (7Ah), this bit
can be cleared by a CLEAR_FAULTS (03h) command when the protection signal
stays high.
1’b0: No VOUT OV positive edge fault has occurred
1’b1: A VOUT OV positive edge fault has occurred
4
OCP_TDC_POS
IOUT OC positive-edge fault indicator. If output OC positive-edge protection occurs,
this bit is set and latched. Unlike STATUS_IOUT (7Bh), this bit can be cleared by
CLEAR_FAULTS (03h) when the protection signal stays high.
1’b0: No IOUT OC positive edge fault has occurred
1’b1: An IOUT OC positive edge fault has occurred
3
UVP_VID or
UVP_MIN_POS
VOUT UV positive edge fault indicator. If output UV VID or MIN positive-edge
protection occurs, this bit is set and latched. Unlike STATUS_VOUT (7Ah), this bit
can be cleared by a CLEAR_FAULTS (03h) command when the protection signal
stays high.
1’b0: No VOUT UV positive edge fault has occurred
1’b1: VOUT UV positive edge fault has occurred
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
53
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
2
TEMP_OTP or DIE_OTP
Over-temperature protection (OTP) positive edge fault indicator. If OTP from the
TEMP pin sampling or the 2981 internal DIE_TEMP sensor fault occurs, this bit is
set and latched. Specific protections can be viewed by STATUS_TEMP (7Dh).
1’b0: No over-temperature (OT) fault has occurred
1’b1: An OT fault has occurred
1
STATUS_CML_
NONZERO
0
RESERVED
CML positive edge fault indicator. If a CML fault occurs, this bit is set and latched.
Specific protections can be viewed by STATUS_CML (7Ch).
1’b0: No CML fault has occurred
1’b1: CML fault has occurred
Reserved. Unused. Reads are always 0.
STATUS_VOUT (7Ah)
The STATUS_VOUT command records the VOUT protection status. It can be reset by an EN or
OPERATION restart if RST_STATUS_EN bit (68h), bit[2] is high, by sending a CLEAR_FAULTS
command (03h in Page 0, Page 1, or Page 3), or by cycling the power on VCC3C3.
Command
Format
Bit
Access
Function
Bits
7
6
5
4
3:0
7
R
6
R
Bit Name
5
R
STATUS_VOUT
Unsigned binary
4
3
R
R
2
R
1
R
0
R
Description
VOUT OVP_MAX fault indicator. If VOUT exceeds VOUT_MAX, this bit is set and
latched.
OVP_MAX
1’b0: No VOUT OVP_MAX fault has occurred
1’b1: A VOUT OVP_MAX fault has occurred
VOUT OVP_VID fault indicator. If VOUT exceeds OVP_VID for a set time, this bit is
set and latched.
OVP_VID
1’b0: No VOUT OVP_VID fault has occurred
1’b1: A VOUT OVP_VID fault has occurred
VOUT UVP_VID fault indicator. If VOUT drops below UVP_VID for a set time, this bit
is set and latched.
UVP_VID
1’b0: No VOUT OVP_MAX fault has occurred
1’b1: A VOUT OVP_MAX fault has occurred
VOUT OVP_MAX fault indicator. If VOUT drops below UVP_MIN, this bit is set and
latched.
UVP_MIN
1’b0: No VOUT OVP_MAX fault has occurred
1’b1: A VOUT OVP_MAX fault has occurred
RESERVED
Reserved. Reads are always 0.
STATUS_IOUT (7Bh)
The STATUS_IOUT command records the IOUT protection status. It can be reset by an EN or
OPERATION restart if RST_STATUS_EN (68h), bit[2] is high, by sending a CLEAR_FAULTS command
(03h on Page 0, Page 1, or Page 3), or by cycling the power on VCC3V3.
Command
Format
Bit
Access
Function
7
R
6
R
5
R
STATUS_IOUT
Unsigned binary
4
3
R
R
2
R
1
R
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
0
R
54
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
7
6
Bit Name
Description
Normal IOUT over-current protection (OCP) TDC fault indicator. If the TDC remains
high for longer than the set time (6Ah), this bit is set and latched.
OCP_TDC
1’b0: No OCP TDC fault has occurred
1’b1: An OCP TDC fault has occurred
Indicates an under-voltage (UV) fault caused by an IOUT OCP TDC fault. If the UV
comparator output is effective when TDC OCP occurs (after the delay), this bit is
set and latched.
OCP_TDC_UV
1’b0: No OCP TDC/UV fault has occurred
1’b1: An OCP TDC/UV fault has occurred
5
Indicates a UV fault caused by an IOUT OCP TDC fault. If the current-sense (CS)
peak exceeds the OC SPIKE H level and the counting pulse number exceeds the
set number (6Bh, bits[5:0]) in the configured range (6Bh, bits[12:8]), this bit is set
and latched.
OCP_SPIKE_TIMES
1’b0: No OCP TDC/UV fault has occurred
1’b1: An OCP TDC/UV fault has occurred
4:0
RESERVED
Reserved. Reads are always 0.
PROTECT_SIG_GRP (7Ch)
The PROTECT_SIG_GRP command records all protections that can result during shutdown. This
register can be stored in the MTP.
Command
PROTECT_SIG_GRP
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Bits
15:12
11
Bit Name
Description
RESERVED
Reserved. Reads are always 0.
DRMOS_OCP
DrMOS over-current protection (OCP) indicator. If the TEMP pin voltage exceeds
1.8V, a DrMOS OCP fault occurs. DRMOS_OCP protection is triggered, and this
bit is set and latched. When an over-current (OC) condition occurs, DrMOS sets
its TEMP pin to VCC.
1’b0: No DrMOS OCP has occurred
1’b1: DrMOS OCP has occurred
10
9
8
7
RESERVED
OCP_TDC
OCP_SPIKE_TIMES
VIN_OVP
Reserved. Reads are always 0.
IOUT TDC OCP indicator. If IOUT TDC OCP occurs and triggers TDC OCP protection,
this bit is set and latched.
1’b0: No TDC OCP has occurred
1’b1: TDC OCP has occurred
OCP_SPIKE_TIMES protection indicator. If an OCP_SPIKE_TIMES fault occurs
and triggers a protection, this bit is set and latched.
1’b0: No OCP_SPIKE_TIMES protection has not occurred
1’b1: A OCP_SPIKE_TIMES protection has occurred
VIN over-voltage protection (OVP) indicator. If VIN OVP is triggered, this bit is set
and latched.
1’b0: No VIN OVP has occurred
1’b1: VIN OVP has occurred
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
55
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
6
VIN under-voltage lockout (UVLO) indicator. If VIN UVLO occurs when delivering
power or if UVLO_STARTUP_MTP_EN (68h), bit[15] is enabled, then this bit is set
and latched.
VIN_UVLO
1’b0: No VIN UVLO fault has occurred
1’b1: A VIN UVLO fault has occurred
5
4
3
2
1
0
Over-temperature protection (OTP) from sampling the TEMP pin indicator. If this
fault occurs and triggers the protection, this bit is set and latched.
OTP
1’b0: No OTP has occurred
1’b1: OTP has occurred
Die OTP protection indicator. If the MP2981’s die temperature exceeds its overtemperature (OT) limit and triggers the protection, this bit is set and latched.
DIE_OTP
1’b0: No die OTP has occurred
1’b1: Die OTP has occurred
VOUT OVP_MAX protection indicator. If a VOUT OVP max fault occurs and triggers
the protection, this bit is set and latched.
OVP_MAX
1’b0: No VOUT OVP_MAX protection has occurred
1’b1: A VOUT OV_MAX protection has occurred
VOUT OVP_VID protection indicator. If VOUT OVP VID fault occurs and triggers the
protection, this bit is set and latched.
OVP_VID
1’b0: No VOUT OVP_MAX protection has occurred
1’b1: A VOUT OV_MAX protection has occurred
VOUT UVP_VID protection indicator. If a VOUT UVP_VID fault occurs and triggers
the protection, this bit is set and latched.
UVP_VID
1’b0: No VOUT UVP_VID protection has occurred
1’b1: A VOUT UVP_VID protection has occurred
VOUT UVP_MIN protection indicator. If a VOUT UVP_MIN fault occurs and triggers
the protection, this bit is set and latched.
UVP_MIN
1’b0: No VOUT UVP_MIN protection has occurred
1’b1: A VOUT UVP_MIN protection has occurred
STATUS_TEMP (7Dh)
The STATUS_TEMP command records the protection statuses related to the TEMP pin. It can be reset
by EN or OPERATION restarting if RST_STATUS_EN bit (68h, bit[2]) is high, by sending a
CLEAR_FAULTS command (03h on Page 0, Page 1, or Page 3), or by cycling the power on VCC3V3.
Command
Format
Bit
Access
Function
Bits
7
6
7
R
Bit Name
OTP
DIE_OTP
6
R
5
R
STATUS_TEMP
Unsigned binary
4
3
R
R
2
R
1
R
0
R
Description
Over-temperature protection (OTP) fault indicator. If an over-temperature (OT)
fault is sampled on the TEMP pin, this bit is set and latched.
1’b0: No OTP fault has occurred
1’b1: An OTP fault has occurred
Die OTP fault indicator. If the MP2981’s die temperature exceeds its OT threshold,
this bit is set and latched.
1’b0: No Die OTP has occurred
1’b1: Die OTP has occurred
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
56
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
5
DrMOS over-current protection (OCP) fault indicator. If the TEMP pin exceeds
1.8V and a DrMOS OCP fault occurs, this bit is set and latched. When an overcurrent (OC) condition occurs, DrMOS sets its TEMP pin to VCC.
DRMOS_OCP
1’b0: No DrMOS OCP has occurred
1’b1: DrMOS OCP has occurred
4:0
RESERVED
Reserved. Reads are always 0.
STATUS_CML (7Eh)
The STATUS_CML command records the status between PMBus/I2C and MTP communication. It can
be reset by sending a CLEAR_FAULTS command (03h on Page 0, Page 1, or Page 3).
Command
Format
Bit
Access
Function
Bits
7
R
6
R
Bit Name
7
CML_INVALID_CMD
6
INTERNAL_DEBUG
5
4
CML_PEC_FAULT
LATCHED_WRFAIL
5
R
STATUS_CML
Unsigned binary
4
3
R
R
2
R
1
R
0
R
Description
CML invalid command fault indicator. If the received PMBus/I2C command is not
defined, this bit is set and latched.
1’b0: No CML invalid command fault has occurred
1’b1: A CML invalid command fault has occurred
Used for debugging.
CML peculiar fault indicator. If the received PMBus/I2C command does not match
the command sent by the master, this bit is set and latched.
1’b0: No CML peculiar fault has occurred
1’b1: A CML peculiar fault has occurred
WRFAIL is a flag signal from the MTP. It signifies that 1 byte written to the MTP
has failed. The MTP_WRFAIL output is reset at the start of writing the next byte.
This bit is the latched result of the MTP_WRFAIL signal. Reset this bit by sending
a CLEAR_FAULTS command (03h) and the beginning the next MTP write process
(not writing the next byte) after the current MTP storing process finishes.
If at least one of the three cyclic redundancy check (CRC) faults occurs, then the
corresponding CRC enable bit (07h, bits[15:13]) is set to 1:
1.
2.
3
CRC_FAULT_ENABLED
3.
The CRC of the first two sections of the MTP (8’h00 to 8’hDD MTP addresses,
8’hDE and 8’hDF store the CRC calculation result). Valid in STORE_ALL
(15h),
RESTORE_ALL
(16h),
STORE_USER_ALL
(17h),
and
RESTORE_USER_ALL (18h). Its enable bit is 07h, bit[15].
The CRC of the third section of MTP (8’hE0 to 8’hFB MTP addresses, 8’hFC,
and 8’hFD are the calculated CRC). Valid in STORE_ALL (15h),
RESTORE_ALL (16h), STORE_S3 (F5h), and RESTORE_S3 (F6h). Its
enable bit is 07h, bit[14].
The total MTP CRC (8’h00 to 8’hFD MTP addresses, 8’hFE and 8’hFF store
the calculated CRC). Valid in STORE_ALL (15h) and RESTORE_ALL (16h).
This CRC cannot be enabled or configured by the user due to the commands
STORE_USER_ALL (17h) and RESTORE_USER_ALL (18h). If
RESTORE_ALL (16h) is sent after STORE_USER_ALL (17h), this CRC error
is a false alarm. Its enable bit is 07h, bit[13].
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
57
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
2
MTP storing state indicator. If MTP storing has finished without errors, this bit is
set. The stored MTP commands are: STORE_ALL (15h), STORE_USER_ALL
(17h), STORE_S3 (F5h), and DBG_MTP (F7h).
STORE_OK
1’b0: MTP storing is not complete
1’b1: MTP storing has completed without errors
1
0
CML_OTHER_FAULT
MTP_SIGNATURE_
FAULT
Other CML fault indicator. If a false start or stop bit shows up during a normal I2C
command, this bit is set and latched.
1’b0: No other CML fault has occurred
1’b1: A different CML fault has occurred
MTP signature fault indicator. If the first 2 bytes of the MTP are not 16’h1234, this
bit is set and latched.
1’b0: No MTP_SIGNATURE_FAULT has occurred
1’b1: MTP_SIGNATURE_FAULT has occurred
SYS_STATE_DBG (80h)
The SYS_STATE_DBG command records the state machine working in digital format. It is for debugging
use.
Command
Format
Bit
Access
Function
Bits
7
6:4
3
7
R
0
SYS_STATE_DBG
Unsigned binary
6
5
4
3
R
R
R
R
CHIP_PWR_ON_STATE
VR_OFF
2
R
1
R
SYS_CRTL_STATE
0
R
Bit Name
Description
RESERVED
Reserved. Reads are always 0.
CHIP_PWR_ON_STATE
MTP restoration status after VCC3V3 powers on.
0x03: MTP copying is complete without errors. Normal operation resumes
0x04: There is an MTP signature or cyclic redundancy check (CRC) error
0x06: A protection occurred and was stored into the MTP during the last VCC3V3
on time
VR_OFF
CRC or MTP fault indicator. If CRC_FAULT_TOT_EN is high and an
MTP_SIGNATURE_FAULT (the first 2 bytes of MTP are not 1234h) or a CRC fault
occurs, this bit is set and latched.
Indicates the state of the chip.
2:0
SYS_CRTL_STATE
0x03: Waiting for VIN to exit under-voltage lockout (UVLO) conditions
0x04: Normal operation
0x07: Protection
FINAL_I2C_ADDR (81h)
The FINAL_I2C_ADDR command returns the final 7-bit I2C slave address, regardless of how the pin or
register is configured.
Command
Format
Bit
Access
Function
Bits
7
6:0
7
R
0
6
R
5
R
FINAL_I2C_ADDR
Unsigned binary
4
3
R
R
FINAL_I2C_ADDR
Bit Name
Description
RESERVED
Not defined. Read-only.
FINAL_I2C_ADDR
Final I2C address of this chip.
2
R
1
R
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
0
R
58
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
REG_LAST_FAULT_MTP (82h)
The REG_LAST_FAULT_MTP command records protections. If PROTECT_FAULT_RECORD_EN
(07h), bit[1] is set high when any one of the eleven protections in PROTECT_SIG_GRP (7Ch) occurs
(except VIN UVLO), PROTECT_SIG_GRP (including the VIN_UVLO bit) are stored into the MTP
addresses (8’hF4 and 8’hF5, FAULT_RECORD bytes).
REG_LAST_FAULT_MTP (82h)
The REG_LAST_FAULT_MTP command records protections. If PROTECT_FAULT_RECORD_EN
(07h), bit[1] is set high when any one of the 11 protections in PROTECT_SIG_GRP (7Ch) occurs (except
VIN UVLO), then PROTECT_SIG_GRP (including the VIN_UVLO bit) is stored to the MTP addresses
(8’hF4 and 8’hF5, FAULT_RECORD bytes).
During the MTP restoration process, including the two FAULT_RECORD bytes (RESTORE_ALL (16h),
RESTORE_S3 (F6h) and Page 2 byte read commands), if the first 2 bytes of the MTP are correct
(16’h1234), then REG_LAST_FAULT_MTP (82h) is updated.
Command
REG_LAST_FAULT_MTP
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Bits
15:0
Bit Name
Description
REG_LAST_FAULT_MTP
Read result of the recorded PROTECT_SIG_GRP (7Ch) in the MTP. Can be
reset by sending a CLR_LAST_FAULT_WMTP command (F1h) on Page 0, Page
1, or Page 3 (not Page 2) when there is no writing or reading to the MTP. It is
updated during MTP restoration, which includes the two FAULT_RECORD MTP
addresses (8’hf4 and 8’hf5), if the first 2 bytes of the MTP are 16’h1234.
READ_VIN (88h)
The READ_VIN command returns the calculated VIN from the ADC sample result on the MP2981’s
VINSEN pin.
Command
READ_VIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
READ_VIN
Bit Name
Description
15:10
RESERVED
Not defined. Read-only.
9:0
READ_VIN
0.125V/LSB.
READ_VOUT (8Bh)
The READ_VOUT command returns the calculated VOUT from the ADC sample result on the VOSEN pin.
Command
READ_VOUT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
0
READ_VOUT
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
59
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
Bits
Bit Name
Description
15:9
RESERVED
Not defined. Read-only.
8:0
READ_VOUT
62.5mV/LSB.
READ_IOUT (8Ch)
The READ_IOUT command returns the calculated IOUT from the ADC sample result on the IMON pin.
Command
READ_IOUT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
5
4
3
2
1
0
R
R
R
R
R
R
READ_IOUT
Bit Name
Description
15:10
RESERVED
Not defined. Read-only.
9:0
READ_IOUT
0.25A/LSB.
READ_TEMP (8Dh)
The READ_TEMP command returns the calculated DrMOS temperature from the ADC sample result on
the TEMP pin.
Command
Format
Bit
Access
Function
7
R
6
R
5
R
Bits
Bit Name
Description
7:0
READ_TEMP
1°C/LSB.
READ_TEMP
Unsigned binary
4
3
R
R
2
R
1
R
0
R
READ_DIE_TEMP (8Eh)
The READ_DIE_TEMP command returns the calculated MP2981 die temperature from the ADC sample
result of the chip’s die temperature sense.
Command
Format
Bit
Access
Function
7
R
6
R
5
R
Bits
Bit Name
Description
7:0
READ_DIE_TEMP
1°C/LSB.
READ_DIE_TEMP
Unsigned binary
4
3
R
R
2
R
1
R
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
0
R
60
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
USER_KEY_INPUT (90h)
The USER_KEY_INPUT command sets the PMBus/I2C password. After 90h is written with the value of
MFR_USER_PWD (44h) and start-up restoration completed, writing Page 0 registers is allowed.
MFR_USER_PWD can be all zeros. This command is write-only. It is not stored in the MTP. After MTP
start-up restoration, send the PMBus command to switch to Page 0, and then set register 90h to be equal
to MFR_USER_PWD.
Command
USER_KEY_INPUT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Function
Bits
Bit Name
Description
15:0
USER_KEY_INPUT
Password for PMBus/I2C communication on Page 0. Set by the user. Write-only.
READ_POUT (96h)
The READ_POUT command returns the monitored output power (POUT) calculated from READ_VOUT
and READ_IOUT. The PSYS pin value comes from this register. If PSYS_SEL_2W (06h), bit[13] is high,
then READ_POUT, bits[10:1] are sent to the internal PSYS DAC. If PSYS_SEL_2W (06h), bit[13] is low,
then READ_POUT, bits[9:0] (READ_POUT, bit[10] = 1 means 10’h3ff) are sent to the DAC. The DAC is
10 bits with a 1.28V range. The DAC output voltage is converted to a current flowing out of PSYS with a
1µA/10mV resolution. Calculate the PSYS current with Equation (20):
PSYS _ CURRENT =
1
1.28V
(μA)
0.01V DAC _IN _10BIT
(20)
Where DAC_IN_10BIT is the 10-bit data inputted into the PSYS DAC.
Command
READ_POUT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
Bits
READ_POUT
Bit Name
Description
15:11
RESERVED
Not defined. Read-only.
10:0
READ_POUT
1W/LSB.
VIN_SENSE (99h)
The VIN_SENSE command returns the MP2981’s VINSEN pin’s 10-bit ADC sample result. Used for
debugging.
Command
VIN_SENSE
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
Bit Name
Description
15:10
RESERVED
Not defined. Read-only.
9:0
VIN_SENSE
VINSEN (V) x 1024 / 1.6 (V).
5
4
3
2
1
0
R
R
R
R
R
R
VIN_SENSE
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
61
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
VOUT_SENSE (9Ah)
The VOUT_SENSE command returns the VOSEN pin’s 10-bit ADC sample result. Used for debugging.
Command
VOUT_SENSE
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
15:10
9:0
VOUT_SENSE
Bit Name
Description
RESERVED
Not defined. Read-only.
VOUT_SENSE
VOSEN (V) x 1024 / 1.6 (V).
IOUT_SENSE (9Bh)
The IOUT_SENSE command returns the IMON pin’s 10-bit ADC sample result. Used for debugging.
Command
IOUT_SENSE
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
15:10
9:0
5
4
3
2
1
0
R
R
R
R
R
R
IOUT_SENSE
Bit Name
Description
RESERVED
Not defined. Read-only.
IOUT_SENSE
VIMON (V) x 1024 / 1.6 (V).
TEMP_SENSE (9Ch)
The TEMP_SENSE command returns the TEMP pin’s 10-bit ADC sample result. Used for debugging.
Command
TEMP_SENSE
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
15:10
9:0
5
4
3
2
1
0
R
R
R
R
R
R
TEMP_SENSE
Bit Name
Description
RESERVED
Not defined. Read-only.
TEMP_SENSE
TEMP (V) x 1024 / 1.6 (V).
DIE_TEMP_SENSE (9Dh)
The DIE_TEMP_SENSE command returns the 10-bit ADC sample result of the chip’s sensed die
temperature. Used for debugging.
Command
DIE_TEMP_SENSE
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
15:10
Bit Name
Description
RESERVED
Not defined. Read-only.
DIE_TEMP_SENSE
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
62
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
The ADC result of the temperature from the internal temperature sensor, typically
by design. DIE_TEMP_SENSE can be calculated with the following equation:
9:0
DIE_TEMP_SENSE
DIE_TEMP_SENSE = INTERNAL_VOLTAGE x 1024 / 1.6
In default mode, the internal temp voltage (mV) = 9.83T (°C) - 109.8. In VBE mode,
voltage (mV) = -1.99T (°C) + 724.0.
TON_PWMP (9Eh)
The TON_PWMP command monitors the output PWMP tON. Used for debugging.
Command
TON_PWMP
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
5
4
3
2
1
0
R
R
R
R
R
R
TON_PWMP
Bit Name
Description
15:10
RESERVED
Not defined. Read-only.
9:0
TON_PWMP
tON for output PWMPs. 5ns/LSB.
TON_SR_PWM (9Fh)
This register monitors the output SR_PWMs tON. Used for debugging.
Command
TON_SR_PWM
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
R
R
R
R
R
R
R
R
R
R
Function
0
0
0
0
0
0
Bits
15:10
9:0
Bit Name
Description
RESERVED
Not defined. Read-only.
TON_SR_PWM
tON for output SR_PWMs. 5ns/LSB.
5
4
3
2
1
0
R
R
R
R
R
R
TON_SR_PWM
CLR_LAST_FAULT_WMTP (F1h)
The CLR_LAST_FAULT_WMTP command writes the 2 FAULT_RECORD bytes of the MTP to 0000h,
and clears the REG_LAST_FAULT_MTP (82h on Page 0) register. It can be sent by Page 0, Page 1, or
Page 3 (not Page 2).
This command is only valid when the MTP is not locked, which means that this command is not a write
protection. When FAULT_SINGLE_EN (07h), bit[3] = 0, sending F1h writes all 32 bytes of the third
section of the MTP (8’hE0 to 8’hFF MTP addresses), but the 2 FAULT_RECORD bytes are written to
0000h. When FAULT_SINGLE_EN = 1, sending F1h only writes the 2 bytes of the MTP, and not all 32
bytes.
READ_LAST_FAULT_TRIG (F2h)
Do not send this command.
CLEAR_STORE_FAULTS (F3h)
The CLEAR_STORE_FAULTS command clears faults. If start-up is paused by MTP_LAST_FAULT (the
data of the 2 FAULT_RECORD bytes in the MTP are not all zeros, or are not found during the start-up
restoration), sending F3h forces the device to continue start-up. The REG_LAST_FAULT_MTP register
(82h) and the 2 bytes in the MTP are not reset by this command. It can be sent by Page 0, Page 1, or
Page 3 (not Page 2).
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
63
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
CLEAR_MTP_FAULTS (F4h)
The CLEAR_MTP_FAULTS command clears MTP faults. If start-up is paused due to an
MTP_SIGNATURE fault (the first 2 bytes of the MTP are not 1234h) or a CRC fault, sending the F4h
command forces the device into the next state (checking REG_LAST_FAULT_MTP (82h)), and start-up
continues.
This command clears all cyclic redundancy check (CRC) errors, clears MTP_SIGN_FAULT, and resets
the DBG_MTP_OK signal (the result to automatically read the MTP after the DBG_MTP command (F7h)
is correct) to 1. It can be sent by Page 0, Page 1, or Page 3 (not Page 2).
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
64
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
TYPICAL APPLICATION CIRCUIT
3.3V
5V
VCC5V
VCC33
PG
PG
SDA
SCL
GND
EN
SDA
SCL
GND
MPC1100A54-0000
EN
VIN
VOUT
VIN
VOUT
GND ADDR PSYS GND
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
65
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
PACKAGE INFORMATION
Surface-Mount (18mmx27mmx6mm)
MPC1100A-54-0000 Rev. 1.0
MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
66
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
CARRIER INFORMATION
1
ABCD
1
1
1
ABCD
ABCD
Pin1
ABCD
Feed Direction
Part Number
Package
Description
Quantity/
Reel
Quantity/
Tube
Reel
Diameter
Carrier
Tape
Width
Carrier
Tape Pitch
MPC1100A-54-0000–Z
Surface-mount
(18mmx27mmx6mm)
300
N/A
13in
44mm
24mm
MPC1100A-54-0000 Rev. 1.0
www.MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
67
MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002
REVISION HISTORY
Revision #
1.0
Revision Date
3/5/2021
Description
Initial Release
Pages Updated
-
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MPC1100A-54-0000 Rev. 1.0
www.MonolithicPower.com
3/5/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
68
工商网监
湘ICP备2023018690号
