MPM3650C
2.75 to 17V, 6A, 1.2MHz, Ultra-Thin,
Synchronous, Step-Down Power Module
with Forced Continuous Conduction Mode
DESCRIPTION
FEATURES
The MPM3650C is a fully integrated highfrequency, synchronous, rectified, step-down
power module with an internal inductor. It offers
a highly compact solution to achieve 6A of
continuous output current (IOUT) across a wide
input voltage (VIN) range, with excellent load and
line regulation. The MPM3650C offers
synchronous mode for high efficiency across the
entire output current load range.
Constant-on-time (COT) control provides fast
transient response, easy loop design, and tight
output regulation.
Full protection features include short-circuit
protection (SCP), over-current protection (OCP),
under-voltage protection (UVP), and thermal
shutdown.
The MPM3650C requires a minimal number of
readily available, standard external components,
and is available in a space-saving QFN-24
(4mmx6mm) package.
Wide 2.75V to 17V Operating Input Voltage
(VIN) Range
Output Current (IOUT):
o 0.6V to 1.8V, 6A IOUT
o 1.8V to 3.3V, 5A IOUT
Internal Power MOSFETs
Adjustable Output from 0.6V
High-Efficiency Synchronous Mode
Forced Continuous Conduction Mode
(FCCM) for Low Output Voltage Ripple
Supports Pre-Biased Start-Up
1200kHz Fixed Switching Frequency (fSW)
Configurable External Soft-Start Time (tSS)
Enable (EN) and Power Good (PG) for
Power Sequencing
Over-Current Protection (OCP) with Hiccup
Mode
Available in a QFN-24 (4mmx6mmx1.6mm)
package
APPLICATIONS
Field-Programmable Gate Array (FPGA)
Power Systems
Optical Modules
Telecommunications
Networking
Industrial Equipment
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
TYPICAL APPLICATION
SW
Efficiency vs. Load
Current vs. Power Loss
VOUT =
1V/6A
VIN
VIN = 12V
VOUT
R1
20kΩ
MPM3650C
PG
FB
R2
30kΩ
EN
SS
AGND
PGND
VCC
C2
EFFICIENCY (%)
C1
100
90
80
70
60
50
40
30
20
10
0
2.5
2
1.5
1
VOUT = 1V
VOUT = 1.8V
VOUT = 3.3V
PlossVOUT=1V
PlossVOUT=1.8V
PlossVOUT=3.3V
0
2
4
0.5
POWER LOSS (W)
BST
2.75V to 17V
0
6
LOAD CURRENT (A)
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
1
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
ORDERING INFORMATION
Part Number*
MPM3650CGQW
Package
QFN-24 (4mmx6mmx1.6mm)
Top Marking
See Below
MSL Rating
3
* For Tape & Reel, add suffix -Z (e.g. MPM3650CGQW-Z).
TOP MARKING
MPS: MPS prefix
Y: Year code
WW: Week code
M3650C: Part number
LLLLLL: Lot number
M: Module
PACKAGE REFERENCE
TOP VIEW
PGND
SW
VIN
PG
24
23
22
21
PGND
1
20
PG
SS
PGND
2
19
PGND
3
18 AGND
PGND
4
17
PGND
5
16
EN
VCC
6
15
BST
SW
7
14
SW
SW
8
13
SW
OUT
9
12
OUT
10
11
OUT
OUT
FB
QFN-24 (4mmx6mmx1.6mm)
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
2
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
PIN FUNCTIONS
Pin #
Name
6
7, 8, 13,
14, 23
9, 10, 11,
12
15
VCC
Description
System ground. The PGND pin is the regulated output voltage’s (VOUT’s) reference
ground. Careful consideration must be taken when designing the PCB layout. Connect
PGND to ground with multiple copper pours and vias.
Internal bias supply output.
1, 2, 3, 4,
5, 24
PGND
SW
Switch output. Float the SW pins.
OUT
Output pin. Connect the OUT pin to the output capacitor (COUT).
BST
16
EN
17
FB
18
AGND
19
SS
20, 21
PG
22
VIN
Bootstrap. Float the BST pin.
Enable. Pull the EN pin high to turn the part on; float EN to turn it off. EN is pulled to AGND
via an internal 1.2MΩ pull-down resistor (REN_PD).
Feedback. To set VOUT, connect the FB pin to the tap of an external resistor divider
connected between the output and AGND.
Signal ground. The AGND pin is not connected internally to the system ground. When
designing the PCB layout, ensure that AGND is connected to the system ground.
Soft start. Connect a capacitor between the SS pin and AGND to set the soft-start time
(tSS) and to avoid start-up inrush current. SS has an internal 22nF capacitor (CSS).
Power good output. The PG pin is an open-drain output. PG’s state changes if one of the
following protections is triggered: under-voltage protection (UVP), over-current protection
(OCP), or over-temperature protection (OTP). PG’s state also changes if an over-voltage
(OV) condition occurs.
Supply voltage. The MPM3650 operates from a 2.75V to 17V input rail. Use a 0.1μF input
capacitor (CIN) in a 0402 package to decouple the input rail. Use wide PCB traces to make
the connection.
ABSOLUTE MAXIMUM RATINGS (1)
VIN .................................................-0.3V to +20V
VSW…………………………………………………..
- 0.3V (-5V < 10ns) to VIN + 0.7V (23V < 10ns)
VBST ...................................................... VSW + 4V
VEN ................................................................. VIN
All other pins ...................................-0.3V to +4V
Continuous power dissipation (TA = 25°C) (2)
…………………………………………….. 3.816W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +125°C
ESD Ratings
Human body model (HBM) .......................... 2kV
Charged device model (CDM).......................2kV
Thermal Resistance
EVM3650C-QW-00A
θJA
θJC
(4)……32.75...10.217
°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation on
EVM3650C-QW-00A board at any ambient temperature is
calculated by PD (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the
maximum allowable power dissipation can cause excessive die
temperature, and the device may go into thermal shutdown.
Internal thermal shutdown circuitry protects the device from
permanent damage.
3) The device is not guaranteed to function outside of its operating
conditions.
4) Measured on EVM3650C-QW-00A, 4-layer PCB.
Recommended Operating Conditions (3)
Supply voltage (VIN) ....................... 2.75V to 17V
Output voltage (VOUT) .................... . 0.6V to 3.3V
Operating junction temp (TJ) .... -40°C to +125°C
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
3
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = -40°C to +125°C (5), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Input voltage
VIN
Supply Current
Shutdown current
ISD
VEN = 0V
Quiescent current
IQ
VEN = 2V, VFB = 0.65V
MOSFET
Switch leakage
ISW_LKG
VEN = 0V, VSW = 7V
Current Limit
Valley current limit
ILIMIT_VALLEY
Short hiccup duty cycle (6)
DHICCUP
Switching Frequency and Minimum On/Off Timer
Switching frequency
fSW
Minimum on time (6)
tON_MIN
Minimum off time (6)
tOFF_MIN
Reference and Soft Start (SS)
TJ = 25°C
Feedback (FB) voltage
VFB
TJ = -40°C to +125°C
FB current
IFB
VFB = 700mV
Soft-start current
ISS_START
Enable (EN) and Under-Voltage Lockout (UVLO)
EN rising threshold
VEN_RISING
EN falling threshold
VEN_FALLING
EN pull-down resistor
REN_PD
VCC
VCC UVLO rising threshold VCC_UVLO_RISING
VCC UVLO threshold
VCC_UVLO_HYS
hysteresis
VCC regulator voltage
VCC
VIN = 5V
VCC load regulation
REGVCC
ICC = 5mA
Power Good (PG)
PG under-voltage (UV)
VPG_UV_RISING
rising threshold
PG UV falling threshold
VPG_UV_FALLING
PG over-voltage (OV) rising
VPG_OV_RISING
threshold
PG OV falling threshold
VPG_OV_FALLING
PG delay
tDELAY_PG
Both edges
PG sink current capability
VPG_SINK
4mA sink
PG leakage current
IPG_LEAK
VPG = 5V
Thermal Protection
Thermal shutdown (6)
TSD
Thermal hysteresis (6)
TSD_HYS
Min
2.75
Typ
Max
17
Units
V
2
100
5
150
µA
µA
5
µA
6
7
10
0.9
1.2
50
100
1.6
594
591
600
600
10
6
606
609
50
8
1.19
0.96
1.23
1
1.2
1.27
1.04
V
V
MΩ
2.4
2.5
2.6
V
4
A
%
MHz
ns
ns
mV
nA
µA
200
mV
3.5
3
V
%
0.85
0.9
0.95
VFB
0.75
0.8
0.85
VFB
1.15
1.2
1.25
VFB
1.05
1.1
50
1.15
VFB
µs
V
μA
0.4
10
150
20
°C
°C
Notes:
5) Not tested in production. Guaranteed by over-temperature correlation.
6) Guaranteed by design and characterization testing.
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
4
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT = 1V, COUT = 4x22µF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Efficiency vs. Load Current
VOUT = 1.8V
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
VOUT = 1V
70
60
50
VIN=5V
VIN=12V
VIN=17V
40
30
70
60
50
40
VIN=5V
VIN=12V
VIN=17V
30
20
20
0
1
2
3
4
5
0
6
1
2
3
4
LOAD CURRENT (A)
Efficiency vs. Load Current
Load Regulation
VOUT = 3.3V
VOUT = 1V
100
1
90
0.8
LOAD REGULATION (%)
EFFICIENCY (%)
LOAD CURRENT (A)
80
70
60
50
40
VIN=5V
VIN=12V
VIN=17V
30
20
0
2
4
0.4
0.2
0
-0.2
-0.4
VIN=5V
VIN=12V
VIN=17V
-0.6
-0.8
-1
6
0
1
2
Load Regulation
VOUT = 1.8V
VOUT = 3.3V
1
0.8
LOAD REGULATION (%)
LOAD REGULATION (%)
3
0.6
0.4
0.2
0
-0.2
-0.4
VIN=5V
VIN=12V
VIN=17V
-1
0
1
2
3
4
LOAD CURRENT (A)
4
5
6
LOAD CURRENT (A)
Load Regulation
-0.8
6
0.6
LOAD CURRENT (A)
-0.6
5
5
6
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
VIN=5V
VIN=12V
VIN=17V
0
1
2
3
4
5
LOAD CURRENT (A)
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
5
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1V, COUT = 4x22µF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Line Regulation
Line Regulation
VOUT = 1.8V
1
1
0.8
0.8
0.6
0.6
LINE REGULATION (%)
LINE REGULATION (%)
VOUT = 1V
0.4
0.2
0
-0.2
-0.4
-0.6
Iout=0.01A
Iout=3A
-0.8
-1
0.4
0.2
0
-0.2
-0.4
-0.6
Iout=0.01A
Iout=3A
-0.8
-1
3
5
7
9
11
13
15
17
3
5
7
INPUT VOLTAGE (V)
11
13
15
17
INPUT VOLTAGE (V)
Line Regulation
Case Temperature vs. Load Current
VOUT = 3.3V
VOUT = 1V, TA = 15°C
90
1
CASE TEMPERATURE (℃)
0.8
LINE REGULATION (%)
9
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
Iout=0.01A
Iout=2.5A
-0.8
-1
80
70
60
50
40
Vin=5V
Vin=12V
Vin=17V
30
20
3
5
7
9
11
13
15
17
1
2
INPUT VOLTAGE (V)
3
4
5
6
LOAD CURRENT (A)
Case Temperature vs. Load Current
Case Temperature vs. Load Current
VOUT = 1.8V, TA = 15°C
VOUT = 3.3V, TA = 15°C
95
CASE TEMPERATURE (℃)
CASE TEMPERTURE (℃)
80
85
75
65
55
45
VIN=5V
VIN=12V
VIN=17V
35
25
1
2
3
4
LOAD CURRENT (A)
5
70
60
50
40
Vin=5V
Vin=12V
Vin=17V
30
20
6
1
2
3
4
5
6
LOAD CURRENT (A)
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Thermal Derating
Thermal Derating
VIN = 5V, no airflow
VIN = 12V, no airflow
7
7
6
6
LOAD CURRENT (A)
LOAD CURRENT (A)
VIN = 5V, VOUT = 1V, COUT = 4x22µF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
5
4
3
VIN=5V,VOUT=1V
2
VIN=5V,VOUT=1.8V
1
VIN=5V,VOUT=3.3V
0
5
4
3
VIN=12V,VOUT=1V
2
VIN=12V,VOUT=1.8V
1
VIN=12V,VOUT=3.3V
0
45
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
115
45
55
65
75
85
95
105
115
AMBIENT TEMPERATURE (°C)
MPM3650C Rev. 1.1
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9/24/2021
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1V, COUT = 4x22µF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
VOUT Ripple
VOUT Ripple
IOUT = 0A
IOUT = 6A
CH1:
VOUT/AC
5mV/div.
CH1:
VOUT/AC
5mV/div.
1μs/div.
1μs/div.
Load Transient
Load Transient
IOUT = 0A to 3A
IOUT = 3A to 6A
CH1:
VOUT/AC
20mV/div.
CH1:
VOUT/AC
20mV/div.
CH4: IOUT
2A/div.
CH4: IOUT
2A/div.
80μs/div.
80μs/div.
Start-Up through VIN
Start-Up through VIN
IOUT = 0A
IOUT = 6A
CH1: VOUT
1V/div.
CH1: VOUT
1V/div.
CH2: VSW
5V/div.
CH2: VSW
5V/div.
CH3: VIN
5V/div.
CH3: VIN
5V/div.
CH4: IOUT
5A/div.
CH4: IOUT
5A/div.
10ms/div.
10ms/div.
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
8
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1V, COUT = 4x22µF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Shutdown through VIN
Shutdown through VIN
IOUT = 0A
IOUT = 6A
CH1: VOUT
1V/div.
CH1: VOUT
1V/div.
CH2: VSW
5V/div.
CH2: VSW
5V/div.
CH3: VIN
5V/div.
CH3: VIN
5V/div.
CH4: IOUT
5A/div.
CH4: IOUT
5A/div.
10ms/div.
10ms/div.
Start-Up through EN
Start-Up through EN
IOUT = 0A
IOUT = 6A
CH1: VOUT
1V/div.
CH1: VOUT
1V/div.
CH2: VSW
5V/div.
CH2: VSW
5V/div.
CH3: VEN
2V/div.
CH3: VEN
2V/div.
CH4: IOUT
5A/div.
CH4: IOUT
5A/div.
4ms/div.
10ms/div.
Shutdown through EN
Shutdown through EN
IOUT = 0A
IOUT = 6A
CH1: VOUT
1V/div.
CH1: VOUT
1V/div.
CH2: VSW
5V/div.
CH2: VSW
5V/div.
CH3: VEN
2V/div.
CH3: VEN
2V/div.
CH4: IOUT
5A/div.
CH4: IOUT
5A/div.
2ms/div.
10ms/div.
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
9
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT = 1V, COUT = 4x22µF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Steady State
SCP Entry and Recovery
CH1: VOUT
1V/div.
CH1: VOUT
1V/div.
CH2: VSW
5V/div.
CH3: VIN
5V/div.
CH4: IOUT
2A/div.
CH4: IOUT
10A/div.
20ms/div.
200ms/div.
MPM3650C Rev. 1.1
MonolithicPower.com
9/24/2021
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© 2021 MPS. All Rights Reserved.
10
MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
FUNCTIONAL BLOCK DIAGRAM
VIN
Bias and
Voltage
Reference
EN
1.2MΩ
Bootstrap
Regulator
BST
LDO
VCC
HS-FET
Driver
ISS
Main
Switch
(NCH)
EAO
SS
SW
EA
22nF
On
Timer
AGND
Logic
Control
VCC
0.5μH
VOUT
VFB+RAMP
FB
BUF
LS-FET
Driver
Ramp
PWM
90% of VREF Rising
80% of VREF Falling
Current
Modulator
Synchronous
Rectifier (NCH)
Current-Sense
Amplifier
PG
110% of VREF Rising
GND
120% of VREF Falling
Figure 1: Functional Block Diagram
MPM3650C Rev. 1.1
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
OPERATION
The MPM3650C is a fully integrated,
synchronous, rectified, step-down power module.
Constant-on-time (COT) control provides fast
transient response and easy loop stabilization.
Figure 2 shows the MPM3650C’s simplified
ramp compensation block.
interval, which is determined by the one-shot ontimer. Once the HS-FET turns off, the LS-FET
turns on and remains on until the next period.
Figure 3 shows FCCM operation.
tON is constant
Whenever VFB+RAMP
drops below VEAO, the
HS-FET turns on
VFB
FB+RAMP
VREF
OnTimer
BUF
RAMP
Logic
Control
L
VOUT
SW
RESR
COUT
Ramp
Generator
PWM
R1
R2
Figure 2: Simplified Ramp Compensation Block
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns on once the feedback
(FB) voltage (VFB) drops below the reference
voltage (VREF), and indicates there is an
insufficient output voltage (VOUT). The on time
(tON) is determined by both VOUT and the input
voltage (VIN) to make the switching frequency
(fSW) fairly constant across the entire VIN range.
After tON elapses, the HS-FET turns off. Once VFB
drops below VREF, it turns on again. The
converter regulates VOUT by repeating this
operation. The integrated low-side MOSFET
(LS-FET) turns on once the HS-FET turns off to
minimize conduction loss. If both the HS-FET
and LS-FET are on at the same time, a dead
short occurs between input and PGND. This is
called shoot-through. To avoid shoot-through, a
dead-time (DT) is internally generated between
the HS-FET off time (tOFF) and LS-FET tON, and
vice versa.
Figure 3: FCCM Operation
During FCCM, the fSW is fairly constant. This
constant fSW during FCCM is called pulse-width
modulation (PWM) mode.
VCC Regulator
The 3.5V internal regulator powers most of the
internal circuitries. This regulator takes the VIN
input and operates across the full VIN range. If VIN
exceeds 3.5V, the regulator output is in full
regulation. If VIN drops below 3.5V, the regulator
output decreases following VIN. The device
includes an internal, 1μF decoupling ceramic
capacitor.
Enable (EN)
EN is a digital control pin that turns the converter
on and off. Drive EN above 1.23V to turn the
converter on; drive EN below 1V to turn it off.
When floating EN, pull EN down to AGND via an
internal 1.2MΩ resistor.
EN can be connected directly to the VIN pin. It
supports a VIN range up to 17V.
Internal compensation is applied during COT
control to ensure stable operation even when
ceramic capacitors are being used as the output
capacitors. This internal compensation improves
the jitter performance without affecting the line or
load regulation.
Under-Voltage Lockout (UVLO) Protection
Under-voltage lockout (UVLO) protects the
MPM3650C from operating at an insufficient
supply voltage. The UVLO comparator monitors
the output voltage of the internal regulator VCC.
The VCC UVLO rising threshold is about 2.5V,
and its falling threshold is about 2.3V.
Forced Continuous Conduction Mode (FCCM)
The MPM3650C can operate in forced
continuous conduction mode (FCCM). If
VFB+RAMP drops below the error amplifier output
(VEAO), then the HS-FET turns on for a fixed
Once VIN exceeds the UVLO rising threshold
voltage, the MPM3650C starts up. If VIN drops
below the UVLO falling threshold, the device
shuts down. UVLO is a non-latch protection.
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
CSS (nF) 0.83
t SS (ms) ISS (μA)
VREF (V)
(1)
The MPM3650C has an internal, 22nF soft start
capacitor. If the output capacitor (COUT) has a
large capacitance, it is not recommended to set
the soft-start time (tSS) too short, or else the
device could too easily reach the current limit
during SS.
Power Good (PG) Indicator
The PG pin is the open drain of a MOSFET that
connects to VCC or another voltage source via a
resistor (e.g. 100kΩ). If VIN is applied before SS
completes, then the MOSFET turns on and the
PG pin is pulled to PGND. Once VFB reaches 90%
of VREF, PG is pulled high after a 50μs delay.
Once VFB drops below 80% of VREF, PG is pulled
low.
If UVLO or over-temperature protection (OTP)
occurs, PG is pulled low. If an over-current (OC)
condition occurs and VFB drops below 80% of
VREF, PG is pulled low after a 0.05ms delay. If an
over-voltage (OV) condition occurs and VFB
exceeds 120% of VREF, PG is pulled low after a
0.05ms delay. If VFB drops below 110% of VREF,
PG is pulled high after a 0.05ms delay.
If the input supply fails to power the MPM3650C,
PG is clamped low, even if PG is tied to an
external DC source via a pull-up resistor. Figure
4 shows the relationship between the PG voltage
(VPG) and the pull-up current.
1.2
PG CLAMPED VOLTAGE (V)
Soft Start (SS)
The MPM3650C employs soft start (SS) to
ensure that the output ramps up smoothly during
start-up. If the EN pin goes high, an internal
current source (6μA) charges the SS capacitor
(CSS). As the device starts up, the SS voltage
(VSS) takes over VREF to the PWM comparator.
VOUT ramps up smoothly with VSS. VSS continues
to ramp up until VSS = VREF, at which point VREF
takes over. Then SS finishes, and the device
enters steady state operation. The SS
capacitance (CSS) can be calculated with
Equation (1):
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
PULL-UP CURRENT (mA)
Figure 4: Clamped VPG vs. Pull-Up Current
Over-Current Protection (OCP) and ShortCircuit Protection (SCP)
The MPM3650C offers valley limit control. The
LS-FET monitors the current flow through itself.
The HS-FET waits until the valley current limit is
not triggered before turning on again. VOUT
decreases until VFB drops below the undervoltage (UV) threshold (typically 50% VREF).
Once a UV fault occurs, the MPM3650C enters
hiccup mode to periodically restart the part.
During over-current protection (OCP), the device
tries to recover from an OC fault using hiccup
mode. OCP includes short-circuit protection
(SCP). The MPM3650C disables the output
power stage, discharges CSS, and initiates a SS.
If the OC condition remains after SS is complete,
the device repeats this operation until the OC
condition disappears, and the output rises back
to its regulation level. OCP is a non-latch
protection.
Pre-Biased Start-Up
The MPM3650 is designed for monotonic startup into pre-biased loads. If the output is prebiased to a certain voltage during start-up, and
the bootstrap (BST) voltage (VBST) is refreshed
and charged, then the VSS is also charged. If VBST
exceeds its rising threshold and VSS exceeds the
sensed VOUT at the FB pin, the part resumes
normal operation.
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures. If
the silicon die temperature exceeds 150°C, the
MPM3650C shuts down. Once the temperature
drops below its lower threshold (typically 130°C),
the chip starts up again.
Start-Up and Shutdown Circuit
If both VIN and the EN voltage (VEN) exceed their
respective thresholds, the chip starts up. The
reference block starts up first to generate a
stable VREF and currents. Then the internal
regulator starts up to provide a stable supply for
the remaining circuits.
Three events can shut down the chip: EN going
low, VIN going low, and thermal shutdown. The
shutdown procedure first blocks the signaling
path to avoid any fault triggering, then the
internal supply rail is pulled down to ground.
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
APPLICATION INFORMATION
COMPONENT SELECTION
Setting the Output Voltage
The external resistor divider sets VOUT. First,
choose a value for R2. Too small of an R2 value
leads to considerable quiescent current (IQ) loss,
while too large an R2 value makes FB noise
sensitive. It is recommended that R2 be between
2kΩ and 100kΩ. Typically, set the current
flowing through R2 below 250μA to balance
system stability and minimize load loss. Then R1
can be calculated with Equation (2):
V VREF
R1 OUT
R2
VREF
(2)
VOUT
RT
R1
CF
ICIN
IOUT
V
V
OUT (1 OUT )
fSW CIN
VIN
VIN
(5)
The worst-case scenario occurs at VIN = 2 x VOUT,
which can be calculated with Equation (6):
Table 1 shows recommended resistor values for
common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
CF (pF)
39
39
39
39
39
(4)
For simplification, choose CIN to have an RMS
current rating greater than half of the maximum
load current (ILOAD).
VIN
Figure 5: Feedback Network
R2 (kΩ)
30
20
13
10
6.34
IOUT
2
∆VIN ripple can be estimated with Equation (5):
R2
R1 (kΩ)
20
20
20
20
20
(3)
The worst-case scenario occurs at VIN = 2 x VOUT,
which can be calculated with Equation (4):
FB
VOUT (V)
1
1.2
1.5
1.8
2.5
VOUT
V
(1 OUT )
VIN
VIN
ICIN IOUT
The input capacitance determines the
converter’s input voltage ripple (∆VIN). If the
system has an ∆VIN requirement, choose an
input capacitor that meets the relevant
specifications.
Figure 5 shows the feedback circuit.
MPM3650C
ripple current. The input ripple current (ICIN) can
be estimated with Equation (3):
RT (Ω)
0
0
0
0
0
Selecting the Input Capacitor (CIN)
The step-down converter has a discontinuous
input current (IIN), and requires a capacitor to
supply the AC current to the converter while
maintaining the DC VIN. Ceramic capacitors are
recommended for the best performance, and
should be placed as close to the VIN pin as
possible. Capacitors with X5R and X7R ceramic
dielectrics are recommended for their stability
amid temperature fluctuations.
VIN
I
1
OUT
4 fSW CIN
(6)
Selecting the Output Capacitor (COUT)
The output capacitor (COUT) is required to
maintain the DC VOUT. Ceramic or POSCAP
capacitors are recommended. The output
voltage ripple (∆VOUT) can be calculated with
Equation (7):
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (7)
fSW L
VIN
8 fSW COUT
With ceramic capacitors, the capacitance
dominates the impedance at fSW, and causes
most of ∆VOUT.
For simplification, ∆VOUT can be estimated with
Equation (8):
VOUT
VOUT
V
(1 OUT )
8 fSW L COUT
VIN
2
(8)
The capacitor should have a ripple current rating
greater than the converter’s maximum input
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
With POSCAP capacitors, the ESR dominates
the impedance at fSW.
4. Keep the paths between CIN and VIN as short
and wide as possible.
For simplification, ∆VOUT can be estimated with
Equation (9):
5. Place a VCC decoupling capacitor close to
the IC.
VOUT
VOUT
V
(1 OUT ) RESR
fSW L
VIN
(9)
In addition to accounting for the output ripple, a
larger-value COUT provides better load transient
response. However, if COUT is too large, VOUT is
unable to reach the design value during the softstart time (tSS), and the device will fail to regulate.
The maximum output capacitor value (CO_MAX)
can be estimated with Equation (10):
COUT_MAX = (ILIM_AVG) x tSS / VOUT
(10)
Where ILIM_AVG is the average start-up current
during the soft-start period.
PCB Layout Guidelines (7)
Efficient PCB layout is critical for stable
operation. A 4-layer layout is recommended to
improve thermal performance. For the best
results, refer to Figure 6 and follow the
guidelines below:
6. Connect AGND and PGND at the VCC
capacitor’s ground connection.
7. Connect VIN, VOUT, and PGND to a large
copper area to improve thermal performance
and long-term reliability.
8. Connect the PGND areas at the internal
layers and bottom layer with multiple vias.
9. Ensure that there is a complete ground plane
on either the internal layer or the bottom layer.
10. Place all signal traces far away from SW.
11. Connect the power planes to the internal
layers with multiple vias.
Top Layer
3. Place the ceramic input capacitor, especially
the small package size (0402) input bypass
capacitor, as close to the VIN and PGND
pins as possible to minimize high-frequency
noise.
VOUT
2
2
2
Via
Pads
1
C3
C2
1. Keep the power loop as small as possible.
2. Connect a large ground plane directly to
PGND. If the bottom layer is a ground plane,
add vias near PGND.
VIN
GND
1
C4
1
C5
GND
Figure 6: Recommended PCB Layout
Note:
7) The recommended layout is based on Figure 7 (see the Typical
Application Circuits section on page 17).
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
C2
0.1μF
R1
499kΩ
16
R2
NS
1, 2, 3,
4, 5, 24
6
R4
GND
20, 21
100kΩ
C5 (optional)
1μF
BST 15
C1
22μF x 2
VIN
VIN =
2.75V to 17V
22
TYPICAL APPLICATION CIRCUITS
9, 10,
11, 12
VOUT = 1V
EN
C3
22μF x 4
C4
0.1μF
PGND
VCC
MPM3650C
SW
GND
7, 8,13,
14, 23
R3
20kΩ
PG
FB
SS
17
AGND
19
OUT
R6
0Ω
R5
30kΩ
18
AGND
C9
39pF
R7
0Ω
AGND
AGND
AGND
GND
C2
0.1μF
R1
499kΩ
16
R2
NS
1, 2, 3,
4, 5, 24
6
R4
GND
20, 21
100kΩ
C5 (optional)
1μF
BST 15
C1
22μF x 2
VIN
VIN =
2.75V to 17V
22
Figure 7: Typical Application Circuit (1V Output)
VOUT = 1.8V
C3
22μF x 4
C4
0.1μF
PGND
VCC
MPM3650C
SW
GND
7, 8,13,
14, 23
R3
20kΩ
PG
FB
SS
17
C9
39pF
R6
0Ω
R5
10kΩ
18
AGND
9, 10,
11, 12
EN
AGND
19
OUT
R7
0Ω
AGND
AGND
AGND
GND
Figure 8: Typical Application Circuit (1.8V Output)
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
C2
0.1μF
R1
499kΩ
16
R2
NS
1, 2, 3,
4, 5, 24
6
R4
GND
20, 21
100kΩ
C5 (optional)
1μF
BST 15
C1
22μF x 2
VIN
VIN =
2.75V to 17V
22
TYPICAL APPLICATION CIRCUITS (continued)
VOUT = 2.5V
C3
22μF x 4
C4
0.1μF
PGND
VCC
MPM3650C
SW
GND
7, 8,13,
14, 23
R3
63.4kΩ
PG
FB
SS
17
C9
39pF
R6
0Ω
R5
20kΩ
18
AGND
9, 10,
11, 12
EN
AGND
19
OUT
R7
0Ω
AGND
AGND
AGND
GND
Figure 9: Typical Application Circuit (2.5V Output)
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
PACKAGE OUTLINE DRAWING FOR 24L FCMQFN (4X6MM)
MF-PO-D-0441 revision 0.0
PACKAGE INFORMATION
QFN-24 (4mmx6mmx1.6mm)
PIN 1 ID
0.25X45ºTYP
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.25X45º
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
3) JEDEC REFERENCE IS MO-220.
4) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
CARRIER INFORMATION
Pin1
1
1
ABCD
1
1
ABCD
ABCD
ABCD
Feed Direction
Quantity/ Quantity/
Reel
Carrier
Carrier
Reel
Tube
Diameter Tape Width Tape Pitch
MPM3650CGQW-Z QFN-24 (4mmx6mmx1.6mm)
2500
N/A
13in
12mm
8mm
Part Number
Package Description
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MPM3650C – 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE
REVISION HISTORY
Revision # Revision Date Description
Pages Updated
1.0
12/22/2020
Initial Release
Updated the efficiency curve
1
Updated “–Z” to “-Z” in the Ordering Information and Carrier
2, 20
Information sections
Updated the step numbers in the PCB Layout Guidelines section
16
1.1
9/24/2021
Updated the VIN and PGND pin numbers
17–18
Grammar and formatting updates; updated pagination; updated
page headers; added technical abbreviations and shorthand
All
(e.g. VOUT, VREF, CSS, ∆VIN, fSW, etc.)
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
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