MPM3695GBH-100-0001

MPM3695-100 16V, 100A, Scalable, DC/DC Power Module with PMBus DESCRIPTION FEATURES The MPM3695-100 is a 100A, scalable, fully integrated power module with a PMBus interface. The device offers a complete power solution that achieves up to 100A of output current, with excellent load and line regulation across a wide input voltage range. The MPM3695-100 operates at a high efficiency across a wide load range, and can be paralleled to deliver up to 800A of current.  By integrating four interleaved phases in a single molded power module, the MPM3695-100 adopts MPS’s proprietary, multi-phase constanton-time (MCOT) control to provide ultra-fast transient response and simple loop compensation. The PMBus interface provides module configurations and monitoring of key parameters. Full protection features include over-current protection (OCP), over-voltage protection (OVP), under-voltage protection (UVP), and over-temperature protection (OTP).            The MPM3695-100 requires a minimal number of readily available, external components. It is available in a BGA (15mmx30mmx5.18mm) package.  3.2V to 16V Input Voltage Range with External 3.3V VCC Bias 4V to 16V Input Voltage Range with Internal VCC Bias 0.5V to 3.3V Output Voltage Range 100A Continuous Current for Outputs Up to 1.8V 60A Continuous Current for 3.3V Output Parallelable Up to 800A with Active Curernt Balancing Auto-Interleaving for Parallel Operation Output Voltage Remote Sensing ±1% Reference Voltage Accuracy (-40°C to +125°C) PMBus 1.3 Compliant Telemetry Readback including VIN, VOUT, IOUT, Temperature, and Faults Configurable via the PMBus: o Output Voltage o Soft-Start Time o Over-Current (OC), Over-Temperature (OT), Over-Voltage (OV), Under-Voltage (UV), Under-Voltage Lockout (UVLO) Limits o PWM Mode o Switching Frequency Available in a BGA (15mmx30mmx5.18mm) Package APPLICATIONS     Telecom and Networking Systems Industrial Equipment Servers and Computing FPGA and ASIC Core Power All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 1 MPM3695-100 – 16V, 100A, SCALABLE, DC/DC POWER MODULE WITH PMBUS TYPICAL APPLICATION Efficiency vs. Load Current 10kΩ VIN 22µF x 8 25V CTRL VIN = 12V, with external 3.3V V CC 1.2V Output 100A 100 VOUT MPM3695-100 CTRL 1kΩ VOSNS+ PG 1kΩ 33nF 100µF x 4 ALT SCL SDA EFFICIENCY (%) 4V to 16V Input 95 90 85 80 75 70 RADDR 65 RUN VOUT=0.75V,Fsw=600KHz VOUT=1V,Fsw=600KHz VOUT=1.2V,Fsw=600KHz VOUT=1.8V,Fsw=800KHz VOUT=3.3V,Fsw=1000KHz 0 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (A) Figure 1: Typical Application Circuit for Single-Module Operation at 1.2V Output MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 2 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS ORDERING INFORMATION Part Number* MPM3695GBH-100-xxxx** MPM3695GBH-100-0001 EVKT-MPM3695-100A EVKT-MPM3695-200A EVKT-MPM3695-400A Package BGA (15mmx30mmx5.18mm) BGA (15mmx30mmx5.18mm) - Top Marking See Below See Below - MSL Rating 3 3 - * Add –T for tray package (e.g. MPM3695GBH-100-0001–T). ** The 4-digit suffix code “-xxxx” is the configuration identifier for the register settings stored in the non-volatile memory (NVM) of the power module. The default configuration code is “-0001”. For customized configurations, contact an MPS FAE to assign a 4-digit suffix code. TOP MARKING MPS: MPS prefix YY: Year code WW: Week code M3695-100: Part number LLLLLLLLL: Lot number M: Module MPM3695-100 EVALUATION KIT Evaluation kit contents (items listed below can be ordered separately, and the GUI installation file and supplemental documents can be downloaded from the MPS website): EVKT-MPM3695-100A: Single-Module Operation # Part Number Item Qty 1 EVM3695-100-BH-00A MPM3695GBH-100 evaluation board for single-module operation 1 2 EVKT-USBI2C-02 USB to I2C communication interface device, USB cable, and ribbon cable 1 EVKT-MPM3695-200A: Dual-Module Operation # Part Number Item 1 EVM3695-100-BH-00B MPM3695GBH-100 evaluation board for dual-module operation 1 2 EVKT-USBI2C-02 USB to I2C communication interface device, USB cable, and ribbon cable 1 MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Qty 3 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS EVKT-MPM3695-400A: Four-Module Operation # Part Number Item Qty 1 EVM3695-100-BH-00C MPM3695GBH-100 evaluation board for four-module operation 1 2 EVKT-USBI2C-02 USB to I2C communication interface device, USB cable, and ribbon cable 1 Input Power Supply Input Virtual Bench V3.0 USB Cable USB to I2C Communication Interface EVKT-USBI2C-02 EVM3695-100 Evaluation Board Ribbon Cable Output Load Figure 2: Evaluation Board Set-Up MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 4 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS PACKAGE REFERENCE 1 2 3 TOP VIEW 4 5 6 7 8 9 10 11 VOSNS+VOSNS- CTRL ISUM< A B VOUT ADDR ADDR VCC VCC ADDR ADDR VCC VCC VIN C D SET< TAKE RUN E PG F GND G VIN H VOUT J K TP1 L TP2 M N VIN P R VOUT T TP3 U GND TP4 V W VIN Y AA VOUT ALT SET> AB AC SCL SDA GND ISUM> GND PASS TP5 BGA (15mmx30mmx5.18mm) MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 5 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS PIN NUMBER LIST Table 1: Pins A1~E11 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Name VOUT VOUT VOUT VOSNS+ VOSNSCTRL ISUM< GND VIN VIN VIN Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Name VOUT VOUT VOUT ADDR ADDR VCC VCC GND VIN VIN VIN Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Name VOUT VOUT VOUT ADDR ADDR VCC VCC GND GND GND GND Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Name VOUT VOUT VOUT GND GND GND GND GND GND GND GND Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Name GND GND GND GND GND GND GND SET< TAKE RUN GND Pin J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 Name VOUT VOUT VOUT GND GND GND GND GND GND GND GND Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 Name VOUT VOUT VOUT GND GND GND GND GND GND GND GND Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 Name VOUT VOUT VOUT GND GND GND GND GND VIN VIN VIN Pin R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Name VOUT VOUT VOUT GND GND GND GND GND GND GND GND Table 2: Pins F1~K11 Pin F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 Name GND GND GND GND GND GND GND GND GND PG GND Pin G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 Name VOUT VOUT VOUT GND GND GND GND GND VIN VIN VIN Pin H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 Name VOUT VOUT VOUT GND GND GND GND GND VIN VIN VIN Table 3: Pins L1~R11 Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 Name GND GND GND GND GND GND GND GND GND TP1 GND Pin M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 Name GND GND GND GND GND GND GND GND GND TP2 GND Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 Name GND GND GND GND GND GND GND GND VIN VIN VIN MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 6 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS Table 4: Pins T1~Y11 Pin T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Name VOUT VOUT VOUT GND GND GND GND GND GND GND GND Pin U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 Name VOUT VOUT VOUT GND GND GND GND GND GND TP3 GND Pin V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 Name GND GND GND GND GND GND GND GND GND TP4 GND Pin W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 Name GND GND GND GND GND GND GND GND VIN VIN VIN Pin AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 Name VOUT VOUT VOUT SCL SDA GND ISUM> GND PASS TP5 GND Pin Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Name VOUT VOUT VOUT GND GND GND GND GND VIN VIN VIN Table 5: Pins AA1~AC11 Pin AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 Name VOUT VOUT VOUT GND GND GND GND GND GND GND GND Pin AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 Name VOUT VOUT VOUT GND ALT GND GND SET> GND GND GND MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 7 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS PIN FUNCTIONS Name VIN VOUT Description Supply voltage. This pin provides power to the module. Decoupling capacitors must be connected between VIN and GND. Module output voltage node. Connect VOUT to a wide PCB copper plane. GND Power ground. Connect all GND pins together on a copper plane. Output of the internal 3.3V LDO. Connect all four VCC pins together for single-phase operation. For VCC parallel operation, connect the VCC pins of the master phase and slave phases together. Converter control. CTRL is a digital input that turns the regulator on and off. Drive CTRL high to turn CTRL the regulator on; drive CTRL low to turn it off. Do not float this pin. For parallel operation, connect the CTRL pins of the master and slave phases together. Output voltage sense negative return. Connect this pin directly to the GND sense point of the load. VOSNS- Short VOSNS- to GND if remote sense is not used. For parallel operation, connect the VOSNS- pins of the master and slave phases together. Output voltage sense positive return. Connect this pin to the output voltage (VOUT) sense positive VOSNS+ side to provide a feedback voltage (VFB) to the system. For parallel operation, connect the VOSNS+ pins of the master and slave phases together. Multi-purpose power good output. For the PG pin to pull high and indicate whether VOUT has PG exceeded 90% of the nominal voltage, a pull-up resistor must be connected to a DC voltage. There is a delay from PG going from low to high. Do not float this pin. Passes trigger signal to the TAKE pin. Connect the PASS and TAKE pins for single-phase operation. PASS For multi-phase operation, see the Typical Application Circuits section on page 47. Receives trigger signal from PASS pin or RUN signal. Pull the TAKE pin of the master phase to TAKE 3.3V. Connect the PASS and TAKE pins for single-phase operation. For multi-phase operation, see the Typical Application Circuits section on page 47. Trigger signal for slave phases. Keep this pin floating for single-phase operation. For multi-phase RUN operation, see the Typical Application Circuits section on page 47. PWM signal setting. The SET< and SET> pins are connected internally. Float the SET< and SET> SET slave phases together. Use either the SET< or SET> pin to connect to other MPM3695-100 devices Reference current output. The ISUM< and ISUM> pins are connected internally. Float the ISUM< ISUM pins for single-module operation. For multi-module operation, connect the ISUM of the ISUM> master and slave phases together. Use either the ISUM< or ISUM> pin to connect to other MPM3695100 devices. SCL PMBus serial clock. SDA PMBus serial data. PMBus alert. Open-drain output, active low. A pull-up resistor must be connected from ALT to a 3.3V ALT rail. PMBus address setting pins. Connect all four ADDR pins together. Connect a resistor from the ADDR ADDR pins to GND to set the device’s address. For parallel operation, the same address should be selected for all modules. TP1~TP5 Test pins. Float these pins. Do not connect them. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 8 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS θJA θJC ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply voltage (VIN) ..................................... 18V VOUT ........................................................... 5.5V VCC ............................................................. 4.5V VCC (1s) (2) ..................................................... 6V All other pins ................................-0.3V to +4.3V All other pins (1s) (2) ....................................... 6V Continuous power dissipation (TA = 25°C) (3) ............................................................... 24.95W Junction temperature ................................170°C Storage temperature ................ -65°C to +170°C BGA (15mmx30mmx5.18mm) EVM3695-100-BH-00A (6) ..... 5.77 .... 0.74 . °C/W JESD51-7 (7) ......................... 10.3 ..... 7.7 .. °C/W ESD Ratings Human body model (HBM) ................... ±1000V Charged device model (CDM)..................±750V Recommended Operating Conditions (4) Supply voltage (VIN) ............................ 4V to 16V Supply voltage (VIN) (5)...................... 3.2V to 16V Output voltage (VOUT) ...................... 0.5V to 3.3V External VCC bias ............................... 3V to 3.6V Operating junction temp (TJ) .... -40°C to +125°C Notes: 1) Exceeding these ratings may damage the device. 2) Voltage rating during MTP programming. 3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ (MAX), the junction-toambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can produce an excessive die temperature. 4) The device is not guaranteed to function outside of its operating conditions. 5) An external 3.3V VCC bias is required. Writing to MTP memory is not supported with an external 3.3V VCC bias. 6) Measured on EVM3695-100-BH-00A, 25cmx15cm, 6-layer PCB. 7) The value of θJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 9 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS ELECTRICAL CHARACTERISTICS VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Parameters VIN Supply Current Shutdown supply current Input Voltage Input voltage range Output Voltage (8) Output voltage range (8) Load regulation (8) Line regulation (8) Symbol Condition IIN VCTRL = 0V VIN Internal VCC With external 3.3V VCC VOUT_RANGE VOUT_DC_LOAD IOUT from 0A to 100A VIN from 4V to 16V, VOUT_DC_LINE IOUT = 100A Min Typ Max Units 10 16 mA 4 3.2 16 16 V V 0.5 3.3 V ±0.5% VOUT ±0.5% VOUT 27 A 1.5 A 27 A -13 A Current Limit Individual valley current limit ILIM Individual phase current limit; D7h, bits[4:0] = 5b’10010 Minimum individual valley current limit configurable Individual phase current limit value (8) Maximum individual valley current limit configurable Individual phase current limit value (8) Individual low-side negative ILIM_NEG_OVP Individual phase current limit current limit in OVP CTRL CTRL on threshold CTRLON 2.2 CTRL off threshold CTRLOFF Timing and Frequency Switching frequency (8) fSW Individual phase Minimum on time (8) tON_MIN fSW = 1000kHz, VOUT = 0.6V (8) Minimum off time tOFF_MIN VFB = 480mV Output Over-Voltage Protection (OVP) and Under-Voltage Protection (UVP) OVP threshold UVP threshold Maximum configurable OVP threshold Minimum configurable OVP threshold Maximum configurable UVP threshold Minimum configurable UVP threshold 1.2 600 50 220 V V kHz ns ns VOVP VUVP D4h, bits[1:0] = 00 D9h, bits[3:2] = 10 111% 75% 115% 79% 119% 83% VREF VREF VOVP_MAX D4h, bits[1:0] = 11 126% 130% 134% VREF VOVP_MIN D4h, bits[1:0] = 00 111% 115% 119% VREF VUVP_MAX D9h, bits[3:2] = 11 80% 84% 88% VREF VUVP_MIN D9h, bits[3:2] = 00 65% 69% 73% VREF MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 10 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol Analog-to-Digital Converter (ADC) Condition Voltage range ADC resolution DNL Sample rate Digital-to-Analog Converter (DAC) (Feedback Voltage) 21h, bits[11:0] = 0x0258h; Range (8) 29h, bits[9:0] = 0x01F4h 21h, bits[11:0] = 0x0258h; Feedback accuracy VFB 29h, bits[9:0] = 0x01F4h Resolution Per LSB Feedback voltage with margin VFB_MG_HIGH high (8) Feedback voltage with margin VFB_MG_LOW low (8) Soft Start and Turn-On/Off Delay Soft-start time (9) tSS 61h, bits[2:0] = 3b’001 Turn-on delay tON_DELAY 60h, bits[7:0] = 0x00h Turn-off delay tOFF_DELAY 64h, bits[7:0] = 0x00h Error Amplifier VFB = VREF (VFB is the Feedback current IFB difference between VOSNS+ and VOSNS-) Soft Shutdown Soft shutdown discharge FET RON_DISCH Individual phase Under-Voltage Lockout (UVLO) VCC UVLO rising threshold VCCVTH VCC UVLO threshold VCCHYS hysteresis Minimum configurable input VIN_ON_MIN VCC = 3.3V turn-on voltage Maximum configurable input turn-on voltage Minimum configurable input turn-off voltage Maximum configurable input turn-off voltage (8) Min Typ Max Units 1.28 V bits LSB kHz (8) VIN_ON_MAX VIN_OFF_MIN VIN_OFF_MAX VCC = 3.3V 0 10 1 3 450 600 672 mV 594 600 606 mV 2 mV 672 mV 450 mV 2 0 0 ms ms ms 50 100 Ω 60 2.6 2.75 nA 2.9 250 V mV 2.65 2.9 3.1 V 16 16.5 17 V 2.75 V 15.75 V MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 11 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Power Good (PG) Symbol PG high threshold PGVTH_HI PG low threshold PGVTH_LO PG low-to-high delay PG sink current capability PG leakage current tPGTD VPG IPG_LEAK VOL_100 PG low-level output voltage VOL_10 Thermal Protection (TP) TP fault rising threshold (8) TSD_RISE TP fault falling threshold (8) TSD_FALL TP warning rising threshold (8) TWARN_RISE TP warning falling threshold (8) TWARN_FALL Condition Min VFB from low to high; D9h, bits[1:0] = 01 VFB from high to low; D9h, bits[3:2] = 10 D1h, bits[5:2] = 0000 IPG = 10mA VPG = 3V VIN = 0V, pull PGOOD up to 3.3V through a 100kΩ resistor, TJ = 25°C VIN = 0V, pull PGOOD up to 3.3V through a 10kΩ resistor, TJ = 25°C Max Units 94% VREF 79% VREF 2 ms V µA 0.3 1.5 600 720 mV 700 4Fh = 0x96h 4Fh = 0x96h; D6h, bits[2:1] = 01 51h = 0082h 51h = 0082h; D6h, bits[2:1] = 01 Min TP warning temperature (8) TSD_WARN_MIN Max TP warning temperature (8) TSD_WARN_MAX Monitoring Parameters Output voltage monitor VOUT = 0.6V accuracy (8) Input voltage monitor accuracy Typ 820 150 °C 125 °C 130 °C 105 °C 35 160 °C °C 0.588 0.6 0.612 V 11.76 12 12.24 V MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 12 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol Condition PMBus DC Characteristics (SDA, SCL, ALERT, CTRL) (8) Input high voltage VIH Input low voltage VIL Output low voltage VOL IOL = 1mA Input leakage current ILEAK SDA, SCL, ALERT = 3.3V Maximum voltage (SDA, VMAX Transient voltage including ringing SCL, ALERT, CTRL) Pin capacitance on SDA, CPIN SCL PMBus Timing Characteristics (8) Min operating frequency Max operating frequency Bus free time Between a stop and start condition Hold time Repeated start condition set-up time Stop condition set-up time Data hold time Data set-up time Clock low timeout Clock low period Clock high period Clock/data falling time Clock/data rising time Min Typ Max Units 2.1 0.4 +10 V V V µA +3.6 V 10 pF 0.8 -10 -0.3 3.3 10 1000 4.7 4.0 kHz kHz µs µs 4.7 µs 4.0 300 250 25 4.7 4.0 µs ns ns ms µs µs ns ns 35 50 300 1000 Notes: 8) 9) Guaranteed by sample characterization. Guaranteed by sample characterization. Not tested in production. The parameter is tested during parameters characterization. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 13 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 1V, fSW = 600kHz, TA = 25°C, unless otherwise noted. Efficiency vs. Output Current Power Loss vs. Output Current VIN = 12V, without external 3.3V VCC VIN = 12V, without external 3.3V VCC 25.0 100.0 VOUT=0.78V, 600kHz VOUT=0.85V, 600kHz VOUT=0.9V, 600kHz VOUT=1V, 600kHz VOUT=1.2V, 600kHz VOUT=1.8V, 600kHz VOUT=3.3V, 1000kHz 20.0 90.0 POWER LOSS (W) EFFICIENCY (%) 95.0 85.0 VOUT=0.78V, 600kHz VOUT=0.85V, 600kHz VOUT=0.9V, 600kHz VOUT=1V, 600kHz VOUT=1.2V, 600kHz VOUT=1.8V, 600kHz VOUT=3.3V, 1000kHz 80.0 75.0 70.0 65.0 15.0 10.0 5.0 0.0 60.0 0 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Efficiency vs. Load Current Power Loss vs. Load Current VIN = 12V, with external 3.3V VCC VIN = 12V, with external 3.3V VCC 100 25 95 VOUT=0.75V,Fsw=600kHz VOUT=1V,Fsw=600kHz VOUT=1.2V,Fsw=600kHz VOUT=1.8V,Fsw=800kHz VOUT=3.3V,Fsw=1000kHz 20 POWER LOSS (W) EFFICIENCY (%) 90 85 80 VOUT=0.75V,Fsw=600kHz VOUT=1V,Fsw=600kHz VOUT=1.2V,Fsw=600kHz VOUT=1.8V,Fsw=800kHz VOUT=3.3V,Fsw=1000kHz 75 70 15 10 5 0 65 0 10 20 30 40 50 60 70 LOAD CURRENT (A) 80 90 100 Output Voltage Derating VIN = 12V, without airflow and external 3.3V VCC VIN = 12V, without airflow and external 3.3V VCC 100 MAX LOAD CURRENT (A) MAX OUTPUT CURRENT (A) 110 90 80 70 60 VOUT=3.3V, 800kHz VOUT=1.8V, 400kHz VOUT=1V, 400kHz VOUT=0.5V, 400kHz 40 30 20 -40 -20 0 20 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (A) Thermal Derating 50 0 40 60 80 AMBIENT TEMPERATURE (°C) 100 100 90 80 70 60 50 40 30 20 10 0 50°C Ambient 75°C Ambient 100° CAmbient 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 OUTPUT VOLTAGE (V) MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 14 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 1V, fSW = 600kHz, TA = 25°C, unless otherwise noted. Start-Up through VIN Shutdown through VIN No load No load CH1: VOUT CH1: VOUT CH2: VIN CH2: VIN CH3: PG CH3: PG CH4: IOUT CH4: IOUT Start-Up through VIN Shutdown through VIN Full load Full load CH1: VOUT CH1: VOUT CH2: VIN CH2: VIN CH3: PG CH3: PG CH4: IOUT CH4: IOUT Start-Up through EN Shutdown through EN No load No load CH1: VOUT CH1: VOUT CH2: EN CH2: EN CH3: PG CH3: PG CH4: IOUT CH4: IOUT MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 15 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 1V, fSW = 600kHz, TA = 25°C, unless otherwise noted. Start-Up through EN Shutdown through EN Full load Full load CH1: VOUT CH1: VOUT CH2: EN CH2: EN CH3: PG CH3: PG CH4: IOUT CH4: IOUT Load Transient, Single-Module Operation Load Transient, Single-Module Operation VOUT = 0.78V, 0A to 25A, COUT = 20 x 47μF + 5 x 220μF VOUT = 0.78V, 0A to 50A, COUT = 20 x 47μF + 5 x 220μF CH1: VOUT/AC CH1: VOUT/AC CH4: IOUT CH4: IOUT Load Transient, Single-Module Operation Load Transient, Single-Module Operation VOUT = 0.9V, 0A to 25A, COUT = 20 x 47μF + 4 x 220μF VOUT = 0.9V, 0A to 50A, COUT = 20 x 47μF + 4 x 220μF CH1: VOUT/AC CH1: VOUT/AC CH4: IOUT CH4: IOUT MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 16 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS FUNCTIONAL BLOCK DIAGRAM TAKE 0.1µF INPUT VIN 10kΩ 1µF TAKE1 BST1 PG CTRL 2x 0.1µF CIN1 220nH COUT1 Power Control Master 1µF SCL VOSNS+ ALT VOSNS- PASS1 COUT2 GND SDA ADDR OUTPUT VOUT VCC ISUM> SET> ISUM1 SET1 RUN 0.1µF VIN 1µF TAKE2 BST2 220nH CTRL2 VCC CIN2 2x 0.1µF Power Control 2 1µF SCL2 SDA2 VOSNS2+ ALT2 VOSNS2- ADDR PASS2 ISUM2 SET2 0.1µF VIN 1µF TAKE3 BST3 2x 0.1µF 220nH CTRL3 VCC 1µF CIN3 Power Control 3 SCL3 SDA3 VOSNS3+ ALT3 VOSNS3- ADDR PASS3 ISUM3 SET3 0.1µF VIN 1µF TAKE4 BST4 220nH CTRL4 VCC 1µF CIN4 2x 0.1µF Power Control 4 SCL4 SDA4 VOSNS4+ ALT4 VOSNS4- ADDR PASS4 ISUM4 SET4 ISUM< SET< PASS Figure 3: Functional Block Diagram MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 17 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS OPERATION The MPM3695-100 is a fully integrated power module with up to 100A of continuous output current on a BGA (15mmx30mmx5.18mm) package. For applications that require more than 100A, up to eight MPM3695-100 modules can be connected in parallel to deliver an output current up to 800A. The MPM3695-100 employs multiphase constant-on-time (MCOT) control to provide fast transient response. Internal ramp compensation guarantees stable operation for applications using zero-ESR ceramic output capacitors. Poly-Phase Architecture The MPM3695-100 integrates four sets of halfbridges with a power controller in each module. In single-module operation, the four phases are phase-shifted by 90° to minimize the output voltage ripple. One of the internal phases must be configured as the master phase, and the other three phases are slave phases. MCOT Operation: Master Phase The master phase performs the following functions:  Accepts both write and read commands through the PMBus from a host.  Generates the SET signal.  Manages start-up, shutdown, and all of the protection functions.  Monitors fault alerts from the slave phases through the PG pin.  Generates the first on pulse.  Generates the on pulse when receiving RUN and SET signals.  Dynamically adjusts its on time to ensure equal current sharing.  Generates the PASS signal. MCOT Operation: Slave Phases The slave phases perform the functions: following  Accept write commands through the PMBus from a host.  Receive SET signal(s) from a master phase.  Start the on pulse when receiving RUN and SET signals.  Dynamically adjust their on time to ensure equal current sharing on their own phase based on the per-phase and total current.  Generate the PASS signal Parallel Operation In parallel configuration, one master module and up to seven slave modules are connected in parallel. The output current (IOUT) is shared equally between all MPM3695-100 power modules with active current balancing. The Typical Application Circuits section on page 47 illustrates two and four MPM3695-100s in parallel configuration. In parallel operation, each switching period is divided by up to eight interleaved phases with 45° phase-shifting. For four-module operation, two half-bridges are turned on simultaneously at each PWM pulse. The TAKE pin of the master module must be pulled up to a voltage source through a resistor. The MPM3695-100 detects its master/slave configuration by monitoring the state of the TAKE pin during start-up. The RUN and TAKE pins of all phases are connected in a cascaded manner. Ramp Compensation The MPM3695-100 operates with zero-ESR ceramic output capacitors by using internal ramp compensation. A triangular RAMP signal is generated internally, then superimposed onto the FB signal. The triangular RAMP signal starts to rise once (VFB + RAMP) drops below the reference signal and a SET pulse is generated. The RAMP signal rise time is fixed. The amplitude of the ramp compensation is selectable through register D0h, bits[3:1] to support a wide range of operation configurations. There is a tradeoff between stability and load transient response. A larger RAMP signal provides better stability but slower load transient response, and vice versa. Optimize ramp compensation selection based on the design criteria for each application (see Table 6 on page 19). MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 18 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS Table 6: Recommended Ramp and Resistor Divider Values VIN (V) VOUT (V) fSW (kHz) R1 (kΩ) R2 (kΩ) Ramp (mV) CFF (nF) 12 12 12 12 12 12 0.78 0.9 1.0 1.2 1.8 3.3 600 600 600 600 600 1000 1 1 1 1 2 4.53 3.3 2 1.5 1 1 1 41 41 41 41 41 41 33 33 33 33 33 33 MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 19 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS PMBUS INTERFACE PMBus Serial Interface Description The Power Management Bus (PMBus) is an open-standard, power management protocol that defines a means of communication with power conversion and other devices. signal transitioning from low to high while SCL is high (see Figure 4 on page 21). Table 7: ADDR Resistor vs. PMBus Address The PMBus is a two-wire, bidirectional, serial interface, consisting of a data line (SDA) and a clock line (SCL). The lines are externally pulled up to a bus voltage when they are in an idle state. When connecting to the lines, a master device generates the SCL signal and device address, then arranges the communication sequence. The MPM3695-100 is a PMBus slave device that supports both standard mode (100kHz) and fast modes (400kHz and 1000kHz). Slave Address A unique address should be set for each slave device that is connected to the same PMBus. The ADDR pin configures the address for the MPM3695-100. There is a 10µA current flowing out of the ADDR pin. Connect a resistor between the ADDR pin and AGND to set the ADDR voltage. The internal analog-to-digital converter (ADC) converts the ADDR pin voltage to set the PMBus address. A maximum of 16 addresses can be set by the ADDR pin. Table 7 lists the PMBus address for different resistor values. MFR_ADDR_PMBUS (D3h) can be used to digitally set the PMBus address. For multi-phase configuration, the slave phases can share the same address as the master or they can have different addresses, depending on the application requirements. The slave phases can only accept write commands, which means they cannot accept read commands from the PMBus master. However, the master phase can accept both write and read commands from the PMBus master. Start and Stop Commands Start and stop commands are signaled by the master device to indicate the beginning and the end of the PMBus transfer. A start (S) command is defined as the SDA signal transitioning from high to low while SCL is high. A stop (P) command is defined as the SDA RADDR (kΩ) Slave Address 1.24 3.74 6.2 8.2 11.3 13.7 16.2 18.7 21 24 26.1 28.7 30.9 33 36 39 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh The master then generates the SCL clock signal(s) and transmits the device address and the read/write (R/W) direction bit on the SDA line. Data is transferred in 8-bit bytes by the SDA line. Each byte of data must be followed by an acknowledge (ACK) bit. PMBus Update Sequence The MPM3695-100 requires a start command, a valid PMBus address, a register address byte, and a data byte for a single data update. After receiving each byte, the MPM3695-100 acknowledges this process by pulling the SDA line low during the high period of a single clock pulse. A valid PMBus address selects the MPM3695-100. The MPM3695-100 performs an update on the falling edge of the LSB byte. Protocol Usage All PMBus transactions on the MPM3695-100 are done using defined bus protocols. The following protocols can be implemented:    Send byte with packet error checking (PEC) Receive byte with PEC Write byte with PEC MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 20 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS     Read byte with PEC Write word with PEC Read word with PEC Block read with PEC PMBus Message Format Figure 5 on page 22 shows the message formats. Unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the MPM3695-100 is driving the bus.     S = Start condition Sr = Repeated start condition P = Stop condition R = Read bit   W = Write bit A = Acknowledge bit (0)  A = Acknowledge bit (1) A represents the acknowledge (ACK) bit. The ACK bit is typically active low (logic 0) if the transmitted byte is successfully received by a device. However, when the receiving device is the bus master, the ACK bit for the last byte read is a logic 1, indicated by A . Packet Error Checking (PEC) The MPM3695-100’s PMBus interface supports the use of the packet error checking (PEC) byte. The PEC byte is transmitted by the MPM3695100 during a read transaction, or sent by the bus host to the MPM3695-100 during a write transaction. The PEC byte detects errors during a bus transaction, depending on whether the transaction is a read or a write. If the host determines that the PEC byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. If the MPM3695-100 determines that the PEC byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag. Within a group command, the host can choose to send or not send a PEC byte as part of the message to the MPM3695-100. PMBus Alert Response Address (ARA) The PMBus alert response address (ARA) is a special address that can be used by the bus host to locate any devices with which it can communicate. A host typically uses a hardware interrupt pin to monitor the PMBus ALERT pins from a number of devices. When the host interrupt occurs, the host issues a message on the bus using the PMBus receive byte, or on the received byte with PEC protocol. The special address used by the host is 0x0C. Any devices that have a PMBus alert signal return their own 7-bit address as the 7MSB of the data byte. The LSB value is not used, and can be either 1 or 0. The host reads the device address from the received data byte and proceeds to handle the alert condition. More than one device may have an active PMBus alert signal and attempt to communicate with the host. In this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. The device that succeeds disables its PMBus alert signal. If the host sees that the PMBus alert signal is still low, it continues to read addresses until all devices have successfully transmitted their addresses. Figure 4: Data Transfer through the PMBus MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 21 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS a) Send Byte and Send Byte with PEC 1 S 7 Slave Address 1 Wr 1 A 8 Data Byte 1 1 A P 1 S 7 Slave Address 1 Wr 1 A 8 Data Byte 1 A 8 PEC 1 1 A P b) Receive Byte and Receive Byte with PEC 1 S 7 Slave Address 1 Rd 1 A 8 Data Byte 1 1 A P 1 S 7 Slave Address 1 Rd 1 A 8 Data Byte 1 A 8 PEC 1 1 A P c) Write Byte and Write Byte with PEC 1 S 7 Slave Address 1 Wr 1 A 8 Command Code 1 A 8 Data Byte 1 1 A P 1 S 7 Slave Address 1 Wr 1 A 8 Command Code 1 A 8 Data Byte 1 A 8 PEC 1 1 A P d) Write Word and Write Word with PEC 1 S 7 Slave Address 1 1 Wr A 8 Command Code 1 A 8 Data Byte Low 1 A 8 Data Byte High 1 1 A P 1 S 7 Slave Address 1 1 Wr A 8 Command Code 1 A 8 Data Byte Low 1 A 8 Data Byte High 1 A 1 1 8 PEC 1 1 A P e) Read Byte and Read Byte with PEC 1 7 1 1 8 S Slave Address Wr A Command Code 1 7 1 1 8 S Slave Address Wr A Command Code A S 1 7 1 1 8 Slave Address Rd A 1 7 1 1 Data Byte 1 1 A P 8 1 8 Data Byte A PEC A S Slave Address Rd A 8 Command Code 1 1 A S 7 1 1 Slave Address Rd A 8 Data Byte Low 1 A 8 Data Byte High 1 A 8 Command Code 1 1 A S 7 1 1 Slave Address Rd A 8 Data Byte Low 1 A 8 Data Byte High 1 A 1 1 A P f) Read Word and Read Word with PEC 1 S 1 S 7 Slave Address 7 Slave Address 1 Wr 1 Wr 1 A 1 A 1 P 8 PEC 1 A 1 P g) Block Read with PEC 1 S 7 Slave Address 8 Data Byte 1 1 S 7 Slave Address 8 Data Byte 1 8 1 A Command Code 1 Wr 1 A 8 Data Byte 2 1 A 1 A 8 Data Byte 2 ... ... 1 A 8 1 A Command Code 1 Wr 1 A 1 A 1 Sr 7 Slave Address 8 Data Byte N 1 Sr ... ... 1 Rd 1 A 7 Slave Address 8 Data Byte N 1 A 8 Byte Count = N 1 A ... 1 P 1 Rd 1 A 1 A 8 Byte Count = N 8 PEC 1 A 1 A ... 1 P Figure 5: PMBus Message Format MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 22 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS Data and Numerical Formats The MPM3695-100 uses a direct internal format to represent real-world values such as voltage, current, power, and temperature. All numbers with no suffix in this document are decimals, unless explicitly designated otherwise. Numbers in binary format are indicated by the prefix “n’b”, where n is the binary count. For example, 5’b01010 indicates a 5-bit binary data where the data is 01010. The suffix “h” indicates a hexadecimal format, which is generally used for the register address number in this document. The symbol “0x” indicates a hexadecimal format, which is used for the value in the register. For example, 0xA3 is a 1-byte number with a hexadecimal value of A3. PMBus Communication Failure A data transmission fault occurs when data is not properly transferred between the devices. There are several possible data transmission faults:       Sending too little data Reading too little data Sending too many bytes Reading too many bytes Improperly set read bit in the address byte Unsupported command code PMBus Reporting and Status Monitoring The MPM3695-100 supports real-time monitoring for some operation parameters and status with PMBus interface (see Table 8). Table 8: PMBus Monitored Parameters and Statuses Parameter/Status PMBus Output voltage (VOUT) Output current (IOUT) Temperature Input voltage (VIN) VIN over-voltage (OV) VIN under-voltage (UV) VIN OV warning VIN UV warning VOUT OV VOUT UV Over-temperature (OT) OT warning VOUT over-current (OC) VOUT OC 1.25mV/LSB 62.5mA/LSB 1°C/LSB 25mV/LSB           MTP Programming The MPM3695-100 has a built-in, multiple-time programmable (MTP) memory to store user configurations. The standard command register STORE_USER_ALL (15h) is not supported by the MPM3695-100. Instead, the MTP cells can be configured using the following command combination: 1. E7h (2000h) 2. E7h (1000h) 3. E7h (4000h) In the GUI, the above commands are integrated together and named STORE_USER_ALL (15h). This means that MPS’s GUI supports the 15h command. When the MTP is being configured, the VCC voltage (VCC) may reach as high as 5V. Ensure that VCC is connected to circuits that can withstand this voltage. MTP configuration typically takes about 300ms. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 23 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS REGISTER MAP Name OPERATION ON_OFF_CONFIG CLEAR_FAULTS WRITE_PROTECT STORE_USER_ALL RESTORE_USER_ALL CAPABILITY VOUT_MODE VOUT_COMMAND VOUT_MAX VOUT_MARGIN_HIGH VOUT_MARGIN_LOW VOUT_SCALE_LOOP VOUT_MIN VIN_ON VIN_OFF OT_FAULT_LIMIT OT_WARN_LIMIT VIN_OV_FAULT_LIMIT VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT TON_DELAY TON_RISE TOFF_DELAY STATUS_BYTE STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_TEMPERATURE STATUS_CML READ_VIN READ_VOUT READ_IOUT READ_TEMPERATURE_1 MFR_CTRL_COMP MFR_CTRL_VOUT MFR_CTRL_OPS MFR_ADDR_PMBUS MFR_VOUT_FAULT_LIMIT MFR_OVP_NOCP_SET MFR_OT_OC_SET MFR_OC_PHASE_LIMIT MFR_PGOOD_ON_OFF_ LIMIT MFR_VOUT_STEP MFR_CTRL Code 01h 02h 03h 10h 15h 16h 19h 20h 21h 24h 25h 26h 29h 2Bh 35h 36h 4Fh 51h 55h 57h 58h 60h 61h 64h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 88h 8Bh 8Ch 8Dh D0h D1h D2h D3h D4h D5h D6h D7h Type R/W with PEC R/W with PEC Send byte with PEC R/W with PEC Send byte with PEC Send byte with PEC R with PEC R with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC R/W with PEC Bytes 1 1 0 1 0 0 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 Default Value 0x80 0x1e 0x00 0xB0 0x40 0x0258 (1.2V) 0x0BB8 (6V) 0x02A0 (1.344V) 0x01FE (1.02V) 0x01F4 (0.5) 0x00FA (0.5V) 0x0010 (4V) 0x000B (2.75V) 0x00A0(160°C) 0x008C (140°C) 0x0024 (18V) 0x0022 (17V) 0x0001 (0.25V) 0x0000 (0ms) 0x0002 (4ms) 0x0000 (0ms) 0x0D 0x00 0x03 0x30 0x03 0x02 0x09 0x11 (102A total, 25.5A per phase) D9h R/W with PEC 1 0x00 DAh EAh R/W with PEC R/W with PEC 1 2 0x04 0xE8 MTP                               Note: 10) For manufacturer use. Write-only. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 24 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS OPERATION (01h) The OPERATION command is a paged register. This command turns the converter output on and off in conjunction with input from the CTRL pin. It also sets VOUT to the upper or lower margin voltages. The device remains in the commanded operating mode until a subsequent OPERATION command (or a change in the state of the CTRL pin) instructs the converter to change to another mode. This command can re-enable the converter after a fault-triggered shutdown. Writing an off command followed by an on command clears all faults. Writing only an on command after a fault-triggered shutdown does not clear the fault registers. Command Format Bit Access Function Default Value Bits[7:6] 00 01 10 10 10 10 10 7 R/W 6 R/W 5 R/W 1 0 0 OPERATION Unsigned binary 4 3 R/W R/W 2 R/W 1 R 0 0 0 R X Bits[5:4] xx xx 00 01 01 10 10 Bits[3:2] xx xx xx 01 10 01 10 Bits[1:0] xx xx xx xx xx xx xx 0 On/Off Immediate off Soft shutdown On On On On On 0 Margin State N/A N/A Off Margin low (ignore fault) Margin low (act on fault) Margin high (ignore fault) Margin high (act on fault) 0 01h 0x00 0x60 0x80 0x94 0x98 0xA4 0xA8 ON_OFF_CONFIG (02h) The ON_OFF_CONFIG command configures the combination of the CTRL pin input and PMBus commands required to turn the converter on and off. This includes how the converter responds when VIN is applied. Command Format Bit Access Function Default value 7 R 0 6 R X 0 5 R 0 ON_OFF_CONFIG Unsigned binary 4 3 R/W R/W ON OP 1 1 2 R/W CTRL 1 1 R/W POL_CTRL 1 0 R DELAY 0 ON The ON bit sets the default to either operate whenever VIN is present, or for the on/off operation to be controlled by the CTRL pin and PMBus commands. Bit[4] Value Description 0 The converter starts up any time VIN is present, regardless of the state of the CTRL pin. 1 The converter does not start up unless commanded by the CTRL pin and OPERATION command (as configured in bits[3:0]). OP The OP bit controls how the converter responds to OPERATION commands. Bit[3] Value Description 0 The converter ignores the ON bit in the OPERATION command from the PMBus. 1 The converter responds to the ON bit in the OPERATION command from the PMBus. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 25 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS CTRL The CTRL bit controls how the converter responds to the CTRL pin. Bit[2] Value Description 0 The converter ignores the CTRL pin (the device turning on and off is only controlled by the OPERATION command). 1 The converter requires the CTRL pin to be asserted to start up. Depending on bit[3] (OP), the OPERATION command may also be required to instruct the converter to start up. POL_CTRL The POL_CTRL bit sets the polarity of the CTRL pin. This function is disabled. Bit[1] Value Description 0 Active low (pull the CTRL pin low to start the converter). 1 Active high (pull the CTRL pin high to start the converter). DELAY The DELAY bit sets the shutdown action when the converter is commanded off through the PMBus. This bit is read-only and cannot be modified by the end user. Bit[0] Value Description 0 TOFF_DELAY, TOFF_FALL. CLEAR_FAULTS (03h) The CLEAR_FAULTS command resets all stored warning and fault flags. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, the ALT# signal may not be cleared, or may be reasserted almost immediately. Issuing a CLEAR_FAULTS command does not cause the converter to restart in the event of a fault shutdown. To restart the device, issue an OPERATION on command after the fault condition is cleared. This command uses the PMBus to send the byte protocol. WRITE PROTECT (10h) The WRITE_PROTECT command controls writing to the converter. The provides protection against accidental changes. All supported commands (registers) may have their parameters read, regardless of the WRITE_PROTECT settings. Bits[7:0] Value Description 0 0 0 0 0 0 0 0 Enables writes to all registers. 0 0 1 0 0 0 0 0 Disables all writes except to the WRITE_PROTECT, OPERATION, PAGE, ON_OFF_CONFIG, and VOUT_COMMAND registers. 0 1 0 0 0 0 0 0 Disables all writes except to the WRITE_PROTECT, OPERATION, and PAGE registers. 1 0 0 0 0 0 0 0 Disables all writes except to the WRITE_PROTECT register. When 10h is set to a value other than 0x00 to configure the MTP, register 15h can only be set through MPS’s GUI. The MTP’s E7h command cannot be used. For more details, see the MTP Programming section on page 23. The default value for this register is 0x00. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 26 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS STORE_USER_ALL (15h) The STORE_USER_ALL command writes the data from the registers to the internal MTP(s). This occurs when the MPM3695-100 receives a STORE_USER_ALL command from the PMBus interface. The MPM3695-100 does not support the 15h command via the MTP. However, the device can accept the 15h command from MPS’s GUI. For more details, see the MTP Programming section on page 23. The following registers can be stored using STORE_USER_ALL:                               OPERATION (01h) ON_OFF_CONFIG (02h) WRITE_PROTECT (10h) VOUT_COMMAND (21h) VOUT_MAX (24h) VOUT_MARGIN_HIGH (25h) VOUT_MARGIN_LOW (26h) VOUT_SCALE_LOOP (29h) VOUT_MIN (2Bh) VIN_ON (35h) VIN_OFF (36h) OT_FAULT_LIMIT (4Fh) OT_WARN_LIMIT (51h) VIN_OV_FAULT_LIMIT (55h) VIN_OV_WARN_LIMIT (57h) VIN_UV_WARN_LIMIT (58h) TON_DELAY (60h) TON_RISE (61h) TOFF_DELAY (64h) MFR_CTRL_COMP (D0h) MFR_CTRL_VOUT (D1h) MFR_CTRL_OPS (D2h) MFR_ADDR_PMBUS (D3h) MFR_VOUT_FAULT_LIMIT (D4h) MFR_OVP_NOCP_SET (D5h) MFR_OT_OC_SET (D6h) MFR_OC_PHASE_LIMIT (D7h) MFR_PGOOD_ON_OFF_LIMIT (D9h) MFR_VOUT_STEP (DAh) MFR_CTRL (EAh) RESTORE_USER_ALL (16h) The RESTORE_USER_ALL command instructs the MPM3695-100 to copy the entire contents of the MTP to the matching locations in the registers. The values in the registers are overwritten by the values retrieved from the MTP. Any items in the MTP that do not have matching locations in the operating memory are ignored. This command can be used while the MPM3695-100 is operating, but the device may be unresponsive. This command is write-only. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 27 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS CAPABILITY (19h) The CAPABILITY command returns information about the PMBus functions supported by the MPM3695100. This command is read with the PMBus read byte protocol. Command Format Bit Access Function Default Value Details Bits[6:5] Value CAPABILITY Unsigned binary 6 5 4 3 2 1 R R R R R R MAX_BUS_SPEED ALERT X 0 1 1 0 0 0 PEC supported, max speed 1MHz, supports PMBus alert and ARA 7 R PEC 1 0 R 0 Meaning 0 0 The maximum supported bus speed is 100kHz. 0 1 The maximum supported bus speed is 1MHz. 1 0 The maximum supported bus speed is 400kHz. 1 1 Reserved. The default value for this register is 0xB0. VOUT_MODE (20h) The VOUT_MODE command reads and commands VOUT. The 3MSB are used to determine the data format (only direct format is supported), and the remaining 5 bits represent the exponent used in the VOUT read/write commands. The default value for this register is 0x40. VOUT_COMMAND (21h) The VOUT_COMMAND command sets VOUT. To calculate the feedback reference voltage, multiply VOUT_COMMAND by VOUT_SCALE_LOOP. For more details, see the Setting the Output Voltage section on page 43. Command Format Bit Access Function Default Value VOUT_COMMAND Direct 9 8 7 6 15 14 13 12 11 10 R R R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 0 X R/W 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 1 1 0 0 0 2mV/LSB 1 0 The value is unsigned and 1LSB = 2mV. The default value of 21h is 1.2V, meaning the default value of this register is 0x0258. VOUT_MAX (24h) The VOUT_MAX command sets an upper limit on VOUT, regardless of any other commands or combinations. VOUT_MAX provides a safeguard against the user accidentally setting VOUT too high. It does not replace over-voltage protection (OVP). Command Format Bit Access Function Default Value VOUT_MAX Direct 8 7 15 14 13 12 11 10 9 R R R R R/W R/W R/W R/W R/W 0 0 0 0 1 0 1 1 1 X 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W 1 1 0 0 0 2mV/LSB 0 1 MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 28 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS If an attempt is made to set VOUT to a level that exceeds VOUT_MAX, the device takes the following actions: 1. The commanded VOUT is set to VOUT_MAX. 2. The VOUT bit is set in STATUS_WORD. 3. The VOUT_MAX_MIN warning bit is set in the STATUS_VOUT register. 4. The device notifies the host. The value is unsigned and 1LSB = 2mV. The maximum value of VOUT_MAX is 6V, and the default value is 6V. The default value of this register is 0x0BB8h. VOUT_MARGIN_HIGH (25h) Command Format Bit Access Function Default Value VOUT_MARGIN_HIGH Direct 9 8 7 6 15 14 13 12 11 10 R R R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 1 X R/W 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 2mV/LSB 0 1 The value is unsigned and 1LSB = 2mV. The default value is 1.344V, meaning the default value of this register is 0x02A0. VOUT_MARGIN_LOW (26h) Command Format Bit Access Function Default Value VOUT_MARGIN_LOW Direct 9 8 7 6 15 14 13 12 11 10 R R R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1 1 X R/W 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 1 1 1 1 0 2mV/LSB 1 1 The value is unsigned and 1LSB = 2mV. The default value is 1.02V, meaning the default value of this register is 0x1fe. VOUT_SCALE_LOOP (29h) The VOUT_SCALE_LOOP sets the feedback resistor divider ratio, which is equal to (VOSNS+ - VOSNS-) / VOUT. This command should match the actual value of the feedback resistor divider, regardless of whether it is an external or internal feedback resistor divider. Command Format Bit Access Function Default Value 15 R 14 R 13 R 0 0 0 VOUT_SCALE_LOOP Direct 9 8 7 6 12 R 11 R 10 R R/W R/W R/W R/W 0 0 0 0 1 1 1 X 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 1 0 0 0.001/LSB 1 1 The value is unsigned and 1LSB = 0.001. The default value is 0.5, meaning the default value of this register is 0x01F4. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 29 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS VOUT_MIN (2Bh) The VOUT_MIN command sets a lower limit on the converter’s VOUT, regardless of any other commands or combinations. VOUT_MIN provides a safeguard against a user accidentally setting VOUT too low. It does not replace under-voltage protection (UVP). Command Format Bit Access Function Default Value VOUT_MIN Direct 8 7 15 14 13 12 11 10 9 R R R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 1 X 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W 1 1 0 1 0 2mV/LSB 1 1 If an attempt is made to program VOUT below the limit set by this command, the device takes the following actions: 1. The commanded VOUT is set to VOUT_MIN. 2. The VOUT bit is set in STATUS_WORD. 3. The VOUT_MAX_MIN warning bit is set in the STATUS_VOUT register. 4. The device notifies the host. The minimum value of VOUT_MIN is 0.5V. The value is unsigned and 1LSB = 2mV. The default value is 0.5V, meaning the default value of this register is 0x00FA. VIN_ON (35h) The VIN_ON command sets the VIN value at which the converter starts to run if all other required startup conditions are met. VIN_ON should be always set above VIN_OFF with a sufficient margin so that there is no bouncing between VIN_ON and VIN_OFF during power conversion. Command Format Bit Access Function Default Value 15 14 13 12 11 10 9 VIN_ON Direct 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 1 0 0 X 250mV/LSB 0 0 The value is unsigned and 1LSB = 250mV. The default value is 4V. VIN_OFF (36h) The VIN_OFF command sets the VIN value at which the converter, once operation has started, should stop power conversion. VIN_OFF should always be set below VIN_ON with a sufficient margin so that there is no bouncing between VIN_OFF and VIN_ON during power conversion. Command Format Bit Access Function Default Value VIN_OFF Direct 8 7 15 14 13 12 11 10 9 6 5 4 3 2 1 0 R R R R R R R R R R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 1 1 X 250mV/LSB 1 0 The value is unsigned and 1LSB = 250mV. The default value is 2.75V. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 30 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS OT_FAULT_LIMIT (4Fh) The OT_FAULT_LIMIT command reads and configures the threshold for over-temperature (OT) fault detection. If the measured temperature exceeds this value, an OT fault is triggered. The MPM3695-100 resumes normal operation after OTP based on the OT_RESPONSE in register MFR_OT_OC_SET (D6h). If an OT fault occurs, the OT fault flags are set in STATUS_BYTE (78h) and STATUS_WORD (79h), and the ALT# signal is asserted. Once the measured temperature falls below the value in this register, the MOSFET may switch back on with the OPERATION command when the device is operating in latch-off mode. The minimum temperature fault detection time should be shorter than 20ms. The temperature range is 0°C to 255°C. If an OT fault occurs when the temperature exceeds this register value, the MPM3695-100 attempts to auto-retry once the temperature drops 20°C below this register value. Command Format Bit Access Function Default Value 15 14 13 12 11 10 OT_FAULT_LIMIT Direct 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 1 0 1 0 0 0 X 1°C/LSB 0 0 The value is unsigned and 1LSB = 1°C. The default value is 160°C, meaning the default value for this register is 00a0h. OT_FAULT_LIMIT should be set below 160°C. If OT_FAULT_LIMIT is set above 160°C, the register value is ignored and the MPM3695-100 enters thermal shutdown if the junction temperature reaches 160°C. Table 9 shows the relationship between the direct values and real-world values. Table 9: Direct vs. Real-World OT Values Direct Value 0000 0000 0000 0001 1111 1111 Real-World Value (°C) 0 1 255 OT_WARN_LIMIT (51h) The OT_WARN_LIMIT commands reads and configures the threshold for over-temperature (OT) warning detection. If the sensed temperature exceeds this value, an OT warning is triggered. If an OT warning occurs, the OT warning flags are set in STATUS_BYTE (78h) and STATUS_WORD (79h), and the ALT# signal is asserted. The minimum temperature warning detection time should be shorter than 20ms. Command Format Bit Access Function Default Value 15 14 13 12 11 10 OT_WARN_LIMIT Direct 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 1 0 0 1 0 0 X 1°C/LSB 0 1 The value is unsigned and 1LSB = 1°C. The default value is 140°C, meaning the default value for this register is 0x8Ch. OT_WARN_LIMIT should be set below 160°C. The relationship between the direct value and real-world values are the same as OT_FAULT_LIMIT. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 31 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS VIN_OV_FAULT_LIMIT (55h) The VIN_OV_FAULT_LIMIT command reads and configures the threshold for VIN over-voltage (OV) fault detection. If VIN exceeds the value in this register, VIN OV fault flags are set in the respective registers and the MPM3695-100 disables the power stage. If VIN drops below VIN_OV_FAULT_LIMIT, the MPM3695-100 resumes normal operation. Command Format Bit Access Function Default Value 15 R 14 R 13 R 12 R 11 R 0 0 0 0 0 10 R VIN_OV_FAULT_LIMIT Direct 9 8 7 6 R R R R 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 1 0 0 0 X 0 0 0 0 0 500mV/LSB 0 1 The value is unsigned and 1LSB = 500mV. VIN_OV_FAULT_LIMIT should not be set above 18V. VIN_OV_WARN_LIMIT (57h) The VIN_OV_WARN_LIMIT command reads and configures the threshold for VIN over-voltage (OV) warning detection. If VIN exceeds the value in this register, the VIN OV warning flags are set in the respective registers and the ALT# signal is asserted. Command Format Bit Access Function Default Value 15 R 14 R 13 R 12 R 11 R 0 0 0 0 0 10 R VIN_OV_WARN_LIMIT Direct 9 8 7 6 R R R R 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 1 0 1 0 X 0 0 0 0 0 500mV/LSB 0 0 The value is unsigned and 1LSB = 500mV. VIN_OV_WARN_LIMIT should not be set above 17V. VIN_UV_WARN_LIMIT (58h) The VIN_UV_WARN_LIMIT command reads and configures the threshold for the VIN under-voltage (UV) fault detection. If VIN falls below the value in this register, then the VIN UV warning flags are set in the respective registers and the ALT# signal is asserted. Command Format Bit Access Function Default Value 15 R 14 R 13 R 12 R 11 R 0 0 0 0 0 10 R VIN_UV_WARN_LIMIT Direct 9 8 7 6 R R R R 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 1 X 0 0 0 0 0 250mV/LSB 0 0 The value is unsigned and 1LSB = 250mV. The default value is 0.25V, meaning the default value for this register is 0x01. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 32 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TON_DELAY (60h) The TON_DELAY command sets the time from when a start command is received (as configured by the ON_OFF_CONFIG command) until VOUT starts to rise. Command Format Bit Access Function Default Value 15 R 14 R 13 R 12 R 0 0 0 0 11 R 10 R 9 R 0 0 0 TON_DELAY Direct 8 7 6 R/W R/W R 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 X 0 0 0 0 4ms/LSB 0 0 The value is unsigned and 1LSB = 4ms. The maximum value for this register is 0x0100 (1024ms). The default value is 0ms. TON_RISE (61h) The TON_RISE command sets the soft-start time from when VOUT starts to rise until it reaches the regulation point. Command Format Bit Access Function Default Value 15 R 14 R 13 R 12 R 11 R 10 R 0 0 0 0 0 0 9 R X 0 TON_RISE Direct 8 7 R R 0 0 6 R 5 R 4 R 3 R 2 1 0 R/W R/W R/W 0 0 0 0 0 1ms/LSB 1 0 Only the following values are supported:      3’b000: 1ms 3’b001: 2ms 3’b010: 4ms 3’b011: 8ms 3’b100 and up: 16ms The default value is 4ms, meaning the default value for this register is 0x02. TOFF_DELAY (64h) The TOFF_DELAY command sets the from when EN turns off to when VOUT starts to fall. Command Format Bit Access Function Default Value 15 R 14 R 13 R 12 R 0 0 0 0 11 R 10 R TOFF_DELAY Direct 9 8 7 6 R/W R/W R R 0 0 0 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 X 0 0 0 0 4ms/LSB 0 0 The value is unsigned and 1LSB = 4ms. The maximum value is FFh (1020ms). The default value is 0ms. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 33 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS STATUS_BYTE (78h) The STATUS_BYTE command returns the value of certain flags indicating the MPM3695-100’s status. Accesses to this command use the read byte protocol. To clear the bits in this register, the underlying fault must first be removed, then a CLEAR_FAULTS command must be issued. Bit s 7 Name RESERVED Description Behavio r Default N/A 0 Always reads as 0. Live 0 0: The device is enabled 1: The device is disabled. This may be due to a VIN under-voltage (UV) or over-voltage fault (OV), or from receiving an OPERATION off command 6 OFF 5 VOUT_OV Latch 0 0: No VOUT OV fault has occurred 1: A VOUT OV fault has occurred 4 IOUT_OC_FAULT Latch 0 0: No over-current (OC) fault has occurred 1: An OC fault has occurred 3 VIN_UV N/A 0 Not supported, always reads as 0. 2 OT_FAULT_ WARN Latch 0 0: No over-temperature (OT) warning or fault has occurred 1: An OT warning or fault has occurred 1 COMM_ERROR Latch 0 0: No communication error has occurred 1: A communication error has occurred 0 NONE_OF_THE_ ABOVE Latch 0 0: No other fault or warning has occurred 1: A fault or warning not listed in bits[7:1] has occurred STATUS_WORD (79h) The STATUS_WORD command returns the value of certain flags indicating the MPM3695-100’s status. To clear the bits in this register, the underlying fault must first be removed, then a CLEAR_FAULTS command must be issued. Bits Name Behavior Default Description 15 VOUT_STATUS Latch 0 0: No VOUT fault or warning has occurred 1: A VOUT fault or warning has occurred 14 IOUT_STATUS Latch 0 0: No IOUT fault has occurred 1: An IOUT fault has occurred 13 VIN_STATUS Latch 0 0: No VIN fault has occurred 1: A VIN fault has occurred. 12 MFR_STATUS N/A 0 Always reads as 0. 11 POWER_GOOD# Live 0 0: A power good (PG) signal has been asserted 1: A PG signal has not been asserted 10 RESERVED N/A 0 Always reads as 0. 9 RESERVED N/A 0 Always reads as 0. 8 UNKNOWN Latch 0 0: No other fault has occurred 1: A fault type not specified in bits[15:1] has been detected. N/A 0 See the description for STATUS_BYTE (78h). Low Byte STATUS_BYTE MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 34 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS STATUS_VOUT (7Ah) The STATUS_VOUT command returns 1 data byte with information related to VOUT faults. Bits Name Behavior Default Description 7 VOUT_OV_FAULT Latch 0 0: No VOUT over-voltage (OV) fault has occurred 1: A VOUT OV fault has occurred 6 RESERVED Latch 0 Always reads as 0. 5 RESERVED Latch 0 Always reads as 0. 4 VOUT_UV_FAULT Latch 0 0: No VOUT under-voltage (UV) fault has occurred 1: A VOUT UV fault has occurred 3 VOUT_MAX_MIN Latch 0 0: No VOUT_MAX or VOUT_MIN warning has occurred 1: An attempt has been made to set VOUT to a value above VOUT_MAX or below VOUT_MIN 2 RESERVED N/A 0 Always reads as 0. 1 RESERVED N/A 0 Always reads as 0. 0 UNKNOWN Latch 0 0: No other fault has occurred 1: A fault type not specified in bits[15:1] of STATUS_WORD has occurred STATUS_IOUT (7Bh) Command Format Bit Access Function 7 R IOUT_OC Default Value 0 6 R VIN_OV_ WARN 0 5 R IOUT_OC_ WARNING 0 STATUS_IOUT Unsigned binary 4 3 R R 2 R 1 R 0 R 0 0 0 X 0 0 STATUS_INPUT (7Ch) The STATUS_INPUT command returns the value of certain flags indicating the device’s VIN status. To clear the bits in this register, the underlying fault or warning must first be removed, then a CLEAR_FAULTS command must be issued. Bits Name Behavior Default Description 7 VIN_OV_FAULT R/Latch 0 0: No over-voltage (OV) condition has been detected on the OV pin 1: An OV condition has been detected on the OV pin 6 VIN_OV_WARN R/Latch 0 0: No OV condition has been detected on the VIN pin 1: An OV condition has been detected on the VIN pin 5 VIN_UV_WARN R/Latch 0 0: No under-voltage (UV) condition has been detected on the VIN pin 1: An UV condition has been detected on the VIN pin R 0 Always reads as 0000. 4:0 RESERVED MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 35 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS STATUS_TEMPERATURE (7Dh) The STATUS_TEMPERATURE returns the value of flags indicating an over-temperature (OT) fault or OT warning. To clear bits in this register, the underlying fault must first be removed, then a CLEAR_FAULTS command must be issued. Bits Name Behavior Default Description 7 OT_FAULT R/Latch 0 0: No over-temperature (OT) fault has occurred 1: An OT fault has occurred 6 OT_WARNING R/Latch 0 0: No OT warning has occurred 1: An OT warning has occurred R 0 Always reads as 0. 5:0 RESERVED STATUS_CML (7Eh) Command Format Bit Access Function 7 R Invalid or unsupported command Default Value STATUS_CML Unsigned binary 6 5 4 R R R Invalid or Memory fault X unsupported data detected 0 0 0 0 3 R 2 R X X 0 0 1 R Other fault 0 R Memory busy 0 0 READ_VIN (88h) The READ_VIN command returns the 10-bit measured VIN value. Command Format Bit Access Function Default Value 15 R 14 R 13 R 0 0 0 12 R 11 R 10 R 9 R 0 0 0 0 READ_VIN Direct 8 7 R R 6 R X 0 0 0 5 4 R R 25mV/LSB 0 0 3 R 2 R 1 R 0 R 0 0 0 0 4 R 3 R 2 R 1 R 0 R 0 0 0 0 0 READ_VOUT (8Bh) The READ_VOUT command returns the 13-bit measured VOUT value. Command Format Bit Access Function Default Value 15 R 14 R X 0 0 13 R 12 R 11 R 10 R 9 R 0 0 0 0 0 READ_VOUT Direct 8 7 6 5 R R R R 1.25mV/LSB 0 0 0 0 READ_IOUT (8Ch) The READ_IOUT command returns the 14-bit measured IOUT value. This value is also compared to IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT, and affects STATUS_IOUT. Command Format Bit Access Function Default value 15 R 14 R 13 R 12 R 11 R 10 R 9 R 0 0 0 0 0 1 X 0 READ_IOUT Direct 8 7 6 R R R 62.5mA/LSB 0 0 1 5 R 4 R 3 R 2 R 1 R 0 R 0 1 1 0 0 0 MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 36 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS READ_TEMPERATURE_1 (8Dh) The READ_TEMPERATURE_1 command returns the internal sensed temperature. This value is also used internally for over-temperature (OT) fault and warning detection. This value ranges between 40°C and 215°C. Command Format Bit Access Function Default Value 15 R 14 R 13 R 0 0 0 12 R 11 R READ_TEMPERATURE_1 Two’s complement integer 10 9 8 7 6 5 R/W R/W R/W R/W R/W R 0 0 0 X 0 0 0 0 1 4 3 2 1 0 R/W R/W R/W R/W R/W 0 1 0 1°C/LSB 1 0 READ_TEMPERATURE_1 is a 2-byte, two’s complement integer. Bit[9] is the signed bit. Table 10 shows the relationship between the direct values and real-world values. Table 10: Direct vs. Real-World Values Sign 0 0 0 1 1 Direct Value 0 0000 0000 0 0000 0001 1 1111 1111 0 0000 0001 1 1111 1111 Real-World Value (°C) 0 +1 +511 -511 -1 PMBUS_REVISION (98h) The PMBUS_REVISION command returns the PMBus protocol revision to which the device is compliant. Access to this command uses the read byte protocol. Bits[7:4] indicate the PMBus revision of specification Part I to which the device is compliant. Bits[3:0] indicate the revision of specification Part II to which the device is compliant. Command Format Bit Access Default Value 7 R 0 6 R 0 5 R 1 PMBUS_REVISION Unsigned binary 4 3 R R 1 0 2 R 0 1 R 1 0 R 1 Bits[7:4] always reads as 4’b0011 to indicate PMBus specification Part I, Revision 1.3. Bits[3:0] always reads as 4’b0011 to indicate PMBus specification Part II, Revision 1.3. MFR_CTRL_COMP (D0h) The MFR_CTRL_COMP command adjusts loop compensation. Bit s Name 7:5 RESERVED Acces s Behavio r Defaul t R/W Live 0000 Live 0 Description Reserved. Sets the feed-forward capacitance (CFF). 4 CFF R/W 0: 20pF 1: 50pF MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 37 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS Sets the internal ramp compensation to stabilize the loop. The actual ramp amplitude is related to the selection from register EAh, bit[3]. See the table below for more details. 3:1 0 RAMP SLAVE_FAULT_ DETECTION R/W R/W Live Live EAh, Bit[3] = 1 (Multi-Phase) 000: 8.6mV 001: 15mV 010: 27mV 011: 45mV 100: 13mV 101: 23mV 110: 41mV 111: 68mV 110 1 Enables the slave fault detection function through the PG pin. 0: Slave-phase fault detection is enabled 1: Slave-phase fault detection is disabled The default value of D0h is 0x0D. MFR_CTRL_VOUT (D1h) The MFR_CTRL_VOUT command adjusts the MPM3695-100’s VOUT behaviors. Bits 7 6 Name RESERVED VO_ DISCHARGE Access Behavior Default R/W Live 0 Reserved. 0 Enables active VOUT discharging when the MPM3695-100 is commanded to turn off through CTRL or an OPERATION off command. R/W Live Description 1: VOUT discharges at CTRL low 0: No active VOUT discharging Set the PG pull-high time after soft-start finishes. 5:2 PG_DELAY R/W Live 0000 0000: 2ms 0001: 3ms …………… 1110: 16ms 1111: 1ms Chooses the voltage divider radio. 1:0 VO_RANGE R/W Live 00 00: External voltage divider 01: Internal voltage divider: VREF / VOUT = 0.4V to 1.344V 10: Internal voltage divider: VREF / VOUT = 0.7V to 2.688V 11: Internal voltage divider: VREF / VOUT = 1.3V to 5.376V MFR_CTRL_OPS (D2h) The MFR_CTRL_OPS command sets the switching frequency (fSW) and light-load operation mode. Bits Name 7:3 RESERVED 2:1 SWITCHING_ FREQUENCY Access Behavior Default N/A N/A 00000 R/W Live 01 Description Reserved. 00: Set fSW to 400kHz 01: Set fSW to 600kHz 10: Set fSW to 800kHz 11: Set fSW to 1000kHz MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 38 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS 0 SKIP_CCM(SYNC) R/W Live 1 0: Pulse-skip mode (PSM) at light loads 1: Forced continuous conduction mode (FCCM) at light loads The default value of this register is 0x03. MFR_ADDR_PMBUS (D3h) Command Format Bit Access Function Default Value Bits 7 6:0 7 R/W ENABLE 0 6 R/W 5 R/W 0 1 MFR_ADDR_PMBUS Direct 4 3 R/W R/W ADDR 1 0 2 R/W 1 R/W 0 R/W 0 0 0 Name Description ENABLE 1: The address is determined by bits[6:0] of this command 0: The address is determined by the ADDR pin ADDR Determines the PMBus address if bit[7] of this command is set to 1. The default value of D3h is 0x30. MFR_VOUT_FAULT_LIMIT (D4h) The MFR_VOUT_FAULT_LIMIT command sets the over-voltage protection (OVP) thresholds. Bits Name 7:4 RESERVED Access Behavior Default N/A N/A 0000 3:2 OV_EXIT_TH R/W Live 1:0 OV_ENTER_TH R/W Live Description Reserved. 00 00: 10% of VREF 01: 50% of VREF 10: 80% of VREF 11: 102.5% of VREF 11 00: 115% of VREF 01: 120% of VREF 10: 125% of VREF 11: 130% of VREF All OVP thresholds are relative to VREF. MFR_OVP_NOCP_SET (D5h) The MFR_OVP_NOCP_SET command sets the VOUT over-voltage protection (OVP) responses and the negative over-current protection (NOCP) delay time. Bits Name Access Behavior Default 7:4 RESERVED N/A N/A 0000 3 DELAY_NOCP R/W Live 0 2 RESERVED N/A N/A N/A Reserved. 10 00: Latch-off mode with VOUT discharging 01: Latch-off mode without VOUT discharging in discontinuous conduction mode (DCM) 10: Hiccup mode with VOUT discharging 11: Hiccup mode without VOUT discharging in DCM 1:0 VOUT_OV_ RESPONSE R/W Live Description Reserved. 0: 100ns delay after NOCP 1: 200ns delay after NOCP MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 39 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS Bits[1:0] (VOUT_OV_RESPONSE) tell the converter how to respond to a VOUT over-voltage (OV) fault. If an OV fault occurs, the device also takes the following actions: 1. Sets the VOUT_OV bit in STATUS_BYTE. 2. Sets the VOUT bit in STATUS_WORD. 3. Sets the VOUT over-voltage fault bit in STATUS_VOUT. 4. Notifies the host by asserting the ALERT pin. The four OV responses are described in greater detail below.  Latch-off mode with VOUT discharging: If the device reaches the over-voltage (OV) threshold, the LSFET turns on until it reaches NOCP. Then the LS-FET turns off for a fixed time before turning on again. This process continues until VFB drops below the OVP exit threshold set by register D4h, bits[3:2]. Then the LS-FET turns off. If VFB exceeds the OV entry threshold again, then the LS-FET turns on again to discharge VOUT. The converter does not attempt to restart until power is cycled on either VIN, VCC, or CTRL.  Latch-off mode without VOUT discharging (only effective in DCM): If the device reaches the OV entry threshold, the LS-FET turns on. When the inductor current reaches 0A, the converter enters Hi-Z mode (output disabled) and the converter stops discharging VOUT. The converter does not attempt to restart until power is cycled on either VIN, VCC, or CTRL.  Hiccup mode with VOUT discharging: If the device reaches the OV entry threshold, the LS-FET turns on until the device reaches NOCP. Then the LS-FET turns off for a fixed time before turning on again. This process continues until VFB drops below the OVP exit threshold set by register D4h, bits[3:2]. Then the LS-FET turns off and a new soft start is initiated.  Hiccup mode without VOUT discharging: If the device reaches the OV entry threshold, the LS-FET turns on until the device reaches NOCP. Then a new soft start is initiated. The default value of this register is 0x02. MFR_OT_OC_SET (D6h) The MFR_OT_OC_SET command sets the over-current protection (OCP) response and the overtemperature protection (OTP) hysteresis. It is a 1-byte command. Bits Name 7:4 3 2:1 0 Access Behavior Default Description RESERVED N/A N/A N/A Reserved. OC_RESPONSE R/W Live 01 0: Latch-off mode 1: Retry mode OT_HYST R/W Live 00 00: 20°C 01: 25°C 10: 30°C 11: 35°C OT_RESPONSE R/W Live 1 0: Latch-off mode 1: Retry after the temperature drops by the value set by bits[2:1] of this command The OCP hiccup time is about 5 times the soft-start time set by TON_RISE (61h). The default value of this register is 0x09. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 40 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS MFR_OC_PHASE_SET (D7h) The MFR_OC_PHASE_SET command sets the inductor valley current limit for each individual phase. This is a cycle-by-cycle current limit. After 31 consecutive over-current (OC) cycles, OCP is triggered. This is a 1-byte command. Bits Name Access Behavior Default 7:5 RESERVED N/A N/A 000 4:0 OC_LIMIT R/W Live 10001 Description Reserved. Current limit. 1.5A/LSB. The value is unsigned and 1LSB = 1.5A. The default value is 25.5A for a single-phase inductor valley current limit. MFR_PGOOD_ON_OFF_LIMIT (D9h) The MFR_PGOOD_ON_OFF_LIMIT command sets the PGOOD on and off thresholds. Bits Name 7:4 RESERVED 3:2 1:0 PG_OFF PG_ON Access Behavior Default N/A N/A 000 Reserved. 00 00: 69% of VREF 01: 74% of VREF 10: 79% of VREF 11: 84% of VREF 00 00: 90% of VREF 01: 92.5% of VREF 10: 95% of VREF 11: 97.5% of VREF R/W Live R/W Live Description PG_OFF also sets the under-voltage protection (UVP) threshold. If VFB drops below the PG_OFF level, the MPM3695-100 triggers UVP. The device responds to UVP the same way it responds to over-current protection (OCP). Any fault condition pulls PG low. MFR_VOUT_STEP (DAh) The MFR_VOUT_STEP command sets the VOUT transition slew rate after soft start finishes. It does not determine the VOUT slew rate during soft start. Bits Name Access Behavior Default 7:4 RESERVED N/A N/A 0000 3:0 VOUT_STEP R/W Live 0100 Description Reserved. 0000: 20µs/2mV 1LSB = 2.5µs/2mV. The default value of this register is 0x04. MFR_CTRL (EAh) The MFR_CTRL command enables certain functions. Bits 15:10 Name RESERVED Access Behavior Default R Live N/A R/W Live 0 Description For manufacturer use only. Enables output sink mode (OSM). 9 OSM 0: Enable OSM 1: Disable OSM MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 41 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS 8:4 3 RESERVED PHASE_ OPERATION R Live R/W Live N/A 1 For manufacturer use only. Selects single-phase or multi-phase operation. This bit affects the actual ramp amplitude selected through register D0h, bits[3:1]. See the MFR_CTRL_COMP (D0h) section on page 37 for more details. 0: For single-phase operation 1: For multi-phase operation 2:0 RESERVED R Live N/A For manufacturer use only. Table 11: 0001 Suffix Code Configuration Items VOUT set method VOUT VFB Soft-start delay time Individual valley current limit Light-load mode Individual switching frequency Ramp UVLO rising UVLO falling Over-temperature (OT) fault limit OT warning limit VIN over-voltage (OV) fault limit Channel 1 External divider 1.2V 0.6V 4ms 25.5A FCCM 600kHz 41mV 4V 2.75V 160°C 140°C 18V Table 12: 0001 Suffix Register Value Register Hex Value Register 01 02 10 21 24 25 26 29 2b 35 36 4F 51 55 57 58 80 1E 0 258 BB8 2A0 1FE 1F4 FA 10 B A0 8C 24 22 1 60 61 64 9B D0 D1 D2 D3 D4 D5 D6 D7 D9 DA EA - Hex Value 0 2 0 36 D 0 3 30 3 2 9 11 0 4 E8 - MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 42 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS APPLICATION INFORMATION Operation Mode Selection The MPM3695-100 provides both forced continuous conduction mode (FCCM) and pulseskip mode (PSM) for light-load conditions. Four switching frequencies are available under lightload conditions. Set the switching frequency (fSW) through the PMBus. Setting the Output Voltage Two feedback resistors are required to set the proper feedback gain. The feedback resistor values (R1 and R2) can be calculated with Equation (1): 𝑅2 (𝑘Ω) = 0.6 𝑉𝑂𝑈𝑇 −0.6 × 𝑅1 (𝑘Ω) (1) Where VOUT is the output voltage. The VOUT feedback gain (GFB) can be estimated with Equation (2): 𝐺𝐹𝐵 = 𝑅2 (2) 𝑅1 +𝑅2 To optimize the load transient response, a feedforward capacitor (CFF) must be placed in parallel with R1. Table 6 on page 19 lists the values of feedback resistors and feed-forward capacitors for common output voltages. The MPM3695-100 offers VOUT configurability through the PMBus. In addition, VOUT can be adjusted through the PMBus by adjusting the internal reference voltage (VREF) of the PWM controller. VREF (default 0.6V) can be adjusted to be between 0.5V and 0.672V. For a given feedback resistor network, the maximum output voltage (VOUT_MAX) can be calculated with Equation (3): 𝑉𝑂𝑈𝑇_𝑀𝐴𝑋 = 0.672 𝐺𝐹𝐵 (3) The minimum output voltage (VOUT_MIN) can be estimated with Equation (4): 𝑉𝑂𝑈𝑇_𝑀𝐼𝑁 = 0.5 𝐺𝐹𝐵 (4) 2. Write the VOUT settings VOUT_COMMAND register. to the 3. VREF is automatically updated based on the commanded VOUT and GFB. VOUT monitoring through the PMBus is enabled by setting VOUT_SCALE_LOOP to a value that matches GFB. For applications where the PMBus interface is not required, VREF is 0.6V by default and the MPM3695-100 operates in analog mode. Calculate the feedback resistor values with Equation (1). Soft Start The soft-start time (tSS) can be configured using register 61h. The minimum tSS is 1ms, but it can also be set to 2ms, 4ms, 8ms, or 16ms. Pre-Biased Start-Up The MPM3695-100 is designed for monotonic start-up into pre-biased loads. If VOUT is prebiased to a certain voltage during start-up, both the HS-FET and LS-FET are disabled until the internal VREF exceeds VFB. Output Voltage Discharge VOUT discharge mode is enabled if the MPM3695-100 is disabled through the CTRL pin. In this case, both the high-side and low-side switches latch off and a discharge FET (connected between SW and GND) turns on to discharge the output capacitor. A typical discharge FET on resistance is 60Ω. Once VFB drops below 10% of VREF, the discharge FET turns off. Current Sense and Over-Current Protection (OCP) The MPM3695-100 features on-die current sensing and a configurable inductor valley current limit threshold. The inductor valley overcurrent limit can be configured via register D7h, which sets the per-phase inductor valley current limit for both single- and multi-phase operation. Follow the steps below to configure VOUT through the PMBus: 1. Calculate GFB with Equation (2), then write this value to the VOUT_SCALE_LOOP register. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 43 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS If VOUT drops below the under-voltage protection (UVP) threshold, the MPM3695-100 enters OCP immediately. Once OCP is triggered, MPM3695-100 either enters hiccup mode or latch-off mode, depending on the register setting. To re-enable the device, cycle the power on VCC or CTRL. Negative Inductor Current Limit When the LS-FET detects a negative current below the limit (about -13A), the LS-FET turns off for a certain period to limit the negative current. This period is set by register D5h, bit[3]. Under-Voltage Protection (UVP) The MPM3695-100 monitors VOUT through the VOSNS+ and VOSNS- pins. Under-voltage protection (UVP) is triggered if VFB drops below the UVP threshold. Once UVP is triggered, the MPM3695-100 enters either hiccup mode or latch-off mode, depending on the register setting. To re-enable the device, cycle the power on VCC or CTRL. Over-Voltage Protection (OVP) Over-voltage protection (OVP) is triggered if VFB exceeds the OVP threshold. See the MFR_OVP_NOCP_SET (D5h) section on page 39 for more details. Output Sinking Mode (OSM) The MPM3695-100 enters output sinking mode (OSM) if VOUT exceeds VREF by 5% while simultaneously being below the OVP threshold in PSM. Once OSM is triggered, the MPM3695100 runs in FCCM. The device exits OSM once the HS-FET turns back on. Over-Temperature Protection (OTP) The MPM3695-100 monitors the junction temperature. If the junction temperature exceeds the over-temperature protection (OTP) threshold, the MPM3695-100 enters either hiccup or latch-off mode depending on the PMBus selection. To re-enable the device, cycle the power on VCC or CTRL. Power Good (PG) The MPM3695-100 has an open-drain power good (PG) output. The PG pin must be pulled high to VCC (or a voltage source below 3.6V) through a pull-up resistor (typically 100kΩ). PG is initially pulled low once VIN is applied to the MPM3695-100. After VFB reaches the threshold set by POWER_GOOD_ON and the delay set by MFR_CTRL_VOUT completes, the PG pin is pulled high. PG latches low if any fault occurs and a protection is triggered (e.g. UV, OV, OT, UVLO). After PG latches off, it cannot be pulled high again unless a new soft start is initiated. If the input supply fails to power the MPM3695100, the PG pin latches off. Figure 5 shows the relationship between the PG voltage (VPG) and the pull-up current (IPG). 6 5 4 IPG (mA) While the LS-FET is on, the inductor current is sensed and monitored cycle by cycle. The HSFET does not turn on if an over-current (OC) condition is detected while the LS-FET is on. Therefore, the inductor current is also limited cycle by cycle. If an OC condition remains for 31 consecutive cycles, OCP is triggered. 3 2 1 0 0.5 0.6 0.7 0.8 VPG (V) 0.9 1 Figure 5: Power-Good Current vs. Power Good Voltage Selecting the Input Capacitor The buck converter has a discontinuous input current, and requires a capacitor to supply the AC current to the module while maintaining the DC input voltage. Use ceramic capacitors for the best performance. When designing the PCB layout, place the input capacitors as close to the VIN pin as possible. The capacitance can vary significantly with temperature. Ceramic capacitors with X5R and X7R dielectrics are recommended because they are fairly stable across a wide temperature range. The capacitors must also have a ripple current rating that exceeds the converter’s maximum input ripple current. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 44 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS Estimate the input ripple current with Equation (5): ICIN  IOUT  VOUT V  (1  OUT ) VIN VIN (5) The worst-case condition occurs at VIN = 2 x VOUT, calculated with Equation (6): ICIN  IOUT 2 (6) For simplification, choose an input capacitor with an RMS current rating that exceeds half of the maximum load current. The input capacitance determines the converter input voltage ripple. Select a capacitance that meets the relevant input voltage ripple requirements. Estimate the input voltage ripple with Equation (7): VIN  IOUT V V  OUT  (1  OUT ) f SW  CIN VIN VIN (7) The worst-case condition occurs at VIN = 2 x VOUT, calculated with Equation (8): VIN  1 IOUT  4 f SW  CIN (8) Selecting the Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic capacitors or POSCAP capacitors. Estimate the output voltage ripple with Equation (9): VOUT  VOUT V 1  (1  OUT )  ( RESR  ) f SW  L VIN 8  f SW  COUT (9) When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency and causes the majority of the output voltage ripple. For simplification, estimate the output voltage ripple with Equation (10): VOUT  VOUT V  (1  OUT ) 2 VIN 8  f SW  L  COUT (10) The ESR contributes minimally to the output voltage ripple, so an external ramp must be implemented to stabilize the system. Design the external ramp using R4, C4, and the equations above. When using POSCAP capacitors, the ESR dominates the impedance at the switching frequency. The ESR ramp voltage is high enough to stabilize the system, thus eliminating the need for an external ramp. Select a minimum ESR value (about 12mΩ) to ensure stable operation. For simplification, the output ripple can be calculated with Equation (11): VOUT  VOUT V  (1  OUT )  RESR f SW  L VIN MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. (11) 45 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS PCB Layout Guidelines For the best results, refer to Figure 6 and follow the guidelines below: VIN 1. Place sufficient decoupling capacitors as close as possible to each set of VIN and GND pins. A minimum of eight 22uF/25V ceramic capacitors are recommend. 2. Place sufficient GND vias around the GND pad of the decoupling capacitors. 3. Avoid placing sensitive signal traces close to the input copper and/or vias without sufficient ground shielding. VOUT 4. Connect all VOUT pins together on a copper plane. 5. Place sufficient vias near the VOUT pads to provide a current path with minimal parasitic impedance. GND 6. Connect all GND pins of the module using copper. 7. Place sufficient vias close to the GND pins to provide a current return path with minimal thermal resistance and parasitic impedance. VOSNS+ and VOSNS8. Route VOSNS+ and VOSNS- as differential signals. 9. When modules are paralleled, connect all VOSNS+ pins of the master and slaves, and connect all VOSNS- master and slaves. 10. Avoid routing VOSNS+/- traces close to the input plane and high-speed signals. SET> and SET< 11. SET< and SET> are connected inside the power module. In parallel operation, choose one SET pin for optimized routing (minimal trace distance) based on the power module placement. 12. Avoid routing SET traces close to the input plane and high-speed signals. ISUM> and ISUM< 13. ISUM< and ISUM> are connected inside the power module. In parallel operation, choose one ISUM pin for optimized routing (minimal trace distance) based on the power module placement. 14. Avoid routing ISUM traces close to the input plane and high-speed signals. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 46 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS VIN RUN ISUM< VCC CTRL PG VIN TP1 TP2 VIN TP3 TP4 VIN TP5 TAKE PASS SET< SET> GND ISUM> VCC VCC VCC GND GND VOSNS- ADDR ADDR GND ALT VOSNS+ ADDRADDR VOUT SDA SCL VOUT VOUT VOUT Figure 6: Recommended PCB Layout for Single-Module Operation MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 47 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TYPICAL APPLICATION CIRCUITS 4V to 16V Input 10kΩ 1.2V Output 100A VIN 22µF x 8 25V OUT MPM3695-100 CTRL CTRL 33nF 1kΩ VOSNS+ 100µF x 4 PG 1kΩ ALT SCL SDA RADDR RUN Figure 7: Typical Application Circuit (Single-Module Operation) 4V to 16V Input 10kΩ 1.2V Output, 200A VIN VOUT 22µF x 8 25V MPM3695-100 1kΩ 33nF CTRL CTRL PG 100µF x 4 VOSNS+ 1kΩ ALT SCL SDA RADDR RUN VIN 22µF x 8 25V VOUT MPM3695-100 CTRL 100µF x 4 VOSNS+ RADDR RUN Figure 8: Typical Application Circuit (Dual-Module Operation) MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 48 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TYPICAL APPLICATION CIRCUITS (continued) 4V to 16V Input 10kΩ 1.2V Output, 300A VIN 22µF x 8 25V VOUT MPM3695-100 1kΩ 33nF CTRL CTRL PG 100µF x 4 VOSNS+ 1kΩ ALT SCL RADDR SDA RUN VIN 22µF x 8 25V VOUT MPM3695-100 CTRL 100µF x 4 VOSNS+ RADDR RUN VIN 22µF x 8 25V VOUT MPM3695-100 CTRL 100µF x 4 VOSNS+ RADDR RUN Figure 9: Typical Application Circuit (Three-Module Operation) MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 49 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS TYPICAL APPLICATION CIRCUITS (continued) VIN 22µF x 8 25V VOUT MPM3695-100 CTRL 100µF x 4 VOSNS+ RADDR RUN 4V to 16V Input 10k 1.2V Output, 400A VIN 22µF x 8 25V CTRL VOUT MPM3695-100 33nF 1kΩ CTRL PG 100µF x 4 VOSNS+ 1kΩ ALT SCL RADDR SDA RUN VIN 22µF x 8 25V VOUT MPM3695-100 CTRL 100µF x 4 VOSNS+ RADDR RUN VIN 22µF x 8 25V VOUT MPM3695-100 CTRL 100µF x 4 VOSNS+ RADDR RUN Figure 10: Typical Application Circuit (Four-Module Operation) MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 50 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS PACKAGE INFORMATION BGA (15mmx30mmx5.18mm) PIN 1 ID PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-275A. 4) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 51 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS CARRIER INFORMATION (11) Detail A Package in Tray Pin 1 ABCD 1 Detail A Part Number Package Description Quantity/ Reel Quantity/ Tray Quantity/ Tube Carrier Tape Width Carrier Tape Pitch MPM3695GBH-100–T BGA (15mmx30mmx5.18mm) N/A 48 N/A N/A N/A Note: 11) This is a schematic diagram of the tray. Different packages correspond to different trays with different lengths, widths, and heights. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 52 MPM3695-100 – 16V, 100A, SCALABLE DC/DC POWER MODULE WITH PMBUS REVISION HISTORY Revision # 1.0 Revision Date 3/25/2021 Description Initial Release Pages Updated - Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPM3695-100 Rev. 1.0 MonolithicPower.com 3/25/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 53