MPM54304
4V to 16V Input, Quad-Output Power Module
with I2C and MTP in Ultra-Thin Package
DESCRIPTION
FEATURES
The MPM54304 is a quad-output, DC/DC stepdown power module with up to 3A per output
(channel 1 and 2) and 2A per output (channel 3
and 4). Channels 1 and 2 can be paralleled to
provide up to 6A of current, and channels 3 and
4 can be paralleled to provide up to 4A of
current.
4V to 16V Operating Input Range
Wide Output Voltage:
o I2C Programmable: 0.55V to 5.4V
o External Resistor Divider: 0.6V to 7V or
VIN * DMAX if VIN < 7V
Channel 1 and 2: 3A Continuous Current
Channel 3 and 4: 2A Continuous Current
Interleaved Operation
Configurable, Multi-Functional GPIO Pin
I2C and Configurable Parameters:
o Paralleling Channel 1 and 2
o Paralleling Channel 3 and 4
o Switching Frequency
o Output Voltage
o Over-Current and Over-Voltage
Protection Threshold
o Power-On and Power-Off Sequencing
o Forced PWM or Auto-PWM/PFM
Operating over a 4V to 16V input voltage range,
the MPM54304 can support an output voltage
range of 0.55V to 7V. The output voltage can
be set via the I2C or external resistor divider.
The module has internal auto-compensation,
which eliminates the need for an external
compensation network. The MPM54304
employs a constant-on-time (COT) control
scheme to provide ultra-fast load transient
responses. This minimizes the required output
capacitance.
APPLICATIONS
The MPM54304 features a two-time, nonvolatile programmable memory. Its operating
parameters are programmable via the I2C.
The MPM54304 requires a minimal number of
external components, and is available in ultrathin LGA-33 (7mmx7mmx2mm) package.
FPGA Power Supplies
Multi-Rail Power Systems
MCU/DSP Power Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
TYPICAL APPLICATION
SW1
4V to 16V
SW2
FB1
SGND1
VIN
C1
22µF
GND
0.85V/3A
VOUT1
VOUT1
VOUT2
FB2
C4
22µFx2
1V/3A
VOUT2
C5
22µFx2
VIN
C2
22µF
MPM54304
VOUT3
GND
FB3
SGND2
I2 C {
1.8V/2A
VOUT3
C6
22µF
Note:
SCL
SDA
VOUT4
FB4
EN
VCC
AGND
3.3V/2A
VOUT4
C7
22µF
GPIO
C3
1µF
1)
Maximum current per rail is subject to total package power
loss derating. See the Max PLOSS vs. Temperature Curve on
page 11 for the maximum allowed package power loss rating.
The total package power loss is determined as the sum of
power loss of all rails: PLOSS = (PLOSS1 + PLOSS2 + … + PLOSSn),
where n represents the utilized number of rails.
4V to 16V Input and Quad Output
MPM54304 Rev. 1.0
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11/6/2019
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© 2019 MPS. All Rights Reserved.
1
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
ORDERING INFORMATION
Part Number*
MPM54304GMN-XXXX
MPM54304GMN-0000
MPM54304GMN-0001
MPM54304GMN-0002
MPM54304GMN-0003
MPM54304GMN-0004
Package
LGA-33
(7mmx7mm)
LGA-33
(7mmx7mm)
LGA-33
(7mmx7mm)
LGA-33
(7mmx7mm)
LGA-33
(7mmx7mm)
LGA-33
(7mmx7mm)
Top Marking
Note
MSL
Rating
See Below
See Below
Pre-programmed output voltage or I2C
adjustable
See Below
Set output voltage with resistor divider
See Below
See Below
See Below
Set output voltage with resistor divider;
buck 1 & 2 in parallel
Set output voltage with resistor divider;
buck 3 & 4 parallel
Set output voltage with resistor divider;
buck 1 & 2, buck 3 & 4 in parallel
3
* -XXXX is the configuration code identifier for register settings stored in the MTP memory. For default configuration with an
I2C programmed output voltage, the code is “0000”. See Tables 3 to 12 on page 42 for the detailed configuration information
and the register map of codes “0001” to “0004”.
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP54304: Part number
LLLLLLLLL: Lot number
M: Module
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
PACKAGE REFERENCE
TOP VIEW
VOUT3
FB3
SGND2 VIN
VIN
GND
GPIO
VCC
32
VOUT3
FB4
VOUT4
23
1
22
GND
GND
GND
SDA
33
GND
SCL
EN
GND
FB2
VOUT4
FB1
6
17
7
GND
SGND1
16
VOUT2 VOUT2 GND
SW2
SW1
GND
VOUT1 VOUT1 GND
LGA-33 (7mmx7mm)
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
PIN FUNCTIONS
Pin #
Name
1, 32
VOUT3
2, 5, 7, 10, 13,
16, 20, 21, 27, 33
3
4
Power ground. Connect to GND with wide copper plane and sufficient vias.
SDA
SCL
I2C data signal pin.
I2C clock signal pin.
Feedback of buck 2. Connect buck 2’s output directly to this pin or through a
feedback resistor divider.
Channel 2 output.
Buck 2 switching node. Connect to SW1 in parallel mode.
Buck 1 switching node. Connect to SW2 in parallel mode.
FB2
8, 9
11
12
VOUT2
SW2
SW1
18
19
22, 23
24
25
26
Channel 3 output.
GND
6
14, 15
17
Description
Channel 1 output.
Signal ground 1. Channel 1 and 2 output voltage feedback sense ground.
Feedback of buck 1. Connect buck 1’s output directly to this pin or through a
FB1
feedback resistor divider.
Enable control. Apply a logic high voltage on this pin to enable the IC; pull
EN/SYNCI to logic low to disable the IC. The EN pin has a 2MΩ internal pullEN/SYNCI
down resistor. Apply a clock on EN/SYNCI to synchronize the switching
frequency to the external clock.
VOUT4 Channel 4 output.
Feedback of buck 4. Connect buck 4’s output directly to this pin or through a
FB4
feedback resistor divider.
Internal 3.3V LDO output. The driver and control circuits are powered from
VCC
this voltage. Connect a 1µF decoupling capacitor to this pin.
General purpose input/output (GPIO) pin – ADD mode. When the MTP/I2C
configure this pin as “ADD,” the pin can program four different I2C slave
addresses.
General purpose input/output (GPIO) pin – PG mode. When the MTP/I2C
configure this pin as “PG,” it is the open-drain power good output. Pull low
when any enabled regulator falls below the UV threshold or when all
regulators are disabled.
GPIO
General purpose input/output (GPIO) pin – Output Port mode. When the
MTP/I2C configure this pin as “Output Port,” it outputs high/low logics
determined by the related register. Open-drain structure.
General purpose input/output (GPIO) pin – SYNCO mode. When the
MTP/I2C configure this pin as “SYNCO,” it is the sync output. Phase-shift the
clock output to sync another device’s switching frequency.
VOUT1
SGND1
28, 29
30
VIN
SGND2
31
FB3
Supply voltage input. Requires a ceramic capacitor to decouple the input rail.
Signal ground 2. Channel 3 and 4 output voltage feedback sense ground.
Feedback of buck 3. Connect buck 3’s output directly to this pin or through a
feedback resistor divider.
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (2)
Thermal Resistance (6)
VIN ................................................ -0.3V to +18V
VSWx ...................................................................
-0.6V (-7V for UVLO Rising
Power Off
Detect power-on
factor
Disable power-on factor
detection
PG switches
low
Power-Off
Sequence
Power-On
Sequence
Power On
Detect poweroff factor
DC/DC turns on
sequentially depending
on the I2C register setting
PG switches
high
Figure 6: Power Control State Machine Diagram
State Machine Description
The state machine has the following statuses:
Shutdown
The PMIC’s EN/SYNCI pin is pulled low. All of
the PMIC’s switcher functions are disabled, but
the I2C and MTP are live as long as the input is
above the UVLO threshold.
No Supply
The PMIC’s input pin has a UVLO detection
circuit. If input voltage VIN is below the UVLO
rising threshold, all PMIC functions are disabled.
Power Off
All buck regulators are turned off. In this state,
the PMIC is always monitoring the power-on
factor. Once a power-on factor is detected, it
changes to the power-on sequence state.
Power-On Sequence
Buck 1 to buck 4 turn on sequentially, according
to the order programmed by the MTP e-fuse. If
a power-off factor is detected during the poweron sequence, the PMIC returns to its power-off
state.
Power On
Buck 1 to buck 4 are turned on. The PG output
switches high. In this state, the PMIC is always
monitoring the power-off factor.
Power-Off Sequence
The PMIC changes to this state when it detects
a power-off factor in the power-on state. Buck 1
to buck 4 either turn off sequentially in the
reverse order of the power-on sequence, or turn
off at the same time, depending on the
Shutdown_Delay_EN bit’s setting.
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
Power-On Factors
The PMIC has the following power-on factors:
die temperature exceeding the thermal
protection
threshold.
Once
the
die’s
temperature decreases, the PMIC enters the
power-on sequence again.
EN/SYNCI Pin
If the EN/SYNCI pin is pulled high, the system
changes from its power-off state to the poweron sequence. The related EN bit determines
each buck’s on or off state.
Power-On Sequence
There are four slots for power-on sequence
timing. All buck regulators can be programmed
with 0 to 2 time slots by the MTP e-fuse (see
Figure 7).
Thermal Recovery
The part may be in its power-off state due to the
Time Slot Number
0
1
2
3
VIN1,
VIN2,
VCC
EN
All registers and MTP are enabled
I2C
Interface
DC/DC
Outputs
1ms
1ms
200µs
PG
Shutdown
No Supply
1ms
Power Off
Figure 7: Power-On Sequence
Buck Regulators Turn On
The MPM54304 provides a programmable
power-on sequence. The MTP configuration
tables on page 42 have bits to set the time slot
number (start-up delay timer) for each channel.
The default power-on sequence is shown in the
default MTP configuration table (see page 42).
Power-Off Factor
EN/SYNCI Pin Hardware-Initiated Power-Off
The MPM54304 supports controlled power-off
the through the EN/SYNCI pin. When the
EN/SYCNI pin is pulled low, the system enters
the
power-off
sequence.
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
Power-Off Sequence
VIN1,
VIN2,
VCC
Time Slot Number
3
2
1
0
UVLO
EN turn-on signal is blanked
EN
DC/DC
Outputs
1ms
1ms
1ms
PG
Power On
Power-Off Sequence
Power Off
No Supply
Figure 8: Power-Off Sequence when Shutdown_Delay_EN = 1
PG is pulled low before the device starts to turn
off. The DC/DC power-off sequence is in the
reverse order of the power-on sequence when
Shutdown_Delay_EN is set to 1.
In order to fully discharge the output voltage,
the EN signal is blanked during the power-off
VIN1,
VIN2,
VCC
sequence period. Within this power-off
sequence period, the MPM54304 continues
working in output discharge mode regardless of
whether the external EN/SYNCI pin is pulled
high or low.
Time Slot Number
UVLO
EN turn-on function is
blanked
EN
All DC/DC
Outputs
PG
Power On
Power-Off Sequence
No Supply
Figure 9: Power-Off Sequence when Shutdown_Delay_EN = 0
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
All the DC/DC outputs power off at the same
time when Shutdown_Delay_EN is set to 0.
Shutdown Sequence
When the input voltage is below the UVLO
falling threshold or the IC is over-temperature,
the PMIC enters the shutdown sequence
immediately. All the DC/DC regulators turn off
at the same time (see Figure 10).
Detect shutdown
event
DC/DC1
...
DC/DC4
PG
Figure 10: Shutdown Sequence
Thermal Warning and Shutdown
Thermal warning and shutdown prevent the part
from
operating
at
exceedingly
high
temperatures. When the silicon die temperature
exceeds 120°C, the MPM54304 sets the OT
WARNING bit to 1.
If the die temperature exceeds 160°C, the
system begins the shutdown sequence. When
the temperature recovers to 140°C, the
regulator begins the power-on sequence again.
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
I2C INTERFACE
I2C Serial Interface Description
The I2C is a two-wire, bidirectional serial
interface, consisting of a data line (SDA) and a
clock line (SCL). The lines are externally pulled
to a bus voltage when they are idle. Connecting
to the line, a master device generates the SCL
signal and device address, then arranges the
communication sequence. The MPM54304
interface is an I2C slave. The I2C interface adds
flexibility to the power supply solution. The
output voltage, transition slew rate, and other
parameters can be instantaneously controlled
by the I2C interface.
Data Validity
One clock pulse is generated for each data bit
transferred. The data on the SDA line must be
stable during the high period of the clock. The
high or low state of the data line can only
change when the clock signal on the SCL line is
low (see Figure 11).
Data line
Stable;
Data valid
Change
of data
allowed
after a stop condition. The bus stays busy if a
repeated start (Sr) is generated instead of a
stop condition. The start and repeated start
conditions are functionally identical.
Transfer Data
Every byte put on the SDA line must be 8 bits
long. Each byte has to be followed by an
acknowledge (ACK) bit. The acknowledgerelated clock pulse is generated by the master.
The transmitter releases the SDA line (high)
during the acknowledge clock pulse. The
receiver must pull down the SDA line during the
acknowledge clock pulse so that it remains
stable low during the high period of this clock
pulse.
Figure 13 shows the format that data transfers
follow. After the start condition, a slave address
is sent. This address is 7 bits long, followed by
an 8th data direction bit (R/W). A 0 indicates a
transmission (write), and a 1 indicates a request
for data (read). A data transfer is always
terminated by a stop condition generated by the
master. However, if a master still wishes to
communicate on the bus, it can generate a
repeated start condition and address another
slave without first generating a stop condition.
Figure 11: Bit Transfer on the I2C Bus
The start (S) and stop (P) commands are
signaled by the master device, which signifies
the beginning and the end of the I2C transfer. A
start condition is defined as the SDA signal
transitioning from high to low while the SCL is
high. A stop condition is defined as the SDA
signal transitioning from low to high while the
SCL is high (see Figure 12).
Start Condition
Stop Condition
Figure 12: Start and Stop Conditions
Start and stop conditions are always generated
by the master. The bus is considered to be
busy after a start condition. The bus is
considered to be free again a minimum of 4.7μs
1To7
Start
Condition
8
9
1To7
8
9
1To7
8
9
Address
Stop
Condition
Figure 13: A Complete Data Transfer
The MPM54304 includes a full I2C slave
controller. The I2C slave fully complies with the
I2C specification requirements. It requires a
start condition, a valid I2C address, a register
address byte, and a data byte for a single data
update. After receipt of each byte, the
MPM54304 acknowledges by pulling the SDA
line low during the high period of a single clock
pulse. A valid I2C address selects the
MPM54304. The MPM54304 then performs an
update on the falling edge of the LSB byte.
Figure 14 shows examples of an I2C write and
read sequence.
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
8 bits
S
8 bits
Slave Address
WR
A
8 bits
Register Address K
A
Write Data
A
P
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
WR Write = 0
Slave to Master
NA = NOT Acknowledge (SDA = High)
P = Stop Condition
RD Read = 1
Figure 14a: I2C Write Example – Write Single Register
S
Slave Address
8 bits
8 bits
8 bits
WR
A
Register Address K
A
Write Data K
A
Write Data K + 1
A
Write Data K + N
A
P
Multi-byte write executed from current register location (the
read-only register will be skipped)
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
WR Write = 0
Slave to Master
NA = NOT Acknowledge (SDA = High)
P = Stop Condition
RD Read = 1
Figure 14b: I2C Write Example – Write Multi-Register
8 bits
S
Slave Address
8 bits
WR
A
Register Address K
8 bits
8 bits
A
Register address to read specified
Sr
Slave Address
RD
A
Read Data K
NA
P
Read register data from current register location
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
Slave to Master
NA = NOT Acknowledge (SDA = High)
P = Stop Condition
Sr = Repeat
Start Condition
WR Write = 0
RD Read = 1
Figure 14c: I2C Read Example – Read Single Register
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
APPLICATION INFORMATION
Internal Inductor
Fixed inductors in the module are 1µH
(channels 1 and 2) and 2.2µH (channels 3 and
4).
Selecting the Input Capacitor
The step-down converter has a discontinuous
input current, and requires a capacitor to supply
AC current to the converter while maintaining
the DC input voltage. Use low-ESR capacitors
for the best performance. Ceramic capacitors
with X5R or X7R dielectrics are recommended
because of their low ESR and small
temperature coefficients. For most applications,
a 22µF capacitor is sufficient.
Since C1 absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (2):
IC1 ILOAD
VOUT VOUT
1
VIN
VIN
(2)
The worst-case condition occurs at VIN = 2VOUT,
calculated with Equation (3):
IC1
ILOAD
2
(3)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high-quality ceramic
capacitor (e.g. 0.1μF) as close to the IC as
possible. When using ceramic capacitors,
ensure that they have enough capacitance to
provide sufficient charge to prevent excessive
voltage ripple at the input. The input voltage
ripple caused by the capacitance can be
estimated with Equation (4):
VIN
IOUT
V
V
OUT (1 OUT )
fSW CIN VIN
VIN
Selecting the Step-Down Regulator
Output Capacitor
The output capacitor for the step-down
regulator maintains the DC output voltage. Use
ceramic, tantalum, or low-ESR electrolytic
capacitors. For best results, use low-ESR
capacitors to keep the output voltage ripple low.
The output voltage ripple can be estimated with
Equation (5):
VOUT
VOUT
V
1
(1 OUT ) (RESR
)
fSW L
VIN
8 fSW COUT
(5)
Where L1 is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency and causes the majority of the output
voltage ripple. For simplification, the output
voltage ripple can be estimated with Equation
(6):
VOUT
VOUT
V
(1 OUT )
8 fSW 2 L COUT
VIN
(6)
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be estimated with Equation (7):
VOUT
VOUT
V
(1 OUT ) RESR
fSW L
VIN
(7)
The characteristics of the output capacitor also
affect the stability of the regulation.
(4)
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
PCB Layout Guidelines (13)
Efficient PCB layout is critical for stable
operation. A 4-layer layout is recommended to
achieve better thermal performance. For best
results, refer to Figure 15 and follow the
guidelines below:
1. Keep the power loop as small as possible.
2. Use a large ground plane to connect directly
to PGND. If the bottom layer is a ground
plane, add vias near PGND.
3. Ensure the high-current paths at GND and
VIN have short, direct, and wide traces.
4. Place the ceramic input capacitor as close
to the device as possible.
5. Keep the input capacitor and IN as short
and wide as possible.
Figure 15: Recommended PCB Layout
Notes:
13) The recommended layout is based on the Typical Application
Circuit section on page 40.
6. Place the VCC capacitor as close to the
VCC and GND pins as possible.
7. Connect VIN, VOUT, and GND to a large
copper
area
to
improve
thermal
performance and long-term reliability.
8. Separate the input GND area from other
GND areas on the top layer, and connect
them together on the internal layers and
bottom layer through multiple vias.
9. Ensure there is an integrated GND area on
the internal layer or bottom layer.
10. Use multiple vias to connect the power
planes to internal layers.
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
TYPICAL APPLICATION CIRCUITS
SW1
SW2
VOUT1
VOUT1 = 0.85V
C4
22µFx2
FB1
SGND1
VIN1 =
4V to 16V
VIN
C1
22µF
VOUT2
GND
VOUT2 = 1V
C5
22µFx2
FB2
VIN
C2
22µF
MPM54304
GND
VOUT3 = 1.8V
VOUT3
C6
22µF
FB3
SGND2
I2C
{
SCL
SDA
VOUT4
VOUT4 = 3.3V
C7
22µF
FB4
EN
VCC
AGND
GPIO
C3
1µF
Figure 16: 4V to 16V Input and Quad-Output
SW1
SW2
VOUT1
VOUT1 = 0.85V
R1
FB1
VIN = 4V to
16V
C1
22µF
C4
22µFx2
R1A
VIN
SGND1
GND
VOUT2
VOUT2 = 1V
R2
FB2
R2A
C5
22µFx2
VIN
C2
22µF
MPM54304
GND
VOUT3 = 1.8V
VOUT3
R3
FB3
R3A
I2C
{
SCL
SGND2
SDA
VOUT4
R4
FB4
R4A
EN
VCC
AGND
C6
22µF
VOUT4 = 3.3V
C7
22µF
GPIO
C3
1µF
Figure 17: 4V to 16V Input and Quad-Output with External Divider
MPM54304 Rev. 1.0
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MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
TYPICAL APPLICATION CIRCUITS (continued)
SW1
SW2
VOUT1
FB1
VIN1 = 4V to
16V
SGND1
C4
22µFx2
VIN
C1
22µF
VOUT2
GND
FB2
C5
22µFx2
VIN
C2
22µF
MPM54304
GND
VOUT3
FB3
SGND2
I2C
{
C6
22µF
SCL
SDA
VOUT4
FB4
EN
VCC
AGND
C7
22µF
GPIO
C3
1µF
Figure 18: 4V to 16V Input, Dual-Output with Parallel Operation Mode
MPM54304 Rev. 1.0
www.MonolithicPower.com
11/6/2019
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© 2019 MPS. All Rights Reserved.
41
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
DEFAULT MTP CONFIGURATION
Table 3: 0000 Suffix Code Configuration
OTP Items
Output Voltage Set Method
Output Voltage
Initial On/Off
Mode
Soft-Start Delay Time Slot
Soft-Start Time (VO = 0% to 100%)
Valley Current Limit
Buck Output Discharge EN
Buck Output Limit EN
Buck Parallel Mode Operation
Switching Frequency
VIN UVLO Rising
GPIO
Shutdown Delay EN
PG Delay Time
Software Initial I2C Slave Address
MTP Configure Code
Buck 1
Buck 2
Buck 3
I2C
I2C
I2C
Buck 4
I2C
1V
3.3V
1.8V
1.5V
On
On
On
On
FCCM
FCCM
FCCM
FCCM
0ms
3ms
1ms
2ms
1ms
1.6ms
1.1ms
0.9ms
4.2A
3A
2A
3A
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled Disabled
Disabled
Unparalleled
Unparalleled
800kHz
4.5V
PG
Enabled
0.2ms
0x68
0x00
Table 4: 0000 Suffix Code Register Value
Suffix Code
Register
Hex Value
0000
0x40
02h
0000
0x41
EBh
0000
0x42
2Dh
0000
0x43
33h
0000
0x44
5Dh
0000
0x45
B7h
0000
0x46
11h
0000
0x47
4Fh
0000
0x48
7Dh
0000
0x49
21h
0000
0x4A
59h
0000
0x4B
5Fh
0000
0x4C
F3h
0000
0x4D
68h
0000
0x4E
40h
0000
0x4F
00h
MPM54304 Rev. 1.0
www.MonolithicPower.com
11/6/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
42
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
Table 5: 0001 Suffix Code Configuration
Suffix Code: 0001
OTP Items
Output Voltage Set Method
FB Voltage
Initial On/Off
Mode
Buck 1
Buck 2
Buck 3
Buck 4
External divider
External divider
External divider
External divider
0.6V
0.6V
0.6V
0.6V
On
On
On
On
FCCM
FCCM
FCCM
FCCM
Soft-Start Delay Time Slot #
Soft-Start Time (VO = 0% to
100%)
Valley Current Limit
0ms
2ms
1ms
3ms
0.9ms
0.9ms
0.9ms
0.9ms
4.2A
4.2A
3A
3A
Buck Output Discharge EN
Enabled
Enabled
Enabled
Enabled
Buck Output Limit EN
Enabled
Enabled
Disabled
Disabled
Buck Parallel Mode Operation
Unparalleled
Switching Frequency
Unparalleled
800kHz
VIN UVLO Rising
4.5V
GPIO
PG
Shutdown Delay EN
Enabled
PG Delay Time
Software Initial I2C Slave
Address
MTP Configure Code
0.2ms
MTP Revision Number
0x00
0x68
0x01
Table 6: 0001 Suffix Code Register Value
Suffix Code
Register
Hex Value
0001
0x40
03h
0001
0x41
EBh
0001
0x42
05h
0001
0x43
23h
0001
0x44
EDh
0001
0x45
05h
0001
0x46
13h
0001
0x47
5Fh
0001
0x48
05h
0001
0x49
33h
0001
0x4A
5Fh
0001
0x4B
05h
0001
0x4C
F3h
0001
0x4D
68h
0001
0x4E
40h
0001
0x4F
01h
MPM54304 Rev. 1.0
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11/6/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
43
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
Table 7: 0002 Suffix Code Configuration
Suffix Code: 0002
OTP Items
Output Voltage Set Method
FB Voltage
Initial On/Off
Mode
Buck 1
Buck 2
Buck 3
Buck 4
External divider
External divider
External divider
External divider
0.6V
0.6V
0.6V
0.6V
On
On
On
On
FCCM
FCCM
FCCM
FCCM
Soft-Start Delay Time Slot #
Soft-Start Time (VO = 0% to
100%)
Valley Current Limit
0ms
0ms
1ms
3ms
0.9ms
0.9ms
0.9ms
0.9ms
4.2A
4.2A
3A
3A
Buck Output Discharge EN
Enabled
Enabled
Enabled
Enabled
Buck Output Limit EN
Enabled
Enabled
Disabled
Disabled
Buck Parallel Mode Operation
Paralleled
Switching Frequency
Unparalleled
800kHz
VIN UVLO Rising
4.5V
GPIO
PG
Shutdown Delay EN
Enabled
PG Delay Time
Software Initial I2C Slave
Address
MTP Configure Code
0.2ms
MTP Revision Number
0x00
0x68
0x02
Table 8: 0002 Suffix Code Register Value
Suffix Code
Register
Hex Value
0002
0x40
03h
0002
0x41
EBh
0002
0x42
05h
0002
0x43
23h
0002
0x44
EDh
0002
0x45
05h
0002
0x46
13h
0002
0x47
5Fh
0002
0x48
05h
0002
0x49
33h
0002
0x4A
5Fh
0002
0x4B
05h
0002
0x4C
F3h
0002
0x4D
68h
0002
0x4E
41h
0002
0x4F
02h
MPM54304 Rev. 1.0
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11/6/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
44
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
Table 9: 0003 Suffix Code Configuration
Suffix Code: 0003
OTP Items
Output Voltage Set Method
FB Voltage
Initial On/Off
Mode
Buck 1
Buck 2
Buck 3
Buck 4
External divider
External divider
External divider
External divider
0.6V
0.6V
0.6V
0.6V
On
On
On
On
FCCM
FCCM
FCCM
FCCM
Soft-Start Delay Time Slot #
Soft-Start Time (VO = 0% to
100%)
Valley Current Limit
0ms
2ms
1ms
1ms
0.9ms
0.9ms
0.9ms
0.9ms
4.2A
4.2A
3A
3A
Buck Output Discharge EN
Enabled
Enabled
Enabled
Enabled
Buck Output Limit EN
Enabled
Enabled
Disabled
Disabled
Buck Parallel Mode Operation
Unparalleled
Switching Frequency
Paralleled
800kHz
VIN UVLO Rising
4.5V
GPIO
PG
Shutdown Delay EN
Enabled
PG Delay Time
Software Initial I2C Slave
Address
MTP Configure Code
0.2ms
MTP Revision Number
0x00
0x68
0x03
Table 10: 0003 Suffix Code Register Value
Suffix Code
Register
Hex Value
0003
0x40
03h
0003
0x41
EBh
0003
0x42
05h
0003
0x43
23h
0003
0x44
EDh
0003
0x45
05h
0003
0x46
13h
0003
0x47
5Fh
0003
0x48
05h
0003
0x49
33h
0003
0x4A
5Fh
0003
0x4B
05h
0003
0x4C
F3h
0003
0x4D
68h
0003
0x4E
42h
0003
0x4F
03h
MPM54304 Rev. 1.0
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11/6/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
45
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
Table 11: 0004 Suffix Code Configuration
Suffix Code: 0004
OTP Items
Output Voltage Set Method
FB Voltage
Initial On/Off
Mode
Buck1
Buck2
Buck3
Buck4
External divider
External divider
External divider
External divider
0.6V
0.6V
0.6V
0.6V
On
On
On
On
FCCM
FCCM
FCCM
FCCM
Soft-Start Delay Time Slot #
Soft-Start Time (VO = 0% to
100%)
Valley Current Limit
0ms
0ms
1ms
1ms
0.9ms
0.9ms
0.9ms
0.9ms
4.2A
4.2A
3A
3A
Buck Output Discharge EN
Enabled
Enabled
Enabled
Enabled
Buck Output Limit EN
Enabled
Enabled
Enabled
Disabled
Buck Parallel Mode Operation
Paralleled
Switching Frequency
Paralleled
800kHz
VIN UVLO Rising
4.5V
GPIO
PG
Shutdown Delay EN
Enabled
PG Delay Time
Software Initial I2C Slave
Address
MTP Configure Code
0.2ms
MTP Revision Number
0x00
0x68
0x04
Table 12: 0004 Suffix Code Register Value
Suffix Code
Register
Hex Value
0004
0x40
03h
0004
0x41
EBh
0004
0x42
05h
0004
0x43
23h
0004
0x44
EDh
0004
0x45
05h
0004
0x46
13h
0004
0x47
5Fh
0004
0x48
05h
0004
0x49
33h
0004
0x4A
5Fh
0004
0x4B
05h
0004
0x4C
F3h
0004
0x4D
68h
0004
0x4E
43h
0004
0x4F
04h
MPM54304 Rev. 1.0
www.MonolithicPower.com
11/6/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
46
MPM54304 – QUAD-OUTPUT POWER MODULE WITH I2C
PACKAGE INFORMATION
LGA-33 (7mmx7mm)
PIN 1 ID
MARKING
PIN 1 ID
0.30X45º TYP
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
3) JEDEC REFERENCE IS MO-303.
4) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MPM54304 Rev. 1.0
MonolithicPower.com
11/6/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
47
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