MPQ18021HS-A-LF-Z

MPQ18021A 100V, 2.5A, High-Frequency Half-Bridge Gate Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MPQ18021A is a high-frequency, 100V, halfbridge, N-channel power MOSFET driver. Its lowside and high-side driver channels are independently controlled and matched with a time delay of less than 5ns. Under-voltage lockout on both high-side and low-side supplies force their outputs low in case of insufficient supply. The integrated bootstrap diode reduces external component count. • • • • • • • • • • Drives N-Channel MOSFET Half Bridge 115V VBST Voltage Range On-Chip Bootstrap Diode Typical 16ns Propagation Delay Time Less Than 5ns Gate Drive Matching Drives 1nf Load with 12ns/9ns Rise/Fall Times with 12V VDD TTL Compatible Input Less Than 150μA Quiescent Current UVLO for Both High-Side and Low-Side In SOIC8 Package APPLICATIONS • • • • Telecom Half-Bridge Power Supplies Avionics DC-DC Converters Two-Switch Forward Converters Active Clamp Forward Converters All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION +12V 100V SECONDARY SIDE CIRCUIT VDD BST/HB INH/HI INL/LI DRIVE HI CONTROL PWM CONTROLLER DRIVE LO DRVH/HO SW/HS DRVL/LO MPQ18021A VSS ISOLATION AND FEEDBACK MPQ18021A Rev. 1.0 www.MonolithicPower.com 12/10/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 MPQ18021A―100V, 2.5A, HIGH-FREQUENCY HALF-BRIDGE GATE DRIVER ORDERING INFORMATION Part Number Package SOIC8 MPQ18021HS-A* Top Marking MP18021A * For Tape & Reel, add suffix –Z (e.g. MPQ18021HS–A–Z); For RoHS compliant packaging, add suffix –LF (e.g. MPQ18021HS–A–LF–Z) PACKAGE REFERENCE TOP VIEW VDD 1 8 DRVL/LO BST/HB 2 7 VSS DRVH/HO 3 6 INL/LI SW/HS 4 5 INH/HI SOIC8 ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply Voltage (VDD).................. -0.3V to +20V SW Voltage (VSW) ...................... -5.0V to +105V BST Voltage (VBST) .................... -0.3V to +120V BST to SW................................... -0.3V to +18V DRVH to SW............. -0.3V to (BST-SW) + 0.3V DRVL to VSS.................. -0.3V to (VDD + 0.3V) All Other Pins...................-0.3V to (VDD + 0.3V) (2) Continuous Power Dissipation (TA =25°C) SOIC8........................................................1.4W Junction Temperature.............................. 150°C Lead Temperature ................................... 260°C Storage Temperature............... -65°C to +150°C SOIC8 .................................... 90 ...... 45... °C/W Recommended Operating Conditions (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. (3) Supply Voltage (VDD)....................... 9.0V to 18V SW Voltage (VSW) ...................... -1.0V to +100V SW slew rate ........................................