MPQ2166
The Future of Analog IC Technology
6V, Dual 2A/2A or 3A/1A,
Low Quiescent Current,
Synchronous Buck with PG and SS
AEC-Q100 Qualified
DESCRIPTION
FEATURES
The MPQ2166 is an internally compensated,
dual, PWM, synchronous, step-down regulator
that operates from a 2.7V to 6V input and
generates an output voltage as low as 0.6V.
The MPQ2166 can be configured as a 2A/2A or
3A/1A output current regulator and is ideal for
powering portable equipment that runs on a
single-cell lithium-ion (Li+) battery due to a low
60µA quiescent current.
The MPQ2166 integrates dual, 55mΩ, high-side
switches and 20mΩ synchronous rectifiers for
high efficiency without an external Schottky
diode. The MPQ2166 has peak-current-mode
control and internal compensation and is
capable of low dropout configurations. Both
channels can operate at 100% duty cycle.
Full protection features include cycle-by-cycle
current limit and thermal shutdown.
The MPQ2166 requires a minimum number of
readily available, standard, external components
and is available in QFN-18 (2mmx3mm) and
QFN-18 (2.5mmx3.5mm) packages.
2.7V to 6V Operating Input Range
2A/2A or 3A/1A Continuous Current
55mΩ/20mΩ RDS(ON)
Programmed Frequency up to 3MHz
External Sync Clock Up to 3MHz
180o Phase Shifted Operation
Power Good (PG) Indicators
External Soft Start (SS) and Track
Adjustable Advanced Asynchronous Mode
(AAM) or Forced Continuous Conduction
Mode (FCCM)
Peak Efficiency >90%
Output Adjustable from 0.6V to 5.5V
100% Duty Cycle Operation
60µA Quiescent Current
Cycle-by-Cycle Over-Current Protection
(OCP)
Short-Circuit Protection (SCP) with Hiccup
Mode and Valley Current Detection
Thermal Shutdown
Available in QFN-18 (2mmx3mm) and QFN18 (2.5mmx3.5mm) Packages
Available in a Wettable Flank Package
Available in AEC-Q100 Grade-1
APPLICATIONS
Automotive Infotainment
Automotive Clusters
Automotive Telematics
Battery-Powered Devices
Portable Instruments
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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© 2020 MPS. All Rights Reserved.
1
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL APPLICATION
Efficiency vs. Load Current
VOUT1 = 1.8V, L1 = 0.68μH, fSW = 2.25MHz,
AAM, one channel on
100
1.50
EFFICIENCY
1.35
80
1.20
70
1.05
60
Vin=2.7V
Vin=3.6V
Vin=5V
50
40
30
0.90
0.75
0.60
0.45
20
POWER LOSS
10
POWER LOSS (W)
EFFICIENCY (%)
90
0.30
0.15
0
10
100
1000
LOAD CURRENT (mA)
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
0.00
3000
2
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
ORDERING INFORMATION
Part Number*
MPQ2166GD
MPQ2166GD-AEC1
MPQ2166GDE-AEC1***
MPQ2166GRH
MPQ2166GRH-AEC1
MPQ2166GRHE-AEC1***
Package
Top Marking
QFN-18 (2mmx3mm)
MSL Rating**
1
See Below
QFN-18 (2.5mmx3.5mm)
1
* For Tape & Reel, add suffix –Z (e.g. MPQ2166GD–Z)
** Moisture Sensitivity Level Rating
*** Wettable flank
TOP MARKING (MPQ2166GD & MPQ2166GD-AEC1)
AQF: Product code of MPQ2166GD and MPQ2166GD-AEC1
Y: Year code
WW: Week code
LLL: Lot number
TOP MARKING (MPQ2166GDE-AEC1)
AXF: Product code of MPQ2166GDE-AEC1
Y: Year code
WW: Week code
LLL: Lot number
MPQ2166 Rev. 1.2
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5/12/2020
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© 2020 MPS. All Rights Reserved.
3
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TOP MARKING (MPQ2166GRH&MPQ2166GRH-AEC1)
AVP: Product code of MPQ2166GRH and MPQ2166GRH-AEC1
Y: Year code
WW: Week code
LLL: Lot number
TOP MARKING (MPQ2166GRHE-AEC1)
BKG: Product code of MPQ2166GRHE-AEC1
Y: Year code
WW: Week code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-18 (2mmx3mm)
QFN-18 (2.5mmx3.5mm)
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ..................................... 6.5V
VSW ........................................ -0.3V to VIN + 0.3V
All other pins ................................ -0.3V to +6.5V
Junction temperature ................................ 150°C
Lead temperature...................................... 260°C
Storage temperature ................... -65°C to 150°C
Continuous power dissipation (TA = +25°C) (2)
QFN-18 (2mmx3mm) ................................ 1.78W
QFN-18 (2.5mmx3.5mm) ............................ 2.5W
ESD Rating
Human-body model (HBM) ....................... ±2kV
Charged-device model (CDM) ................ ±750V
Recommended Operating Conditions
Supply voltage (VIN) ........................... 2.7V to 6V
Output voltage (VOUT) ...................... 0.6V to 5.5V
Operating junction temp........ -40°C to +125°C (3)
Thermal Resistance
θJA
θJC
QFN-18 (2mmx3mm)
JESD51-7 (4) ……………………. 70……15….°C/W
QFN-18 (2.5mmx3.5mm)
JESD51-7 (4) ……………………. 50……12…°C/W
EV2166-RH-00A (5) …………...34.8….2.7…°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) Operating devices at junction temperatures greater than
125°C is possible, please contact MPS for details.
4) Measured on JESD51-7, 4-layer PCB.
5) Measured on MPS standard EVB, 6.35cm*6.35cm, 2oz
cooper thick, 4-Layer PCB.
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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© 2020 MPS. All Rights Reserved.
5
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C.
Parameters
Supply current (quiescent)
Shutdown current
VIN under-voltage lockout
threshold
VIN under-voltage lockout
hysteresis
Regulated FB voltage
FB input current
EN high threshold
EN low threshold
EN input current
HS switch on resistance
LS switch on resistance
SW leakage current
HS switch current limit(6)
LS valley current limit(6)
LS switch current limit
Oscillator frequency accuracy
Symbol
IQ
ISHDN
INUVLO
Condition
VIN = 5V, VEN = 2V,
VFB = 0.65V, no switching
VEN = 0V, CCM=GND,
TJ = +25°C
VEN = 0V, CCM=GND
TJ = -40°C to +85°C(6)
VEN = 0V, CCM=GND
TJ = +85°C to +125°C
Min
Rising edge
IFB
VEN_H
VEN_L
IEN
RDSON_P
RDSON_N
ISW_LK
IHS_LIMIT
IVALLEY
ILS_LIMIT
fSW
Max
Units
60
80
μA
0
0.2
μA
0
1.5
μA
5
μA
2.55
V
2.4
INUVLO_HYS
VFB
Typ
230
TJ = +25°C
TJ = -40°C to +125°C
VFB = 0.65V
0.593
0.588
mV
0.600
0.600
0
0.607
0.612
50
0
0
55
20
0.4
0.1
0.1
90
45
mΩ
mΩ
-1
0
1
μA
3.4
4.5
3.9
5.6
350
1000
3000
402
1150
3300
3
A
A
A
kHz
kHz
kHz
MHz
degree
ns
ns
%
°C
°C
μA
VFB
VFB
μs
μs
V
V
1.6
VEN = 2V
VEN = 0V
VIN = 5V
VIN = 5V
VEN = 0V, VIN = 6V,
VSW = 0V and 6V,
TJ = 25°C
Sourcing
Sinking, CCM
RFREQ = 665k
RFREQ = 200k
RFREQ = 51k
Sync frequency range
fSYNC
Phase shift
Minimum on time(6)
TON_MIN
Minimum off time(6)
TOFF_MIN
Maximum duty cycle
DMAX
Thermal shutdown threshold(6)
TD
Thermal shutdown hysteresis(6)
TD_HYS
Soft-start charging current
ISS
VSS = 0V
Power good rising threshold
PGOODVth-Hi
Power good falling threshold
PGOODVth-Lo
Power good rising delay
TPGOOD_R
Power good falling delay
TPGOOD_F
CCM on threshold
CCM off threshold
1
298
850
2700
0.35
2
0.85
0.77
180
55
50
100
175
40
3.2
0.9
0.82
30
40
5
0.95
0.87
1.6
0.4
V
V
nA
V
V
μA
NOTE:
6) Guaranteed by design and characterization, not test in production.
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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© 2020 MPS. All Rights Reserved.
6
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL CHARACTERISTICS
VIN = 5V, TJ = -40°C to +125°C, unless otherwise noted.
VFB vs. Temperature
602
66
601
64
600
62
VFB (mV)
IQ (μA)
IQ vs. Temperature
68
60
58
599
598
597
56
596
54
595
52
-50
-25
0
25
50
75
100
-50
125
-25
TEMPERATURE (°C)
0
25
50
75
TEMPERATURE (°C)
100
125
VIN UVLO Rising Threshold vs.
Temperature
ILIMIT vs. Temperature
2.410
4.8
4.7
2.405
VIN UVLO (V)
ILIMIT (A)
4.6
4.5
4.4
4.3
4.2
2.400
2.395
2.390
2.385
4.1
2.380
4.0
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
-50
125
0
25
50
75
TEMPERATURE (°C)
100
125
100
125
RLS_ON vs. Temperature
64
30
62
28
60
26
24
58
RLS_ON (mΩ)
RHS_ON (mΩ)
RHS_ON vs. Temperature
-25
56
54
52
50
22
20
18
16
14
48
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
12
-50
-25
0
25
50
75
TEMPERATURE (°C)
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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© 2020 MPS. All Rights Reserved.
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL CHARACTERISTICS (continued)
VIN = 5V, TJ = -40°C to +125°C, unless otherwise noted.
Frequency vs. Temperature
fSW = 350kHz
92
358
90
356
88
FREQUENCY (kHz)
PG THRESHOLD (%VREF)
PG Rising/Falling Threshold vs.
Temperature
PG Rising Threshold
PG Falling Threshold
86
84
82
352
350
348
346
344
342
80
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
-50
125
-25
0
25
50
75
TEMPERATURE (°C)
Frequency vs. Temperature
Frequency vs. Temperature
fSW = 1MHz
fSW = 3MHz
1.03
3.06
1.02
3.04
FREQUENCY (MHz)
FREQUENCY (MHz)
354
1.01
1.00
0.99
0.98
0.97
100
125
100
125
3.02
3.00
2.98
2.96
2.94
2.92
2.90
0.96
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
-50
-25
0
25
50
75
TEMPERATURE (°C)
MPQ2166 Rev. 1.2
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5/12/2020
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
Efficiency vs. Load Current
Efficiency vs. Load Current
80
1.20
80
70
1.05
0.90
Vin=2.7V
Vin=3.6V
Vin=5V
50
40
0.75
0.60
0.25
0.20
30
0.15
0.30
20
10
0.15
10
0
0.00
3000
0
0.10
POWER LOSS
0.05
10
100
LOAD CURRENT (mA)
0.00
1000 2000
Efficiency vs. Load Current
Efficiency vs. Load Current
VOUT1 = 1.8V, L1 = 0.68μH, FCCM, one channel on
VOUT2 = 1.2V, FCCM, one channel on
EFFICIENCY
90
80
70
50
100
1.35
90
1.20
80
0.48
70
0.42
1.05
Vin=2.7V
Vin=3.6V
Vin=5V
60
0.90
0.75
0.60
40
0.45
30
POWER LOSS
0.36
Vin=2.7V
Vin=3.6V
Vin=5V
40
0.30
0.24
0.18
30
10
0.15
10
0
0.00
3000
0
100
1000
LOAD CURRENT (mA)
0.54
50
20
10
EFFICIENCY
60
0.30
20
0.60
1.50
EFFICIENCY (%)
100
POWER LOSS
0.12
0.06
10
100
LOAD CURRENT (mA)
1000
Load Regulation
Load Regulation
VOUT1 = 1.8V, L1 = 0.68μH, AAM, one channel on
VOUT2 = 1.2V, AAM, one channel on
0.6
0.4
0.3
0.2
0.1
0.0
-0.1
0.04
0.02
0.00
-0.02
-0.04
Vin=2.7V
Vin=3.6V
Vin=5V
-0.06
-0.08
-0.2
10
0.00
2000
0.06
Vin=2.7V
Vin=3.6V
Vin=5V
0.5
LOAD REGULATION (%)
EFFICIENCY (%)
0.30
40
20
100
1000
LOAD CURRENT (mA)
0.35
Vin=2.7V
Vin=3.6V
Vin=5V
50
0.45
10
0.40
60
30
POWER LOSS
0.45
70
EFFICIENCY (%)
60
POWER LOSS (W)
EFFICIENCY (%)
90
0.50
EFFICIENCY
POWER LOSS (W)
1.35
90
EFFICIENCY
POWER LOSS (W)
1.50
100
LOAD REGULATION (%)
VOUT2 = 1.2V, AAM, one channel on
100
POWER LOSS (W)
VOUT1 = 1.8V, L1 = 0.68μH, AAM, one channel on
100
1000
LOAD CURRENT (mA)
3000
10
100
1000 2000
LOAD CURRENT (mA)
MPQ2166 Rev. 1.2
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5/12/2020
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
Load Regulation
Load Regulation
VOUT1 = 1.8V, L1 = 0.68μH, FCCM, one channel on
Vin=2.7V
Vin=3.6V
Vin=5V
0.5
0.4
LOAD REGULATION (%)
LOAD REGULATION (%)
0.6
VOUT2 = 1.2V, FCCM, one channel on
0.06
0.3
0.2
0.1
0.0
-0.1
-0.2
10
100
1000
0.04
0.02
0.00
-0.02
-0.04
Vin=2.7V
Vin=3.6V
Vin=5V
-0.06
-0.08
3000
10
Line Regulation
Line Regulation
VOUT1 = 1.8V, L = 0.68μH, AAM, one channel on
VOUT2 = 1.2V, AAM, one channel on
0.06
Io=1mA
Io=1.5A
Io=3A
0.40
0.30
LINE REGULATION (%)
LINE REGULATION (%)
0.50
0.20
0.10
0.00
-0.10
Io=1mA
Io=1A
Io=2A
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.20
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
VIN (V)
Line Regulation
Line Regulation
VOUT1 = 1.8V, L = 0.68μH, FCCM, one channel on
VOUT2 = 1.2V, FCCM, one channel on
0.08
0.50
Io=1mA
Io=1.5A
Io=3A
0.40
0.30
Io=1mA
Io=1A
Io=2A
0.06
LINE REGULATION (%)
LINE REGULATION (%)
1000 2000
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
0.20
0.10
0.00
-0.10
0.04
0.02
0.00
-0.02
-0.04
-0.20
2.5
3.0
3.5
4.0
4.5
VIN (V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
MPQ2166 Rev. 1.2
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5/12/2020
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Case Thermal Rise
Case Thermal Rise
VIN = 5V, IOUT1 = IOUT2 = 0A to 2A, AAM,
both channels on
VIN = 5V, IOUT1 = 0A to 3A, IOUT2 = 1A, AAM,
L1 = 0.68μH, both channels on
20
18
20
18
16
16
14
12
14
TRISE (°C)
TRISE (°C)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
10
8
12
10
8
6
4
6
2
2
4
0
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
IOUT (A)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IOUT1 (A)
MPQ2166 Rev. 1.2
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5/12/2020
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
VOUT2/AC
10mV/div.
IL2
200mA/div.
VSW2
5V/div.
VOUT1/AC
10mV/div.
IL1
200mA/div.
VSW1
5V/div.
VOUT2/AC
2mV/div.
IL2
1A/div.
VSW2
5V/div.
VOUT1/AC
2mV/div.
VOUT2/AC
10mV/div.
VOUT2/AC
10mV/div.
IL2
500mA/div.
IL2
1A/div.
VSW2
5V/div.
VSW2
5V/div.
VOUT1/AC
10mV/div.
IL1
500mA/div.
VOUT1/AC
10mV/div.
IL1
1A/div.
VSW1
5V/div.
VSW1
5V/div.
VIN
5V/div.
VOUT2
1V/div.
IL2
500mA/div.
VSW2
5V/div.
VIN
5V/div.
VOUT2
1V/div.
IL2
500mA/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
500mA/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
500mA/div.
VSW1
5V/div.
VIN
5V/div.
VOUT2
1V/div.
IL2
2A/div.
VSW2
5V/div.
VIN
2V/div.
VIN
5V/div.
IL2
2A/div.
VOUT2
1V/div.
VSW2
5V/div.
VOUT2
1V/div.
IL2
50mA/div.
VSW2
2V/div.
VOUT1
1V/div.
IL1
2A/div.
VSW1
5V/div.
IL1
2A/div.
VOUT1
1V/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
50mA/div.
VSW1
2V/div.
IL1
1A/div.
VSW1
5V/div.
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
VIN
5V/div.
VOUT2
1V/div.
IL2
500mA/div.
VSW2
5V/div.
VIN
5V/div.
VOUT2
1V/div.
IL2
2A/div.
VSW2
5V/div.
VIN
2V/div.
VOUT2
1V/div.
IL2
1A/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
500mA/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
2A/div.
VSW1
5V/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
500mA/div.
VSW2
5V/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
500mA/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
500mA/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
500mA/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
2A/div.
VSW1
5V/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
50mA/div.
VSW2
2V/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
500mA/div.
VOUT1
1V/div.
IL1
50mA/div.
VSW1
2V/div.
VOUT1
1V/div.
IL1
500mA/div.
VSW1
5V/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
1A/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
1A/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
1A/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
2A/div.
VSW2
5V/div.
VSW2
5V/div.
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
VEN
2V/div.
VOUT2
1V/div.
IL2
2A/div.
VSW2
5V/div.
VEN
2V/div.
VOUT2
1V/div.
IL2
1A/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
2A/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
1A/div.
VSW1
5V/div.
VOUT2
1V/div.
VOUT2
1V/div.
IL2
5A/div.
VSW2
5V/div.
IL2
5A/div.
VSW2
5V/div.
IL2
5A/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT2
1V/div.
VOUT2
1V/div.
VOUT2
1V/div.
IL2
5A/div.
VSW2
5V/div.
IL2
5A/div.
VSW2
5V/div.
IL2
5A/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT2
1V/div.
IL2
5A/div.
VSW2
5V/div.
VOUT1
1V/div.
IL1
5A/div.
VSW1
5V/div.
VOUT2
1V/div.
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VOUT1 = 1.8V, VOUT2 = 1.2V, L1 = L2 = 1.5µH, fSW = 2.25MHz, TA = 25°C, unless otherwise
noted.
VOUT1/AC
200mV/div.
VOUT2
1V/div.
VSW2
5V/div.
IL2
5A/div.
VOUT1
1V/div.
VSW1
5V/div.
IL1
5A/div.
VOUT1/AC
100mV/div.
IL1
1A/div.
VSW1
5V/div.
VOUT2/AC
100mV/div.
IL2
1A/div.
VSW2
5V/div.
IL1
2A/div.
VSW1
5V/div.
IL2
2A/div.
VSW2
5V/div.
VOUT1/AC
200mV/div.
IL1
2A/div.
VSW1
5V/div.
VOUT2/AC
200mV/div.
IL2
2A/div.
VSW2
5V/div.
IL1
2A/div.
VSW1
5V/div.
VOUT2/AC
100mV/div.
IL2
2A/div.
VSW2
5V/div.
VOUT1/AC
100mV/div.
IL1
1A/div.
VSW1
5V/div.
VOUT2/AC
100mV/div.
IL2
1A/div.
MPQ2166 Rev. 1.2
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15
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PIN FUNCTIONS
QFN-18
QFN-18
(2mmx3mm) (2.5mmx3.5mm)
Pin #
Pin #
Name Description
Power ground of channel 2. Connect PGND2 with larger copper
PGND2 areas to the negative terminals of the input and output capacitors.
PGND2 must connect to PGND1 externally on board.
Switch node connection to the inductor for channel 2. SW2
SW2 connects to the internal high- and low-side power MOSFET switches
of the channel 2 buck.
1
2
2
3
3
4
VIN2
4
5
SS2
5
6
FB2
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
Input supply for channel 2. Place a decoupling capacitor to ground
close to VIN2 to reduce switching spikes.
Soft start for channel 2. Place a capacitor from SS2 to GND to set
the soft-start time externally. Floating this pin will activate the internal
default 0.5ms soft-start setting.
Feedback for channel 2. FB2 is the input to the error amplifier of
channel 2. An external resistive divider connects FB2 between the
output and ground. The voltage on FB2 compares to the internal
0.6V reference to set the regulation voltage of channel 2.
AGND Analog ground. Connect AGND to PGND externally.
Power supply to the internal regulator for both channels.
Decouple with a 0.1µF to 1µF capacitor between VCC and AGND.
VCC
Connect VIN1, VIN2, VCC together externally, it is not
recommended to power them from separated power supply.
AAM or forced CCM control. Pull CCM high to enter forced CCM
CCM mode; pull CCM low to enter AAM mode at light load. Do not float
CCM.
Feedback for channel 1. FB1 is the input to the error amplifier of
channel 1. An external resistive divider connects FB1 between the
FB1
output and GND. The voltage on FB1 compares to the internal 0.6V
reference to set the regulation voltage of channel 1.
Soft start for channel 1. Place a capacitor from SS1 to GND to set
SS1 the soft-start time externally. Floating this pin will activate the internal
default 0.5ms soft-start setting.
Input supply for channel 1. Place a decoupling capacitor to ground
VIN1
close to VIN1 to reduce switching spikes.
Switch node connection to the inductor for channel 1. SW1
SW1 connects to the internal high- and low-side power MOSFET switches
of the channel 1 buck.
Power ground of channel 1. Connect PGND1 with larger copper
PGND1 areas to the negative terminals of the input and output capacitors.
PGND1 must connect to PGND2 externally on board.
Power good for channel 1. The output of PG1 is an open drain, a
pull-up resistor to power source is needed if used. PG1 is pulled high
PG1
when VFB1 reaches 90% of VREF, it is pulled low to GND if VFB1 drops
to 82% of VREF.
MPQ2166 Rev. 1.2
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16
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PIN FUNCTIONS (continued)
QFN-18
QFN-18
(2mmx3mm) (2.5mmx3.5mm)
Pin #
Pin #
15
16
16
17
17
18
18
1
Name Description
Enable control for channel 1. Pull EN1 below the specified
threshold 0.4V to shut the chip down. Pull EN above the specified
threshold to 1.6V enable the chip. Do not float EN1.
Frequency set. Connect a resistor to GND to set the switching
FREQ frequency. The switching frequency can be synchronized by an
external clock via FREQ.
Enable control for channel 2. Pull EN2 below the specified
EN2 threshold 0.4V to shut the chip down. Pull EN above the specified
threshold to 1.6V enable the chip. Do not float EN2.
Power good for channel 2. The output of PG2 is an open drain, a
pull-up resistor to power source is needed if used. PG2 is pulled high
PG2
when VFB2 reaches 90% of VREF, it is pulled low to GND if VFB2 drops
to 82% of VREF.
EN1
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
BLOCK DIAGRAM
VCC
VIN1
UVLO
UVLO and
Bandgap
0.6V
Main
Switch
PCH
Internal SS
SS1
FB1
Control
Logic
COMP1
0.6V
PWM
608kΩ 30pF
SW1
Hi-Z
0.5pF
ISLOPE1
EN1
FREQ
PH1
Slope
Comp
Synchronous
Rectifier
NCH
OSC1
Low-Side
Gate Driver
Oscillator
PLL
PGND1
PH2
EN2
CCM
VIN2
CCM/AAM
Control
Slope
Comp
OSC2
Main
Switch
PCH
ISLOPE2
Internal SS
SS2
FB2
COMP2
0.6V
608kΩ 30pF
Control
Logic
PWM
SW2
Hi-Z
0.5pF
PG1
PG2
Synchronous
Rectifier
NCH
Power
Good
Low-Side
Gate Driver
AGND
PGND2
Figure 1: Functional Block Diagram
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
OPERATION
The MPQ2166 is a fully integrated, dualchannel, synchronous, step-down converter.
Both channels use peak-current-mode control
with internal compensation for fast transient
response and cycle-to-cycle current limit.
The MPQ2166 is optimized for low-voltage,
portable applications where efficiency and small
size are critical.
180° Out-of-Phase Operation
The MPQ2166 operates the two channels in
180° out-of-phase operation to reduce input
current ripple, so a smaller input bypass
capacitor can be used. When both channels
operate in CCM, two internal clocks are used
(see Figure 2). The high-side MOSFET is
turned on at the clock rising edge of the
corresponding channel.
The shutdown current in forced CCM mode
(50μA at 3.3V) is much higher than AAM mode
due to some internal circuits are active. It is
recommended to pull CCM pin LOW when part
is shutdown if the high shutdown current is
cared.
The
MPQ2166
works
in
advanced
asynchronous mode (AAM) when CCM is
pulled lower than 0.4V. AAM is used to optimize
efficiency during light-load and no-load
conditions.
When AAM mode is enabled, the MPQ2166
first enters non-synchronous operation as the
inductor current approaches zero at light load. If
the load decreases further or is at no load,
which makes the internal COMP voltage (VCOMP)
decrease to the set value, then the MPQ2166
enters AAM. In AAM, the internal clock is reset
whenever VCOMP crosses over the set value,
and the crossover time is taken as the
benchmark of the next clock. When the load
increases and VCOMP is higher than the set
value, the operation mode is in DCM or CCM,
which has a constant switching frequency.
Figure 2: 180° Out-of-Phase Operation
At low dropout, when the switching frequency is
stretched out for each channel, the MPQ2166
runs at a fixed-off time with its own independent
switching frequency. After the input voltage
rises high again, frequency stretch mode ends,
and PWM mode resumes and synchronizes
with the master oscillator for out-of-phase
operation.
Light-Load Operation
In light-load condition, the MPQ2166 can work
in two different operating modes by setting
CCM to different statuses.
The MPQ2166 works in forced continuous
conduction mode (CCM) when the CCM pin is
pulled higher than 1.6V. The MPQ2166 works
with fixed frequency from no load to full load in
this mode. The advantage of CCM is the
controllable frequency and lower output ripple
at light load.
Figure 3: AAM Mode and Forced CCM Mode
Enable
EN is a digital control pin that turns the
regulator on and off.
When EN is pulled below falling threshold
voltage 0.4V, the chip is shutdown. Forcing this
pin above EN rising threshold voltage 1.6V
turns on the part. Do not float EN.
Soft Start (SS)
The MPQ2166 has a built-in soft start that
ramps up the output voltage at a controlled slew
rate, preventing an overshoot at start-up. The
soft-start time is about 0.5ms, typically.
The soft-start time can also be programmed by
an external capacitor connected to SS, shown
in Equation (1):
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
t SS ms
C SS nF VRFF V
ISS μA
(1)
Where CSS is the external SS capacitor, VREF is
the internal reference voltage (0.6V), and ISS is
the 3.2µA SS charge current.
Oscillator and SYNC Function
The internal oscillator frequency is set by a single
external resistor (RFREQ) connected between
FREQ and ground. The frequency setting resistor
should be located close to the device. The
relationship between the oscillator frequency and
RFREQ is shown in Figure 4.
Power Good (PG)
The MPQ2166 has one power good (PG)
output to indicate normal operation after the
soft-start time. PG is the open drain of an
internal MOSFET. It should be connected to
VIN, VCC, or an external voltage source
through a resistor (i.e.: 100kΩ). After the input
voltage is applied, the MOSFET is turned on
and PG is pulled to GND before SS is ready.
After the FB voltage reaches 90% of the
reference voltage (VREF), the MOSFET turns off
and PG is pulled high by an external voltage
source. When the FB voltage drops to 82% of
VREF, the PG voltage is pulled to GND to
indicate a failure output.
Current Limit and Short Circuit
Each channel of the MPQ2166 has a typical
4.5A current limit for the high-side switch. When
FB drops to 60% of the reference value and SS
is OK, the MPQ2166 treats this as a short and
attempts to recover with hiccup mode.
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
10
100
1000
Figure 4: FSW vs. RFREQ
FREQ can also be used to synchronize the
internal oscillator to an external clock. The
rising edge of the channel 1 clock is
synchronized to the external clock rising edge,
while the channel 2 clock remains at 180° outof-phase to channel 1. The recommended
external SYNC frequency is in the range of
350kHz to 3MHz. While there is no pulse width
requirement, note that there is always parasitic
capacitance of the pad there, so if the pulse
width is too short, a clear rising and falling edge
may not be seen. The pulse is recommended to
be longer than 100ns.
Ensure to add the external SYNC clock
(350kHz to 3MHz) before the device starts up
and keep the SYNC clock until the device is off.
Constant high, constant low and high/low
transition for the SYNC signal are all not
allowed during the operation.
In hiccup mode, the MPQ2166 disables the
output power stage, slowly discharges the softstart cap, and soft starts automatically. If the
short-circuit condition still remains, the
MPQ2166 repeats this operation cycle until the
short circuit is removed and the output rises
back to regulation levels.
Dropout Operation
The MPQ2166 allows the high-side switch to
remain on for more than one switching cycle and
increases the duty cycle while the input voltage
drops down to the output voltage. When the duty
cycle reaches 100%, the high-side switch is on to
deliver current to the output up to its current limit.
The output voltage is then the difference between
the input voltage and the voltage drop across the
main switch and the inductor.
Thermal Shutdown
The MPQ2166 has thermal protection by
monitoring the IC temperature internally. This
function prevents the chip from operating at an
exceedingly high temperature. If the junction
temperature exceeds the threshold value
(typically 175°C), it shuts down the whole chip.
This is a non-latch protection. There is a 40°C
hysteresis. Once the junction temperature
drops to about 135°C, the device resumes
operation by initiating a soft start.
MPQ2166 Rev. 1.2
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20
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider sets the output
voltage. The feedback resistor (R1) also sets
the feedback loop bandwidth with the internal
compensation. The
T-type
network
is
recommended. (see Figure 5).
fESR
RT+R1 is used to set the loop bandwidth. The
lower RT+R1 is, the higher the bandwidth.
However, a high bandwidth may cause an
insufficient phase margin, resulting in loop
instability. Therefore, a proper RT value is
required to make a trade off between the
bandwidth and phase margin. Table 1 lists the
recommended feedback resistor and RT values
for output voltages.
R1 is estimated to be 100kΩ. R2 can then be
calculated with Equation (2):
R2
R1
VOUT
1
0.6V
(2)
Table 1: Resistor Selection vs. Output Voltage
Setting
RT
R1
R2
VOUT
1.2V
1.5V
1.8V
2.5V
3.3V
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
66.5kΩ
49.9kΩ
31.6kΩ
22.1kΩ
In the case of ceramic capacitors used as
output capacitors (CO), the feedback loop
bandwidth (fC) is no higher than 1/10 of the
switching frequency for optimal transient
performance and good phase margin. If an
electrolytic capacitor is used, the loop
bandwidth is no higher than 1/4 of the ESR zero
frequency (fESR). fESR can be calculated by
Equation (3):
2 RESR CO
(3)
For example, choose fC = 80kHz with a ceramic
capacitor and CO = 22μF.
Inductor Selection
An inductor with a DC current rating at least
25% higher than the maximum load current is
recommended for most applications. For best
efficiency, the inductor DC resistance should be
less than 20mΩ. For most designs, the
inductance value can be derived from Equation
(4):
L
Figure 5: T-type Feedback Network
1
VOUT (VIN - VOUT )
VIN IL fSW
(4)
Where ∆IL is inductor ripple current. Choose the
inductor ripple current to be approximately 30%
of the maximum load current.
The maximum inductor peak current can be
calculated with Equation (5):
IL(MAX) ILOAD
IL
2
(5)
Input Capacitor Selection
The input capacitor reduces the surge current
drawn from the input and the switching noise
from the device. The input capacitor impedance
at the switching frequency should be less than
the input source impedance to prevent highfrequency switching current from passing to the
input source. Ceramic capacitors with X5R or
X7R dielectrics are highly recommended
because of their low ESR and small
temperature coefficients. For most applications,
a 22µF capacitor is sufficient.
Output Capacitor Selection
The output capacitor (CO) keeps the output
voltage ripple small and ensures a stable
regulation
loop.
The
output
capacitor
impedance should be low at the switching
frequency. Use ceramic capacitors with X5R or
X7R dielectrics. If an electrolytic capacitor is
used, pay close attention to the output ripple
voltage, extra heating, and the selection of the
upper feedback resistor due to the large ESR of
electrolytic capacitor (refer to the Setting the
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
Output Voltage section). The output ripple
(∆VOUT) can be approximated with Equation (6):
VOUT
VOUT (VIN - VOUT )
1
(ESR
) (6)
8 fSW Co
VIN L fSW
Power Dissipation
IC power dissipation is important in circuit
design, not only because of efficiency concerns,
but also because of the chip’s thermal
requirements. Several parameters influence
power dissipation, such as conduction loss
(Cond), dead time (DT), switching loss (SW),
MOSFET driver current (DR), and supply
current (S).
Based on these parameters, we can estimate
the power loss with Equation (7):
PLOSS PCond PDT PSW PDR PS
(7)
Thermal Regulation
Changes in IC temperatures change the
electrical characteristics, especially when the
temperature exceeds the IC’s recommended
operating
range.
Managing
the
IC’s
temperature requires additional considerations
to ensure that the IC runs within the maximum
allowable temperature junction. Specific layout
designs can improve the thermal profile while
limiting costs to either the efficiency or
operating range.
For the MPQ2166, connect the ground pin on
the package to a ground plane on top of the
PCB to use this plane as a heat sink. Connect
this ground plane to the ground planes beneath
the IC using vias to improve heat dissipation.
However, given that these ground planes can
introduce unwanted EMI noise and occupy
valuable PCB space, design their size and
shape to match the thermal resistance
requirement.
Connecting the ground pin to a heat sink cannot
guarantee that the IC will not exceed its
recommended temperature limits (i.e.: the
ambient temperature exceeds the IC’s
temperature limits). If the ambient air
temperature approaches the IC’s temperature
limit, the IC can be de-rated to operate using
less power and help prevent thermal damage
and unwanted electrical characteristics.
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PCB Layout Guidelines(7)
Efficient PCB layout is critical for stable
operation. A four-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure 6
and follow the guidelines below.
1. Place the high-current paths (PGND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
2. Place input capacitors on both VIN sides
and as close to VIN and PGND as possible.
3. Place the decoupling capacitor as close to
VCC and AGND as possible.
4. Keep the switching node SW short and
away from the feedback network.
5. Place the external feedback resistors next
to FB. Do not place vias on the FB trace.
6. Connect PGND to a large copper area to
achieve better thermal performance.
Inner Layer 1
Inner Layer 2
Top Layer
Bottom Layer
Figure 6: Recommended PCB Layout
NOTE:
7) The recommended PCB layout is based on Figure 7.
MPQ2166 Rev. 1.2
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5/12/2020
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23
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
TYPICAL APPLICATION CIRCUITS
EN2
VIN1
EN2
R4
100kΩ
0603
EN1
R2
100kΩ
0603
PG2
PG1
PG1
L1
L2
R10
SW1
SW2
FB2
FB1
SS2
SS1
R11
75kΩ
0603
AGND
C4
1.5nF
0603
50V
CCM
100kΩ
PGND1
1.5µH
R8
C2C C2D 100kΩ
22µF 22µF 0603
0805 0805 R9
16V 16V
100kΩ
0603
FREQ
CHB
1.2V/2A
R1
100kΩ
0603
EN1
MPQ2166
PG2
VOUT2
VIN2
R3
100kΩ
0603
C5
C1D
0.1µF 0.1µF
0805 0603
16V
C1A C1B C1C
22µF 0.1µF 22µF
0805 0805 0805
16V
16V 16V
VCC
2.7V-6V
PGND2
VIN
CHA
1.5µH
R7
100kΩ
VOUT1
1.8V/2A
R5
100kΩ
C2A C2B
0603 22µF 22µF
0805 0805
R6
16V 16V
49.9kΩ
0603
C3
1.5nF
0603
50V
VCC JP1
CCMAAM
AGND
Figure 7: 2A/2A Application Circuit
Figure 8: 3A/1A Application Circuit
MPQ2166 Rev. 1.2
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5/12/2020
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24
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PACKAGE INFORMATION
QFN-18 (2mmx3mm)
Non-Wettable Flank
MPQ2166 Rev. 1.2
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MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PACKAGE INFORMATION (continued)
QFN-18 (2mmx3mm)
Wettable Flank
PIN 1 ID
MARKING
PIN 1 ID
0.15X0.10 TYP
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
SECTION A-A
0.15X0.10
NOTE:
1) THE LEAD SIDE IS WETTABLE.
2) ALL DIMENSIONS ARE IN MILLIMETERS.
3) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MPQ2166 Rev. 1.2
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5/12/2020
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26
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PACKAGE INFORMATION (continued)
QFN-18 (2.5mmx3.5mm)
Non-Wettable Flank
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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27
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
PACKAGE INFORMATION (continued)
QFN-18 (2.5mmx3.5mm)
Wettable Flank
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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28
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
CARRIER INFORMATION
Part Number
MPQ2166GD-Z
MPQ2166GD-AEC1-Z
MPQ2166GDE-AEC1-Z
MPQ2166GRH-Z
MPQ2166GRH-AEC1-Z
MPQ2166GRHE-AEC1-Z
Package
Description
Quantity
/Reel
Quantity/
Tube*
Reel
Diameter
Carrier Tape
Width
Carrier Tape
Pitch
5000
N/A
13in.
12mm
8mm
QFN-18
(2mmx3mm)
QFN-18
(2.5mmx3.5mm)
* N/A indicates “not available” in tubes. For 500 piece tape & reel prototype quantities, see factory. (Order code for 500 piece partial reel is “-P”,
tape & reel dimensions same as full reel.)
MPQ2166 Rev. 1.2
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5/12/2020
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29
MPQ2166 – 6V, DUAL 2A/2A OR 3A/1A, SYNC, BUCK REGULATOR WITH PG AND SS
Revision History
Revision #
1.2
Revision
Date
Description
4/30/2020
Add three auto relative application:
Automotive Infotainment
Automotive Clusters
Automotive Telematics
Add MSL rating, ESD and Carrier information.
Add the thermal resister data on EVB result.
Update the efficiency, load and line regulation based on the
new version of MPQ2166.
Add the comments:
Ensure to add the external SYNC clock (350kHz to 3MHz)
before the device starts up and keep the SYNC clock until
the device is off. Constant high, constant low and high/low
transition for the SYNC signal are all not allowed during the
operation.
Add the specific descriptions for the pin functions.
Add the compensation parameters and modify VCC
connection in the functional block.
Add the “Enable” description in OPERATION part
Add the “Thermal shutdown” description in OPERATION
part
Pages
Updated
P1
P3,P5,P29
P5
P9, P10
P20
P16,P17
P18
P19
P20
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MPQ2166 Rev. 1.2
www.MonolithicPower.com
5/12/2020
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© 2020 MPS. All Rights Reserved.
30
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