MPQ2420-AEC1
75V, 0.3A, Synchronous
Step-Down Converter with Watchdog
AEC-Q100 Qualified
DESCRIPTION
FEATURES
The MPQ2420 is a step-down switching
regulator with integrated high- and low-side,
high-voltage power MOSFETs. It provides a
highly efficient output of up to 0.3A. The
integrated watchdog adds additional security
redundancy to the system.
The wide 4.5V to 75V input range accommodates
a variety of step-down applications in an
automotive environment. A 5μA shutdown
mode quiescent current in a full temperature
range is ideal for battery-powered applications.
It allows for high-power conversion efficiency
over a wide load range by scaling down the
switching frequency under a light-load condition
to reduce switching and gate driver losses. The
start-up switching frequency and short circuit
can also be scaled down to prevent inductor
current runaway.
Full protection features include under-voltage
lockout (UVLO) and thermal shutdown. Thermal
shutdown provides reliable, fault-tolerant
operation.
The MPQ2420 is available in a TSSOP-16 EP
package.
20μA Quiescent Current for Buck Only
Wide 4.5V to 75V Operating Input Range
(80V ABS MAX)
1.2Ω/0.45Ω Internal Power MOSFETs
Programmable Soft Start
FB Tolerance: 1% at Room Temperature,
2% at Full Temperature
Adjustable Output Voltage
Integrated Window Watchdog
Power-On Reset during Power-Up
Under-Voltage Lockout and Thermal
Shutdown
Programmable Short Window Mode or Long
Window Mode
Low Shutdown Mode Current of 5μA
TSSOP-16 EP Package
Available in AEC-Q100 Grade 1
APPLICATIONS
Automotive Systems
Industrial Power Systems
Distributed Power Systems
Battery-Powered Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
VIN
EN
EN
BST
VOUT
SW
BIAS
VCC
VCC
MPQ2420
FB
VREF
MODE
MCU
WDI
POK
WDO
/DIS_WD
TIMER
SS
GND
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
1
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ORDERING INFORMATION
Part Number*
MPQ2420GF
MPQ2420GF-AEC1
Package
Top Marking
TSSOP-16 EP
See Below
* For Tape & Reel, add suffix –Z (e.g. MPQ2420GF–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP2420: Part code of MPQ2420GF
LLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
WDO
1
WDI
2
MODE
3
GND
4
IN
EN
5
6
VREF
7
FB
8
WAKE
TIMER
WDI
NC
MODE
VCC
GND
WDO
GND
IN
EN
FB
SW
BST
16
/WD_DIS
15
TIMER
14
VCC
13
SW
12
BST
11
BIAS
10
POK
9
SS
BIAS
SS
TSSOP-16 EP
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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2
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply voltage (VIN) ………… ...... -0.3V to +80V
Switch voltage (VSW) …… …….-0.3V to VIN + 1V
BST to SW……………………. ……-0.3 to +6.0V
All other pins……………… ... ……-0.3V to +6.0V
EN sink current……………… ............……150µA
(2)
Continuous power dissipation (TA = +25°C)
TSSOP-16 EP…………………………....….2.7W
Junction temperature………… ... …………150C
Lead temperature ………… ...... …………260C
Storage temperature………… .. -65°C to +150C
TSSOP-16 EP ……..…………..45…….10…C/W
Recommended Operating Conditions
(3)
Supply voltage (VIN)………… .......... 4.5V to 75V
Output voltage (VOUT)………………1V to 0.9VIN
Operating junction temp. (TJ) ..... -40C to 125C
(4)
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
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MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ELECTRICAL CHARACTERISTICS
VIN = 24V, VEN = 2V, VCC = 5V, TJ = -40C to +125C, unless otherwise noted.
Parameter
Condition
Min
Typ
Max
Units
20
30
µA
2.2
4.2
3.75
0.45
1.0
5
4.4
3.95
μA
V
1.01
1.02
V
V
V
2
1
1.2
50
1.035
1.5
2.5
0.625
0.9
nA
V
Ω
Ω
Ω
Ω
1
µA
810
mA
1.85
1.248
ns
V
V
DC/DC Converter
Supply quiescent current
No load, VFB = 1.2V
Shutdown supply current
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN UVLO hysteresis
VEN < 0.3V
Feedback voltage
Feedback current
VREF voltage
Upper switch-on resistance
Lower switch-on resistance
Lower switch leakage
3.9
3.45
VIN = 4.5V to 75V, TJ = 25°C
VIN = 4.5V to 75V
0.99
0.98
VFB = 1.2V
VIN = 4.5V to 75V, IREF = 100µA
VBST - VSW = 5V, TJ = 25°C
VBST - VSW = 5V
VBIAS = 5V, TJ = 25°C
VBIAS = 5V
-50
0.965
0.9
0.7
0.275
0.2
VEN = 0V, VSW = 75V
Peak current limit
Minimum switch-on time
Enable rising threshold
Enable falling threshold
Thermal shutdown
630
720
1.25
1.152
120
1.55
1.2
(5)
Enable threshold hysteresis
Enable current
Soft-start current
POK upper trip threshold
POK lower trip threshold
POK threshold hysteresis
POK deglitch timer
POK output voltage low
FB OVP rising threshold
FB OVP hysteresis
0.45
VEN = 2.4V
FB respect to the nominal value
FB respect to the nominal value
FB respect to the nominal value
4
86
81
0.35
0.8
5.5
90
85
5
7
94
89
40
ISINK = 1mA
(5)
Thermal shutdown
(5)
hysteresis
1.05
50
0.4
1.1
V
µA
µA
%
%
%
μs
V
V
mV
175
C
20
C
NOTE:
5) Derived from bench characterization. Not tested in production.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
4
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, VEN = 2V, VCC = 5V, TJ = -40C to +125C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
0.3
16
25
19
32
V
µA
µA
Watchdog Power Supply
Timer voltage
Quiescent current
Power-on reset
threshold
IQ
RTIMER = 51k
RTIMER = 100k
RTIMER = 51k
VPOR-HIGH WDO goes high with rising VCC
4.4
4.6
4.8
V
VPOR-LOW WDO goes low with falling VCC
4.3
4.5
4.7
V
-10%
880
10
+10%
µs
cycle
Watchdog Timing
Single period
T
(6)
Power-on delay
t0
Sync signal monitoring
t1
(6)
time
Watchdog window close
t2
(6)
time (short mode)
Watchdog window open
t3
(6)
time (short mode)
Watchdog window close
t4
(6)
time (long mode)
Watchdog window open
t5
(6)
time (long mode)
WDO reset pulse
t6
(6)
width
WDI_OK pulse width
Watchdog Input and Output
RTIMER = 51k
RTIMER = 51k
RTIMER = 51k
450
cycle
RTIMER = 51k, mode = low
15
cycle
RTIMER = 51k, mode = low
10
cycle
RTIMER = 51k, mode = high
1500
cycle
RTIMER = 51k, mode = high
1000
cycle
4
cycle
RTIMER = 51k
10
WDI logic high
WDI logic low
3.2
MODE logic high
3.2
WDO low
V
V
0.8
V
0.1
1
μA
MODE = 0V
5
8
μA
3.2
V
/WD_DIS logic low
WDO high
0.8
MODE = 5V
/WD_DIS logic high
/WD_DIS input current
μs
V
MODE logic low
MODE input current
5000
0.8
V
WD_DIS = 5V
0.1
1
μA
WD_DIS = 0V
5
8
μA
VCC = 5V, IWDO = 1mA
VCC-0.2
V
VCC = 5V, IWDO = 1mA
0.2
V
VCC = 1V, IWDO = 300μA
0.1
V
NOTE:
6) Guaranteed by design.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
5
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL CHARACTERISTICS
DC/DC Converter
VIN = 12V, unless otherwise noted.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
6
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL CHARACTERISTICS (continued)
Watchdog
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL PERFORMANCE CHARACTERISTICS
DC/DC Converter
VIN = 12V, VOUT = 3.3V, L = 33µH, COUT = 2x22µF, TA = 25C, unless otherwise noted.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 33µH, COUT = 2x22µF, TA = 25C, unless otherwise noted.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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9
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
PIN FUNCTIONS
Pin #
Watchdog
Name
Description
1
2
WDO
WDI
3
MODE
4
GND
14
15
VCC
TIMER
16
/WD_DIS
Watchdog output. WDO outputs the reset signal to MCU.
Watchdog input. WDI receives the trigger signal from MCU.
Mode switching. Pull MODE high to make the watchdog work in a long window
mode. Pull MODE low to make the watchdog work in a short window mode. MODE
has a weak internal pull-up.
Ground. Connect GND as close as possible to the output capacitor to avoid highcurrent switch paths.
Power input.
Watchdog timer. Set the time out with an external resistor
Watchdog disable. Pull /WD_DIS low to disable the watchdog. Pull /WD_DIS high
to enable the watchdog. /WD_DIS has a weak internal pull-up.
DC/DC
4
GND
5
IN
6
EN
7
VREF
8
FB
9
SS
10
POK
11
BIAS
12
BST
13
SW
Ground. Same as GND in Watchdog.
Input supply. IN requires a decoupling capacitor connected to ground to reduce
switching spikes.
Enable input. Pull EN below the low threshold to shut the chip down. Pull EN
above the high threshold to enable the chip. Float EN to disable the chip.
Reference voltage output.
Feedback input to the error amplifier (QFN-10 3mmx3mm package only).
Connect FB to the tap of an external resistive divider between the output and GND.
FB sets the regulation voltage when compared to the internal 1V reference.
Soft-start control input. Connect a capacitor from SS to GND to set the soft-start
period.
Open-drain power-good output. A high output indicates that VOUT is higher than
90% of the reference. POK is pulled down during shutdown.
Controller bias input. BIAS supplies current to the internal circuit when
VBIAS > 2.9V and provides a feedback input for the SOIC8E package, which has a
fixed output only.
Bootstrap. BST provides a positive power supply for the internal floating high-side
MOSFET driver. Connect a bypass capacitor between BST and SW.
Switch node.
Exposed Pad Connect exposed pad to GND plane for optimal thermal performance.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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10
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
FUNCTIONAL BLOCK DIAGRAM
VIN
BIAS
BST
Regulator
REF
VREF
EN
+
ILIMIT
POK
SW
POK
+
+
SS
FB
S
RS
R
COMP
SS
-
ICOMP
EN Control
3M
ZCD
FB
VCC
Power On
Reset
Oscillator,
State Machine
/WD_DIS MODE WDI
WDGND
WDO
TIMER
GND
Figure 1: Functional Block Diagram
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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11
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
DC/DC OPERATION
The MPQ2420 is a 75V, 0.3A, synchronous,
step-down, switching regulator with integrated
high-side and low-side, high-voltage power
MOSFETs (HS-FET and LS-FET, respectively). It
provides a highly efficient 0.3A output and
features a wide input voltage range, external softstart control, and precision current limit. It has a
very low operational quiescent current, making it
suitable for battery-powered applications.
Control Scheme
The ILIM comparator, FB comparator, and zero
current detector (ZCD) block control of the PWM
(see Figure 2). If VFB is below the 1V reference
and the inductor current drops to zero, the HSFET turns on, and the ILIM comparator begins
sensing the HS-FET current. When the HS-FET
current reaches its limit, the HS-FET turns off,
and the LS-FET and the ZCD block turn on. The
ILIM comparator turns off to reduce the quiescent
current. The LS-FET and the ZCD block turn off
after the inductor current drops to zero. If VFB is
below the 1V reference, the HS-FET turns on
and begins another cycle. If VFB remains higher
than the 1V reference, the HS-FET remains off
until VFB drops below 1V.
VFB
VREF
VSW
IL
Ipeak
Io
Io increase
regulation. Lower values of VIN result in lower
output voltages. When VBIAS > 2.9V, the BIAS
supply overrides the input voltage and supplies
power to the internal regulator. When VBIAS >
4.5V, BIAS powers the LS-FET driver. Using
BIAS to power the internal regulators improves
efficiency. It is recommended to connect BIAS to
the regulated output voltage when it is in the 2.9V
to 5.5V range. When the output voltage is out of
this range, BIAS can be powered using an
external supply of >2.9V to >4.5V.
Enable Control (EN)
The MPQ2420 has a dedicated enable control
(EN). When VIN goes high, EN enables and
disables the chip (high logic). Its falling threshold
is a consistent 1.2V, and its rising threshold is
about 350mV. When floating, EN is pulled down
internally to GND to disable the chip.
When EN = 0V, the chip enters the lowest
shutdown current mode. When EN is higher than
zero, but lower than its rising threshold, the chip
remains in shutdown mode with a slightly larger
shutdown current.
A Zener diode is connected internally from EN to
GND. The typical clamping voltage of the Zener
diode is 6.5V. VIN can be connected to EN
through a high ohm (Ω) resistor if the system
does not have another logic input acting as an
EN signal. The resistor must be designed to limit
the EN sink current to less than 150μA. Since
there is an internal 3M resistor from EN to GND,
the external pull-up resistor should be smaller
than
[VIN (MIN) - 1.55V] 3M
1.55V
to ensure that EN can
turn on at the lowest operational VIN.
Figure 2: Control Scheme
Internal Regulator and BIAS
The 2.6V internal regulator powers most of the
internal circuitry. This regulator takes VIN and
operates in the full VIN range. When VIN is greater
than 3.0V, the output of the regulator is in full
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
12
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating below the operational supply
voltage range. The UVLO rising threshold is
about 4.2V while its falling threshold is about
3.75V.
Soft Start (SS)
The MPQ2420 employs a soft-start (SS)
mechanism to prevent the converter output
voltage from overshooting during start-up. When
the chip starts, the internal circuitry generates a
constant current to charge an external soft-start
capacitor. The SS voltage ramps up slowly from
0V at a slow pace set by the SS time. When VSS
is less than VREF, VSS overrides VREF, and the FB
comparator uses VSS as the reference instead of
VREF. When VSS is higher than VREF, VREF
resumes control.
VSS can be much smaller than VFB, but it can only
barely exceed VFB. If VFB drops, VSS tracks VFB.
This function prevents an output voltage
overshoot during short-circuit recovery. When the
short circuit is removed, a new SS process
ramps up.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed its upper threshold, the entire chip shuts
down. When the temperature falls below its lower
threshold, the chip is enabled again.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating HS-FET driver. This floating driver has
its own UVLO protection. This UVLO’s rising
threshold is about 2.4V with a hysteresis of about
300mV. During the UVLO, the SS voltage resets
to zero. When the UVLO is disabled, the
regulator follows the soft-start process.
The dedicated internal bootstrap regulator
charges and regulates the bootstrap capacitor to
about 5V. When the voltage difference between
BST and SW falls below its working parameters,
a PMOS pass transistor connected from VIN to
BST turns on to charge the bootstrap capacitor.
The current path runs from VIN to BST to SW.
The external circuit must have enough voltage
headroom to accommodate charging.
If VIN is sufficiently higher than SW, the bootstrap
capacitor charges. When the HS-FET is on, VIN is
about equal to SW, and the bootstrap capacitor
cannot charge. The optimal charging period
occurs when the LS-FET is on and VIN - VSW is at
its largest. VSW is equal to VOUT when there is no
current in the inductor. The difference between
VIN and VOUT charges the bootstrap capacitor.
If the internal circuit does not have sufficient
voltage and time to charge the bootstrap
capacitor, extra external circuitry can be used to
ensure that the bootstrap voltage operates in its
normal region.
Start-Up and Shutdown
If both VIN and VEN are higher than their
appropriate thresholds, the chip starts up. The
reference block starts first, generating stable
reference voltages and currents, and then the
internal regulator is enabled. The regulator
provides a stable supply for the remaining
circuitries.
If the internal supply rail is high, an internal timer
keeps the power MOSFET off for about 50µs to
clear any start-up glitches. When the soft-start
block is enabled, the SS output is held low and
ramps up slowly.
Three events can shut down the chip: VEN low,
VIN low, and thermal shutdown. During the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. The
internal supply rail is then pulled down. The
floating driver is not subject to this shutdown
command, but its charging path is disabled.
Power OK (POK)
POK is an open-drain power good output. A high
output indicates that VOUT is higher than 90% of
its nominal value. POK is pulled down in
shutdown mode.
Reference Voltage Output (VREF)
VREF has an output reference voltage of 1V. It has
up to 500µA of source current capability.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
13
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
WATCHDOG OPERATION
Supply Voltage
A supply voltage of VCC = 5V +/-10% is
recommended for normal operation. WDO is
pulled low when VCC rises to 1V or higher.
When VCC rises to 4.65V, WDO remains at a
low level for t0 to reset the MCU.
Timer
Calculate Period T (µs) with Equation (1):
T s 15.75 RTIMER k 73.5
(1)
Calculate RTIMER (k) with Equation (2):
RTIMER k 0.063 T s 4.67
(2)
For example, if RTIMER=51kΩ, then T0.88ms.
Monitor MCU Synchronization Signal
When the watchdog is in a sync signal
monitoring state, the watchdog IC receives a
WDI_OK signal from the MCU within t1, the
timer resets and the watchdog enters normal
operation (WDI remains low for 10µs to 5ms). If
the watchdog does not receive the WDI_OK
signal from the MCU during t1, it generates a
reset signal and enters the sync signal
monitoring state again.
Short Window Mode
When the MCU and watchdog are synchronized
correctly and MODE is low, the watchdog
operates in short window mode if WDI_OK is
received in a window close state (t2). The
watchdog then outputs a reset signal and
enters the sync signal monitoring state.
Long Window Mode
When the MCU and watchdog are synchronized
correctly and MODE is high, the watchdog
works in a long window mode if WDI_OK is
received in a window close state (t4). The
watchdog then outputs a reset signal and
enters the sync signal monitoring state.
If WDI_OK is received in a window open state
(t5), the watchdog enters a window close state.
The MCU is in normal operation in this
situation.
If WDI_OK is not received in t4+t5, the watchdog
then outputs a reset signal and enters the sync
signal monitoring state.
MODE is pulled low during a long window
mode, and the watchdog then enters a short
window mode.
Watchdog Disable
Pull /WD_DIS low to disable the watchdog. Pull
/WD_DIS high to enable the watchdog. It has a
weak internal pull-up so leaving /WD_DIS open
enables the watchdog.
WDI Error
The WDI signal remaining at a low level for
longer than the max WDI_OK pulse width is
regarded as an error. When this error occurs,
WDO is pulled down until WDI rises to a high
level again.
If WDI_OK is received in a window open state
(t3), the watchdog enters a window close state.
The MCU is in normal operation in this
situation.
If WDI_OK is not received in t2+t3, the watchdog
outputs a reset signal and enters the sync
signal monitoring state.
MODE is pulled high during the short window
mode, and the watchdog enters a long window
mode.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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14
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TIMING DIAGRAM
Power-On Reset and No-Sync Signal
VCC=1V VCC=90%
VCC
t6
t0
Floating
WDO
t1
t1
1
WDI
0
MODE
0
Synchronized by WDI and Triggered in Open Window (MODE=0, Short Window Mode)
VCC
t0
WDO
t2
t3
t1
t2
WDI_OK
WDI_OK
1
WDI
0
MODE
0
Synchronized by WDI and No-Trigger Signal (MODE=0, Short Window Mode)
VCC
t6
t0
WDO
t2
t1
t3
t1
WDI_OK
WDI
MODE
1
0
0
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
15
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Synchronized by WDI and Triggered in Closed Window (MODE=0, Short Window Mode)
VCC
t6
t0
WDO
t2
t1
WDI_OK
1
WDI
t1
WDI_OK
0
MODE
0
NOTE: When the WDI_OK rising edge approaches WDO when it is low, the t6 timer resets. In the above situation, the WDO
reset signal keeps a t6+WDI_OK time.
Synchronized by WDI and Triggered in Open Window (MODE=1, Long Window Mode)
VCC
t0
WDO
t4
t5
t1
t4
WDI_OK
WDI_OK
1
WDI
0
1
MODE
0
Synchronized by WDI and No-Trigger Signal (MODE=1, Long Window Mode)
VCC
t6
t0
WDO
t1
t4
t5
t1
WDI_OK
WDI
MODE
1
0
1
0
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
16
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Synchronized by WDI and Triggered in Closed Window (MODE=1, Long Window Mode)
VCC
t6
t0
WDO
t1
WDI_OK
WDI
MODE
1
t4
t1
WDI_OK
0
1
0
NOTE: When the WDI_OK rising edge approaches WDO when it is low, the t6 timer resets. In the above situation, the WDO
reset signal keeps a t6+WDI_OK time.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
17
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
STATE DIAGRAM
WDO reset state
time-out t0
Sync signal
monitoring state
WDI_OK &
MODE=1
WDI_OK &
MODE=0
MODE=1
Short window
close state
MODE=0
MODE=0
Long window
close state
MODE=1
WDI_OK
time-out t2
time-out t6
WDI=0
time-out t1
WDI_OK
time-out t4
Short window
open state
Long window
open state
WDI=0
time-out t5
time-out t3
WDO reset pulse
state
NOTE: The above state diagram does not show a WDI error situation.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
18
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
APPLICATION INFORMATION
Selecting the Inductor
The Ipeak is fixed, and the inductor value can be
determined with Equation (3):
L
VOUT VIN - VOUT
VIN Ipeak fs
VIN (MAX ) t ON(MIN)
Ipeak
(4)
Where VIN(MAX) is the maximum value of the input
voltage, and tON(MIN) is the 115ns minimum switch
on time.
Switching Frequency
The switching frequency can be estimated with
Equation (5):
2 Io VOUT VIN - VOUT
(5)
fs
2
Ipeak
VIN L
A larger inductor can produce a lower fS. fS
increases as Io increases. When Io increases to
its maximum value Ipeak/2, fS also reaches its
highest value. The maximum fS value can be
estimated with Equation (6):
fs(max)
V VIN - VOUT
OUT
Ipeak VIN L
(6)
Setting the Output Voltage
The output voltage is set using a resistive voltage
divider from the output voltage to FB. To achieve
the desired output voltage, select a resistor
divider using Equation (7):
R1 VOUT
-1
R2 VREF
IIN_FB
(3)
Where fS is the switching frequency at the
maximum output current.
A larger inductor value results in a lower
switching frequency and higher efficiency.
However, the larger value inductor has a larger
physical size, a higher series resistance, a lower
saturation current, and/or a slow load transient
dynamic performance. The inductor value has a
lower limit, which is determined by the minimum
on time. To keep the inductor functioning
properly, choose an inductor value that is higher
than LMIN, which is derived from Equation (4):
L MIN
The current flowing into the resistor divider
increases the supply current, especially at noload and light-load conditions. The VIN supply
current caused by the feedback resistors can be
calculated with Equation (8):
VOUT
V
1
OUT
R1 R2 VIN η
(8)
Where ƞ is the efficiency of the regulator.
To reduce this current, resistors in the MΩ range
are recommended. The recommended value of
the feedback resistors are shown in Table 1.
Table 1: Resistor Selection for Common Output
Voltages
VOUT (V)
R1 (kΩ)
R2 (kΩ)
3.3
5
1200
1200
523
300
Under-Voltage Lockout Point Setting
The MPQ2420 has an internal fixed undervoltage lockout (UVLO) threshold. The rising
threshold is about 4.2V while the falling threshold
is about 3.75V. An external resistor divider
between EN and VIN can be used to obtain a
higher equivalent UVLO threshold (see Figure 3).
VIN
IN
R4
EN
R5
3M
Figure 3: Adjustable UVLO Using EN
The UVLO threshold can be calculated with
Equation (9) and Equation (10):
UVLO TH_Rising (1
R4
) ENTH_Rising
3M//R5
UVLO TH_Falling (1
R4
) ENTH_Falling (10)
3M//R5
(9)
(7)
Where VREF is the FB reference voltage 1V.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
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© 2016 MPS. All Rights Reserved.
19
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Soft-Start Capacitor
The soft-start time is the duration of an internal
5μA current source charging the SS capacitor
from 0 to the FB reference voltage (1V). The SS
capacitor value can be determined with Equation
(11):
(11)
CSS 5 t SS (μF)
Feed-Forward Capacitor
The HS-FET turns on when FB drops below the
reference voltage, producing good load transient
performance. However, this also causes the HSFET to be sensitive to the FB voltage during turnon. The HS-FET is easily affected by FB noise at
turn-on, which can trigger a Fsw jitter. Fsw jitter
occurs most often when the Vo ripple is very
small. To improve jitter performance, it is
recommended to use a small feed-forward
capacitor of about 39pF between Vo and FB.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
20
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL APPLICATION CIRCUITS
GND
4.5V-75V
5
R4
1M
C1B
10uF
100V
12
C3
0.1uF
BST
VIN
U1
VIN
SW
L1
33uH
VOUT
C1A
0.1uF
100V
C2B
47uF
10V
C2A
0.1uF
10V
GND
MPQ2420
6
EN
EN
BIAS
R3 10
11
R5
NS
VCC
3.3V/300mA
13
C4
0.1uF
14
VCC
FB
R1 1.2M
8
R2
510K
C5
39pF
MODE
3
MODE
VREF
7
C6
1uF
WDI
2
WDI
POK
16
/WD_DIS
GND
/WD_DIS
10
POK
WDO
TIMER
1
4
15
WDO
R7
100K
SS
9
C7
10nF
R8
51K
Figure 4: 3.3V Output Typical Application Circuit
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
21
MPQ2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
PACKAGE INFORMATION
TSSOP-16 EP
PIN 1 ID
TOP VIEW
RECOMMENDED LAND PATTERN
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
DETAIL "A"
NOTE:
BOTTOM VIEW
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
3) PACKAGE WITDH DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER
FORMING) SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-153,
VARIATION ABT.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MPQ2420 Rev. 1.0
www.MonolithicPower.com
5/24/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
22
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