MPQ3428A
19A, 600kHz, 20V Wide Input Range, Synchronous
Boost Converter with Input Disconnect Function,
AEC-Q100 Qualified
DESCRIPTION
FEATURES
The MPQ3428A is an Automotive AECQ
application device with 600kHz, fixed-frequency,
high-efficiency, wide input range, current mode
boost converter, optional input disconnect and
an input average current limit function. The
input disconnect feature provides additional
protection by isolating the input from the output
during output short or shutdown.
With a programmable input average current
limit, the MPQ3428A supports a wide range of
applications, including eCall, Smart latch,
Telematics and infotainment. The MPQ3428A
features a 18mΩ, 24V power switch and a
synchronous gate driver for high efficiency. An
external compensation pin allows flexibility in
setting loop dynamics and obtaining optimal
transient performance under all conditions.
Guaranteed Industrial/Automotive Temp
3V to 20V Wide Input Range
Integrated 18mΩ Low-Side Power FET
SDR Driver for Synchronous Solution
19A Internal Switch Current Limit or
External Programmable Input Current
Limit
Input Disconnect and Output SCP
External Soft Start and Compensation for
Higher Flexibility
Programmable UVLO and Hysteresis
5.5V) for automatic start-up. EN can also program VIN UVLO. Do not leave
EN floating.
Driver for the input disconnect MOSFET. If connected to the gate of the input MOSFET
CLDR or floating, an external current-sense resistor is needed. Connect CLDR to GND to use
the internal current-sense circuit. Do not pull CLDR down to GND through a resistor.
Voltage sense. Voltage sensed between SENSE and IN determines the external currentSENSE
sense signal. Connect SENSE to IN if the internal current-sense solution is selected.
Power switch output. SW is the drain of the internal power MOSFET. Connect the power
SW
inductor and output rectifier to SW.
PGND
IN
12
VDD
13
COMP
14
FB
15
SS
16
AGND
Power ground.
Input supply. IN must be bypassed locally.
Internal bias supply. Decouple with a 2.2μF ceramic capacitor as close to VDD as
possible.
Compensation. Connect a capacitor and resistor in series to analog ground for loop
stability.
Feedback input. The reference voltage is 1.225V. Connect a resistor divider from VOUT to
FB.
Soft-start control. Connect a soft-start capacitor to SS. The soft-start capacitor is charged
with a constant current. Leave SS disconnected if soft start is not used.
Analog ground.
ABSOLUTE MAXIMUM RATINGS (1)
SW.......................-0.3V to +24V (28V for 0.7V
Boost switching
VCLDR < VIN + 1.6V
VCLDR ≥ VIN + 1.6V (8)
VOUT > VIN
Work Mode
The boost input average current limit works:
The COMP voltage is regulated to keep the input average
current at VCL / RSENSE.
Runs into hiccup protection without delay.
The linear charge current limit does not work. VCLDR remains
high.
Boost switching
The boost input average current limit works.
The COMP voltage is regulated to keep the input average
current at VCL / RSENSE, no hiccup.
Note:
8) After start-up, the VCLDR ≥ VIN + 1.6V condition is registered if VCLDR exceeds VIN + 1.6V one time. This means the MPQ3428A treats the
condition as VCLDR ≥ VIN + 1.6V even if VCLDR falls below VIN + 1.6V again in protection mode (unless it is turned off by the hiccup protection
or by the power recycle).
Enable (EN) and Programmable UVLO
EN enables and disables the MPQ3428A.
When a voltage greater than VEN_H (1V) is
applied, the MPQ3428A starts up some of the
internal circuits (micro-power mode). If the EN
voltage continues to increase above VEN_ON
(1.33V), the MPQ3428A enables all functions
and begins boost operation. Boost operation is
disabled if the EN voltage is below VEN_ON
(1.33V). To shut down the MPQ3428A
completely, a voltage less than VEN_L (0.36V) is
required on EN. After shutdown, the
MPQ3428A sinks a current less than 1µA from
the input power.
The maximum recommended voltage on EN is
5.5V. If the EN control signal comes from a
voltage greater than 5.5V, a resistor should be
added between EN and the control source. An
internal Zener diode on EN clamps the EN
voltage to prevent runaway. Ensure the Zener
clamped current flowing into EN is less than
0.3mA. EN can be used to program VIN’s UVLO.
See the UVLO Hysteresis section on page 16
for details.
Output Over-Voltage Protection
Except for controlling the COMP signal to
regulate the output voltage, the MPQ3428A
also provides over-voltage protection. If the FB
voltage exceeds 108% of the reference voltage,
boost switching stops. When the FB voltage
drops below 104% of the reference voltage, the
device resumes switching automatically.
Thermal Shutdown
The device has an internal temperature monitor.
If the die temperature exceeds 150°C, the
converter shuts down. Once the temperature
drops below 125°C, the converter turns on
again.
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
APPLICATION INFORMATION
Components referred to below apply to the
typical application circuit (Figure 6) on page 20.
Selecting the Current Limit Resistor
The MPQ3428A features an average current limit
when the external sensing resistor is used. The
resistor (RSENSE) connected between IN and
SENSE sets the current limit (ICL). Calculate ICL
with Equation (1):
ICL VCL /RSENSE
(1)
Where VCL is typically 54mV, ICL is in A, and
RSENSE is in mΩ.
Considering the parasitic inductance on the
sense resistor, a small-sized resistor (e.g. 0805)
is recommended. Add several parallel resistors if
the power rating is lower than recommended. To
reduce the effect of parasitic resistance and
noise, a sense resistor with resistance greater
than 4mΩ is recommended.
UVLO Hysteresis
The MPQ3428A features a programmable UVLO
hysteresis. When powering up, EN sinks a 4.5μA
current from the upper resistor, RTOP (see Figure
2).
Selecting the Soft-Start Capacitor
The MPQ3428A includes a soft-start circuit that
limits the voltage on COMP during start-up to
prevent excessive input current. This prevents
premature termination of the source voltage at
start-up due to input current overshoot. When
power is applied to the MPQ3428A and EN is
asserted, a 7μA internal current source charges
the external capacitor at SS.
The SS voltage clamps the COMP voltage (and
the inductor peak current) until the output is close
to regulation or until COMP reaches 2V. For most
applications, a 10nF SS capacitor is sufficient. If
the output capacitance is large or the front power
supply cannot withstand the huge inrush current,
SS capacitors can be increased accordingly.
Setting the Output Voltage
The output voltage is fed back through two sense
resistors in series. The feedback reference
voltage is typically 1.225V. The output voltage is
determined with Equation (4):
VOUT VREF (1
R1
)
R2
(4)
Where R1 is the top feedback resistor, R2 is the
bottom feedback resistor, and VREF is the
reference voltage (typically 1.225V).
Choose the feedback resistors to be about 10kΩ
(or higher) for good efficiency.
Figure 2: VIN UVLO Program
VIN must increase in voltage to overcome the
current sink. Calculate the VIN start-up threshold
with Equation (2):
VINON VENON (1
RTOP
) 4.5A RTOP
RBOT
(2)
Where VEN-ON is the EN voltage turn-on threshold
(typically 1.33V).
Once the EN voltage reaches VEN-ON, the 4.5µA
sink current turns off to create a reverse
hysteresis for the VIN falling threshold. Calculate
VIN-UVLO-HYS with Equation (3):
VINUVLOHYS 4.5A RTOP
Selecting the Input Capacitor
An input capacitor is required to supply the AC
ripple current to the inductor while limiting noise
at the input source. A low-ESR capacitor is
required to minimize noise. Ceramic capacitors
are recommended, but tantalum or low-ESR
electrolytic capacitors will suffice.
At least two 22µF capacitors are recommended
for loop stability in high-power applications. The
capacitor can be electrolytic, tantalum, or
ceramic. Since the capacitor absorbs the input
switching current, it requires an adequate ripple
current rating. Use a capacitor with an RMS
current rating greater than the inductor ripple
current. See the Selecting the Inductor section on
page 17 to determine the inductor ripple current.
(3)
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
To ensure stable operation, place the input
capacitor as close to the IC as possible.
Alternately, a smaller, high-quality 0.1μF ceramic
capacitor may be placed closer to the IC and the
larger capacitor placed farther away. If using this
technique, a larger electrolytic or tantalum
capacitor is recommended. All ceramic
capacitors should be placed close to the
MPQ3428A input.
Selecting the Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Low-ESR capacitors are
preferred to minimize the output voltage ripple.
The characteristics of the output capacitor affect
the stability of the regulation control system.
Ceramic, tantalum, or low-ESR electrolytic
capacitors are recommended. If using ceramic
capacitors, the capacitance dominates the
impedance at the switching frequency, so the
output voltage ripple is independent of the ESR.
Estimate the output voltage ripple with Equation
(5):
VIN
) ILOAD
VOUT
COUT fSW
Selecting the Inductor
The inductor is required to force the higher output
voltage while being driven by the input voltage. A
higher-value inductor has less ripple current,
resulting in lower peak inductor current. This
reduces stress on the internal N-channel switch
and enhances efficiency. However, the highervalue inductor also has a larger physical size,
higher series resistance, and lower saturation
current.
A good rule of thumb is to allow the peak-to-peak
ripple current to be approximately 30% to 40% of
the maximum input current. Ensure that the peak
inductor current is below 75% of the current limit
at the operating duty cycle to prevent loss of
regulation due to the current limit. In addition, be
sure that the inductor does not saturate under the
worst-case load transient and start-up conditions.
Calculate the required inductance value with
Equation (7) and Equation (8):
L
VIN (VOUT VIN )
VOUT fSW I
(1
VRIPPLE
(5)
Where VRIPPLE is the output ripple voltage, VIN and
VOUT are the DC input and output voltages
respectively, ILOAD is the load current, fSW is the
600kHz fixed switching frequency, and COUT is
the capacitance of the output capacitor.
If using tantalum or low-ESR electrolytic
capacitors, the ESR dominates the impedance at
the switching frequency. Estimate the output
ripple using Equation (6):
VIN
) ILOAD
RESR VOUT
VOUT
I
LOAD
COUT fSW
VIN
(1
VRIPPLE
(6)
Where RESR is the equivalent series resistance of
the output capacitors.
Choose an output capacitor to satisfy the output
ripple and load transient requirements of the
design. Capacitance derating should be taken
into consideration when designing high output
voltage applications. Three 22μF ceramic
capacitors are suitable for most applications.
IIN(MAX)
VOUT ILOAD(MAX)
VIN
(7)
(8)
Where ILOAD(MAX) is the maximum load current, ∆I
is the peak-to-peak inductor ripple current, ∆I =
(30% to 40%) x IIN (MAX), and ŋ is the efficiency.
Selecting the Output Rectifier
The MPQ3428A features an SDR gate driver.
Instead of a Schottky diode, an N-channel
MOSFET can be used to freewheel the inductor
current when the internal MOSFET is off. The
SDR gate driver voltage has a high 5V voltage,
so choose an N-channel MOSFET compatible
with a 5V gate voltage rating. The minimum high
level is about 3V. Therefore, the MOSFET’s turnon threshold is recommended to be below 2.5V.
In some low-output applications, such as a 5V
output, the voltage across the BST capacitor may
be insufficient. In this case, a Schottky diode
should be connected from the output port to BST,
conducting the current into the BST capacitor
when SW goes low (see Figure 3).
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
VOUT = 5V
COUT
MPQ3428A
Figure 3: BST Charger for Low-Output Application
The MOSFET voltage rating should be equal to
or greater than the output voltage. The average
current rating must exceed the maximum load
current, and the peak current rating must exceed
the peak inductor current. If a Schottky diode is
used as the output rectifier, the same
specifications should be considered.
Selecting the Input MOSFET
The MPQ3428A integrates one CLDR pin to
drive an external N-channel MOSFET to
disconnect the input power or limit the input
current. The following key factors should be
considered
when
selecting
the
input
disconnecting MOSFET:
1. Drain-to-source voltage rating: This value
should be greater than VIN + VTH of the input
MOSFET.
2. Drain-to-source current rating: The maximum
current through the input disconnecting
MOSFET is the maximum input current. This
occurs when the input voltage is at a minimum
and the load power is at a maximum.
3. SOA: The MOSFET should survive when
conducting a current pulse that has a high
level of VCL (mV) / RSENSE (mΩ) and lasts for
CSS (nF) x 0.7 (V) / 7 (µA) + 0.5ms.
4. Gate-to-source voltage rating: The positive
gate-to-source voltage rating should be
greater than 5.5V, while the negative voltage
rating should be greater than the value of the
output voltage. If the output voltage is too high
and the MOSFET gate-to-source rating cannot
meet the requirement, a diode from the source
to the gate of the disconnecting MOSFET is
recommended (see Figure 4).
7. Low leakage current: The leakage current
should be low for better isolation.
In addition, size and thermal temperature should
be taken into consideration.
VIN
L1
Q1
R4
D1
BST
SDR
5. Gate-to-source
threshold
voltage:
The
threshold should be below 1.5V. A 1V to 1.2V
overall temperature range is preferred.
6. On resistance (RDS_ON): The on resistance
should be small for high conversion efficiency.
BST
1N5819
SW
CBST
SW
L
CLDR
SENSE
IN
U1
MPQ3428A
Figure 4: Gate Protection Diode for High Output
Voltage Condition
Compensation
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are fP1 (set by the output capacitor,
COUT, and the load resistance), and fP2 (start from
origin). The zero fZ1 is set by the compensation
capacitor (CCOMP) and the compensation resistor
(RCOMP). Calculate fP2 and fZ1 with Equation (9)
and Equation (10):
fP1
fZ1
1
(Hz)
2 RLOAD COUT
1
2 RCOMP CCOMP
(Hz)
(9)
(10)
Where RLOAD is the load resistance.
Calculate the DC loop gain using Equation (11):
A VDC
A VEA VIN RLOAD VFB GCS x R COMP
(V / V)
2
2 VOUT
(11)
Where GCS is the compensation voltage to the
inductor current gain, AVEA is the error amplifier
voltage gain, and VFB is the feedback regulation
threshold.
There is a right-half-plane zero (fRHPZ) that exists
in continuous conduction mode (the inductor
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
current does not drop to zero in each cycle). The
frequency of the right-half-plane zero is
determined with Equation (12):
VIN
VOUT
IOUT
3.3V to 10V
12V
0A to 2A (9)
Note:
9) The maximum load capability may be limited by the permitted
temperature rising.
10. Place enough GND vias close to the
MPQ3428A for good thermal dissipation.
11. Do not place vias on the SW net.
12. Place wide copper pours and vias associated
with the input MOSFET’s drain pin for thermal
dissipation.
Route on bottom
layer
C6
2
1
L1
1
2
U1
1
8
2
7
3
BST
EN
SDR
OUT
MODE
SENSE
SW
SW
SW
PGND
PGND
PGND
SS
1
R2
2
2
C2
2
1
1
1
8
7
6
5
R4
AGND
IN
2
FB
1
VDD
C1
COMP
1
2
2
5
PGND
PGND
Q1
6
Q2
4
SW
SW
3
PCB Layout Guidelines
High-frequency switching regulators require very
careful layout for stable operation and low noise.
All components should be placed as close to the
IC as possible, and a 4-layer PCB is
recommended for high-power applications. For
best results, refer to Figure 5 and follow the
guidelines below:
9. Make the BST and SDR path as short as
possible.
4
The maximum output current is determined by
the permitted temperature rising, current limit,
and input voltage. The detailed application
schematic is shown in Figure 6. The typical
performance and circuit waveforms are shown in
the Typical Performance Characteristics section
on page 8. For more device applications, refer to
the related evaluation board datasheets.
8. Keep the input loop (C1, R4, Q1, L1, SW, and
PGND) as small as possible.
1
Table 2: Design Example
7. Do not connect to the PGND net before
connecting to the IC and AGND.
C5
R1
Design Example
Below is a design example following the
application guidelines for the specifications:
6. Connect the VDD capacitor to AGND with a
short loop.
2
Compensation recommendations are listed in the
Typical Application Circuits section on page 20.
5. Connect the compensation components and
SS capacitor to AGND with a short loop.
C3
The right-half-plane zero increases the gain and
reduces the phase simultaneously, which results
in a smaller phase and gain margin. The worstcase condition occurs when the input voltage is
at its minimum and the output power is at its
maximum.
4. Connect FB and OUT feedback from the
output capacitor (C2).
1
(12)
R3
RLOAD
V
( IN )2 (Hz)
2 L VOUT
2
fRHPZ
0805 package is recommended for the
sensing resistor (R4) to reduce parasitic
inductance.
2
VIN
C4
GND
1
VOUT
Figure 5: Recommended PCB Layout
1. Keep the output loop (SW, PGND, Q2, and
C2) as small as possible.
2. Place the FB divider R1 and R2 as close as
possible to FB.
3. Route the sensing traces (SENSE and IN) in
parallel closely with a small closed area. A
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
TYPICAL APPLICATION CIRCUITS
VIN = 3V to 10V
R4 4X18m
Q1
R7
0Ω
C6
0.1µF
L1 1.5µH
FDMC7678
C1B
C1C
22µF
22µF
SW
C1A
BST
SiR802
22µF
CLDR
GND
GND
GND
OUT
U1
MPQ3428A
VDD
GND
C2C
22µF
PGND
C4
10nF
AGND
C5
SS
GND
GND
R1
300kΩ
FB
EN
R2
34kΩ
COMP
6.8nF
R3
27kΩ
GND
GND
C2B
22µF
GND
2.2µF
R6
NS
C2A
22µF
IN
C3
EN
SDR
SENSE
R5
100kΩ
VOUT = 12V
Q2
GND
GND
GND
GND
Figure 6: 12V Output Synchronous Solution with Input Disconnect Function
VIN = 3V to 10V
L1
C1A
C1B
C1C
22µF
22µF
22µF
1.5µH
C6
0.1µF
CLDR
SENSE
IN
C3
EN
R7
0Ω
Q2
SDR
U1
MPQ3428A
OUT
C2A
C2B
C2C
22µF
22µF
22µF
R1
300kΩ
VDD
R5
100kΩ
VOUT = 12V
FDMC7678
2.2µF
EN
SS
R6
NS
C4
33nF
FB
R2
34kΩ
C5
COMP
6.8nF
R3
21kΩ
Figure 7: 12V Output Synchronous Solution Using an Internal Current-Sensing Circuit
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
R7
0
C6
0.1µF
L1 1.5µH
VIN = 3V to 10V
R4 4x18mΩ
D1
VOUT = 12V
Q1
C1C
22µF
22µF
22µF
SiR802DP
BST
C1B
SW
C1A
CLDR
SDR
SENSE
IN
C3
EN
OUT
U1
MPQ3428A
C2B
C2C
22µF
22µF
22µF
R1
300kΩ
VDD
R5
100kΩ
C2A
2.2µF
FB
EN
C4
10nF
AGND
R6
NS
R2
34kΩ
C5
PGND
SS
COMP
6.8nF
R3
27kΩ
Figure 8: 12V Output Non-Synchronous Solution with Input Disconnect Function
Figure 9: 5V Output Synchronous Solution Using Internal Current-Sensing Circuit
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
PACKAGE INFORMATION
QFN-22 (3mmx4mm)
PIN 1 ID
MARKING
PIN 1 ID
0.125 X 45° TYP
PIN 1 ID INDEX
AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.125 X 45°
NOTE:
RECOMMENDED LAND PATTERN
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MPQ3428A – 19A, 600kHz, 20V, SYNC BOOST CONVERTER W/ INPUT DISCONNECT, AEC-Q100
CARRIER INFORMATION
Part Number
Package
Description
Quantity/Reel
Quantity/Tube
Reel
Diameter
Carrier
Tape Width
Carrier
Tape Pitch
MPQ3428AGL–
Z
QFN 3x4
5000
N/A
13 in.
12mm
8mm
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
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