MPQ4312
45V, 2A, Low IQ, Synchronous Step-Down
Converter with Frequency Spread Spectrum,
AEC-Q100 Qualified
DESCRIPTION
FEATURES
The MPQ4312 is a configurable-frequency,
synchronous step-down switching converter with
integrated internal high-side and low-side power
MOSFETs (HS-FET and LS-FET, respectively).
It provides up to 2A of highly efficient output
current (IOUT) with current mode control for fast
loop response.
•
The wide 3.3V to 45V input voltage (VIN) range
accommodates a variety of step-down
applications in automotive input environments. A
1.7μA shutdown mode quiescent current allows
the device to be used in battery-powered
applications.
•
High power conversion efficiency across a wide
load range is achieved by scaling down the
switching frequency (fSW) under light-load
conditions to reduce the switching and gate
driver losses. An open-drain power good (PG)
signal indicates whether the output is within 95%
to 105% of its nominal voltage.
Frequency foldback helps prevent inductor
current runaway during start-up. Thermal
shutdown provides reliable, fault-tolerant
operation. High-duty cycle and low-dropout
mode are provided for automotive cold-crank
conditions.
The MPQ4312 is available in a QFN-20
(4mmx4mm) package.
MPQ4312 FAMILY VERSIONS
Part
Number
MPQ4312
MPQ4313
MPQ4314
MPQ4315
MPQ4316
MPQ4317
Output
Current
2A
3A
4A
5A
6A
7A
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
Package Options
•
QFN-20 (4mmx4mm)
WF (1)
Wide 3.3V to 45V Operating Input Voltage
(VIN) Range
2A Continuous Output Current (IOUT)
1.7μA Low Shutdown Supply Current (ISHDN)
18μA Sleep Mode Quiescent Current
Internal 48mΩ High-Side and 20mΩ LowSide MOSFETs
350kHz to 1000kHz Configurable Switching
Frequency (fSW) for Car Battery Applications
Synchronizable with External Clock
Out-of-Phase Synchronized Clock Output
Frequency Spread Spectrum (FSS) for Low
EMI
Symmetric VIN for Low EMI
Power Good (PG) Output
External Soft Start (SS)
100ns Minimum On Time
Selectable Advanced Asynchronous Mode
(AAM) or Forced Continuous Conduction
Mode (FCCM)
Low-Dropout Mode
Hiccup Over-Current Protection (OCP)
Available in a QFN-20 (4mmx4mm)
Package
Available in a Wettable Flank Package
Available in AEC-Q100 Grade 1
Automotive Infotainment
Automotive Clusters
Advanced Driver Assistance Systems
(ADAS)
Industrial Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
Note:
1)
WF means wettable flank.
MPQ4312 Rev. 1.0
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1
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL APPLICATION
VIN =
3.3 to 45V
Efficiency vs. Load Current
BST
VOUT
VOUT = 5V, fSW = 470kHz, L = 5.6μH (DCR =
14.5mΩ), AAM
EN
VIN
MODE
SYNCO
SW
FREQ
FB
PG
VCC
NC
SYNCIN
SS
GND
EFFICIENCY (%)
MPQ4312
100
90
80
70
60
50
40
30
20
10
0
Vin=12V
Vin=24V
Vin=36V
Vin=45V
0.1
1
10
100
1000 2000
LOAD CURRENT (mA)
MPQ4312 Rev. 1.0
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2
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
ORDERING INFORMATION
Part Number*
Package
Top Marking
MSL Rating**
MPQ4312GRE-AEC1***
QFN-20 (4mmx4mm)
See Below
1
* For Tape & Reel, add suffix -Z (e.g. MPQ4312GRE-AEC1-Z).
** Moisture Sensitivity Level Rating
*** Wettable Flank
TOP MARKING (MPQ4312GRE-AEC1)
MPS: MPS prefix
Y: Year code
WW: Week code
MP4312: Part number
LLLLLL: Lot number
E: Wettable flank
PACKAGE REFERENCE
TOP VIEW
20
SS
FB
19
18
NC
17
16
15
MODE
SYNCIN
14
2
13
VIN
3
12
VIN
PGND
4
11
PGND
PGND
5
10
6
7
8
9
BST
SW
SW
EN
QFN-20 (4mmx4mm)
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
PIN FUNCTIONS
Pin #
Name
Description
1
MODE
AAM or FCCM selection pin. Pull this pin high to make the MPQ4312 operate in forced
continuous conduction mode (FCCM). Pull it low to make it operate in advanced
asynchronous modulation (AAM) mode under light-load conditions. Do not float this pin.
2
SYNC input. Apply a 350kHz to 1000kHz clock signal to this pin to synchronize the
internal oscillator frequency to the external clock. This pin is also used for multi-phase
operation. This pin is internally high impedance. Do not float this pin under any
SYNCIN circumstances. If used, ensure that the external sync clock has adequate pull-up and pulldown capability. It is recommended to place a ≤51kΩ resistor between the pin and GND
in case the external sync clock’s pull-down capability is not strong enough or the pin
enters a high-impedance (Hi-Z) state.
Input supply. VIN supplies power to all of the internal control circuitry, as well as the
power MOSFET, which is connected to SW. To minimize switching spikes, it is
recommended to connect a decoupling capacitor from VIN to ground, as close to VIN as
possible.
3, 12
VIN
4, 5, 10, 11
PGND
6
BST
Bootstrap. BST is the positive power supply for the high-side MOSFET (HS-FET) driver
connected to SW. Connect a bypass capacitor between this BST and SW. See the
Application Information section on page 32 to calculate the size for this capacitor.
7, 8
SW
Switch node. SW is the output of the internal power MOSFET.
9
EN
Enable. Pull this pin below the specified threshold (0.85V) to shut down the chip. Pull it
above the specified threshold (1V) to enable the chip.
13
SYNCO
SYNC output. The SYNCO pin outputs a clock signal that is 180° out of phase with the
internal oscillator signal. It can also output a signal that is opposite to the clock signal
applied at the SYNCIN pin. Float this pin if it is not used.
14
PG
Power good indicator. PG is an open-drain output. Use a pull-up resistor when
connecting PG to a power source. If the output voltage (VOUT) is within 95% to 105% of
the nominal voltage, PG goes high. If VOUT is above 106.5% or below 93% of the nominal
voltage, then PG goes low.
15
NC
Not connected. Float this pin.
16
VCC
17
AGND
Power ground.
Bias supply. This pin supplies power to the internal control circuitry and gate drivers. A
decoupling capacitor connected to ground must be placed close to this pin. See the
Selecting the VCC Capacitor section on page 33 to calculate the size for this capacitor.
Analog ground.
FB
Feedback input. Connect FB to the midpoint of the external resistor feedback divider,
between the output and AGND. This sets the output voltage. The feedback threshold
voltage is 0.815V. Place the resistor divider as close to FB as possible. Avoid placing vias
on the FB traces.
19
SS
Soft-start input. Place a capacitor from SS to GND to set the soft-start time (tSS). The
MPQ4312 sources 13µA from the SS pin to the soft-start capacitor (CSS) during start-up.
As the SS voltage (VSS) rises, the feedback threshold voltage increases to limit inrush
current during start-up.
20
FREQ
Switching frequency selection. Connect a resistor from this pin to ground to set the
switching frequency (fSW). To set the frequency, see the fSW vs. RFREQ curves on page 15.
18
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (2)
Thermal Resistance
VIN, EN ....................................... -0.3V to +50V
SW ................................. -0.3V to VIN (MAX) +0.3V
BST ...................................................VSW +5.5V
All other pins ............................... -0.3V to +5.5V
Continuous power dissipation (TA= 25°C) (3) (5)
QFN-20 (4mmx4mm) .................................5.4W
Operating junction temperature................ 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +150°C
QFN-20 (4mmx4mm)
JESD51-7 (4).............................44.........9....°C/W
EVQ4312-R-00A (5)................. 23.......2.5...°C/W
Electrostatic Discharge (ESD) Rating
Human body model (HBM)........................ ±2kV
Charged device model (CDM) ................ ±750V
Recommended Operating Conditions
Supply voltage (VIN) ........................ 3.3V to 45V
Output voltage (VOUT) ..........0.815V to 0.95 x VIN
Operating junction temp (TJ) .... -40°C to +150°C
Notes:
2) Exceeding these ratings may damage the device.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX) - TA) / θJA. Exceeding the maximum allowable power
dissipation can cause excessive die temperature, and the
regulator may go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
4) Measured on JESD51-7, 4-layer PCB. The values given in this
table are only valid for comparison with other packages and
cannot be used for design purposes. These values were
calculated in accordance with JESD51-7, and simulated on a
specified JEDEC board. They do not represent the
performance obtained in an actual application.
5) Measured on an MPS standard EVB: 9cmx9cm, 2-oz copper,
4-Layer PCB.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, typical values are at TJ = 25°C, unless otherwise noted.
Parameter
VIN under-voltage lockout
(UVLO) rising threshold
VIN UVLO falling threshold
VIN UVLO hysteresis
VCC voltage
Symbol
VIN_UVLO_
RISING
VIN_UVLO_
FALLING
VIN quiescent current
Min
Typ
Max
Units
2.8
3
3.2
V
2.5
2.7
2.9
V
VIN_UVLO_HYS
VCC
VCC regulation
VCC current limit
Condition
280
IVCC = 0A
4.6
IVCC = 30mA
ILIMIT_VCC
IQ
VCC = 4V
(6)
FB = 0.85V, no load, (sleep
mode)
VIN shutdown current
ISHDN
FB reference voltage
VFB
FB current
IFB
Switching frequency
fSW
Minimum on time (6)
Minimum off time (6)
tON_MIN
tOFF_MIN
SYNCIN voltage rising threshold
EN = 0V
RFREQ = 26.1kΩ
VSYNC_RISING
SYNCIN voltage falling threshold VSYNC_FALLING
SYNCIN clock range
fSYNC
SYNCO high voltage
VSYNCO_HIGH
SYNCO low voltage
VSYNCO_LOW
SYNCO phase shift
High-side (HS) current limit
ILIMIT
Low-side (LS) valley current limit
MODE = high (FCCM),
switching, fSW = 2MHz, no load
MODE = high (FCCM),
switching, fSW = 470kHz, no
load
VIN = 3.3V to 45V, TJ = 25°C
VIN = 3.3V to 45V
VFB = 0.85V
RFREQ = 62kΩ
ILIMIT_VALLEY
5.2
V
1
4
%
mA
18
RFB_UP = 1MΩ,
RFB_DOWN = 316kΩ
IQ_ACTIVE
4.9
100
MODE = GND (AAM),
switching, no load,
VIN quiescent current (switching)
mV
820
μA
40
mA
9.5
mA
3.5
0.815 0.823
0.815 0.831
0
+50
470
520
1000
100
80
1180
μA
V
V
nA
kHz
ns
ns
1.8
External clock
ISYNCO = -1mA
ISYNCO = 1mA
Tested under SYNCIN
Duty cycle = 30%
μA
20
1.7
0.807
0.799
-50
420
26
V
0.4
1000
350
3.3
4.5
4.4
180
5.5
6.6
V
kHz
V
V
deg
A
3.2
4
4.8
A
0.4
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, typical values are at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Zero-current detection (ZCD)
IZCD
current
LS reverse current limit
ILIMIT_REVERSE
Switch leakage current
ISW_LKG
High-side MOSFET (HS-FET)
RDS(ON)_HS
on resistance
Low-side MOSFET (LS-FET) on
RDS(ON)_LS
resistance
Soft-start current
ISS
Condition
Min
Typ
Max
Units
AAM
-0.15
0.10
+0.35
A
2
4.5
0.01
7
1
A
µA
VBST - VSW = 5V
48
80
mΩ
VCC = 5V
20
40
mΩ
8
13
19
µA
FCCM
VSS = 0V
EN rising threshold
VEN_RISING
0.8
1.0
1.2
V
EN falling threshold
VEN_FALLING
0.65
0.85
1.05
V
EN hysteresis voltage
VEN_HYS
MODE rising threshold
VMODE_RISING
MODE falling threshold
VMODE_FALLING
PG rising threshold (VFB / VREF)
PG falling threshold (VFB / VREF)
PG output voltage low
PG rising delay
PG falling delay
(6)
Thermal shutdown
Thermal shutdown hysteresis (6)
190
mV
1.8
V
0.4
PGRISING
VFB rising
VFB falling
92%
102%
95%
105%
98%
108%
PGFALLING
VFB falling
VFB rising
90.5%
103.5%
93.5%
106.5%
96.5%
109.5%
0.1
0.3
VPG_LOW
ISINK = 1mA
V
VREF
V
tPG_R_DELAY
35
µs
tPG_F_DELAY
35
µs
TSD
TSD_HYS
170
20
°C
°C
Note:
6) Derived from bench characterization. Not tested in production.
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Quiescent Current vs. Temperature
Feedback Voltage vs. Temperature
0.818
23
22
0.817
0.816
20
VFB (V)
IQ (μA)
21
19
0.815
18
0.814
17
0.813
16
15
0.812
-50
-25
0
25
50
75
100
125
-50
-25
TEMPERATURE (°C)
Current Limit vs. Temperature
4.4
5.55
4.2
ILIMIT_VALLEY (A)
ILIMIT (A)
100
125
Valley Current Limit vs. Temperature
5.60
5.50
5.45
5.40
4.0
3.8
3.6
5.35
5.30
3.4
-50
-25
0
25
50
75
100
125
-50
-25
TEMPERATURE (°C)
Reverse Current Limit vs.
Temperature
0
25
50
75
TEMPERATURE (°C)
100
125
VIN UVLO Threshold vs. Temperature
3.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.0
VIN UVLO (V)
ILIMIT_REVERSE (A)
0
25
50
75
TEMPERATURE (°C)
2.9
VIN UVLO Rising
2.8
VIN UVLO Falling
2.7
2.6
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
-50
-25
0
25
50
75
TEMPERATURE (°C)
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100
125
8
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
PG Rising/Falling Threshold vs.
Temperature
EN UVLO Threshold vs. Temperature
EN UVLO (V)
1.00
0.95
EN UVLO Rising
EN UVLO Falling
0.90
0.85
0.80
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
PG THRESHOLD (% OF VREF)
1.05
110
108
106
104
102
100
98
96
94
92
90
88
-50
-25
Falling Threshold
Rising Threshold
Rising Threshold
Falling Threshold
0
25
50
75
TEMPERATURE (°C)
100
125
100
125
100
125
RDS(ON)_HS vs. Temperature
2.2
70
2.1
65
2.0
60
RDS(ON_HS (mΩ)
ISD (μA)
VIN Shutdown Current vs.
Temperature
1.9
1.8
1.7
1.6
55
50
45
40
1.5
35
1.4
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
-50
125
RDS(ON)_LS vs. Temperature
-25
0
25
50
75
TEMPERATURE (°C)
VCC vs. Temperature
30
4.96
28
4.95
4.94
26
4.93
VCC (V)
RDS(ON)_LS (mΩ)
PG Upper
PG Lower
PG Upper
PG Lower
24
22
4.92
4.91
4.90
20
4.89
18
4.88
16
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
4.87
-50
-25
0
25
50
75
TEMPERATURE (°C)
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Zero-Current Detection vs.
Temperature
Soft-Start Current vs. Temperature
150
15.0
14.5
130
ZCD (mA)
ISS (μA)
14.0
13.5
13.0
12.5
12.0
110
90
70
11.5
11.0
50
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
100
125
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
fSW vs. Temperature
RFREQ = 62kΩ
473
472
fSW (kHz)
471
470
469
468
467
466
465
-50
-25
0
25
50
75
TEMPERATURE (°C)
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 5.6μH (7), fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Input Current vs. Load Current
Input Current vs. Load Current
AAM mode, VOUT = 3.3V
AAM mode, VOUT = 5V
100
VIN=24V
80
VIN=36V
70
VIN=45V
INPUT CURRENT (µA)
INPUT CURRENT (µA)
140
VIN=12V
90
60
50
40
30
20
VIN=12V
VIN=24V
VIN=36V
VIN=45V
120
100
80
60
40
20
10
20
30
40
50
60
70
80
90 100
10
LOAD CURRENT (µA)
80
90
70
80
EFFICIENCY (%)
EFFICIENCY (%)
90
60
50
40
Vin=12V
Vin=24V
Vin=36V
Vin=45V
10
10
50
100
500
LOAD CURRENT (mA)
1000
Efficiency vs. Load Current
FCCM, VOUT = 3.3V
Vin=12V
Vin=24V
Vin=36V
Vin=45V
1600
1800
LOAD CURRENT (mA)
2000
EFFICIENCY (%)
EFFICIENCY (%)
90 100
Vin=12V
Vin=24V
Vin=36V
Vin=45V
30
5
1
50
AAM mode, VOUT = 3.3V
1400
80
60
Efficiency vs. Load Current
1200
70
70
LOAD CURRENT (mA)
100
98
96
94
92
90
88
86
84
82
80
1000
60
40
10
0.5
50
AAM mode, VOUT = 3.3V
100
0.1
40
Efficiency vs. Load Current
AAM mode, VOUT = 3.3V
20
30
LOAD CURRENT (µA)
Efficiency vs. Load Current
30
20
20
18
16
14
12
10
8
6
4
2
0
Vin=12V
Vin=24V
Vin=36V
Vin=45V
0.1
5
0.5
1
LOAD CURRENT (mA)
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11
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH (7), fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Efficiency vs. Load Current
EFFICIENCY (%)
Vin=12V
Vin=24V
Vin=36V
Vin=45V
10
50
500
100
LOAD CURRENT (mA)
1000
Vin=12V
Vin=24V
Vin=36V
Vin=45V
1200
1400
1600
1800
Efficiency vs. Load Current
AAM mode, VOUT = 5V
100
Vin=12V
Vin=24V
Vin=36V
Vin=45V
70
90
60
50
40
30
80
70
60
Vin=12V
Vin=24V
Vin=36V
Vin=45V
50
40
20
30
10
0.1
0.5
1
LOAD CURRENT (mA)
5
10
10
50
500
100
LOAD CURRENT (mA)
Efficiency vs. Load Current
AAM mode, VOUT = 5V
FCCM, VOUT = 5V
EFFICIENCY (%)
Efficiency vs. Load Current
100
98
96
94
92
90
88
86
84
82
80
1000
Vin=12V
Vin=24V
Vin=36V
Vin=45V
1200
1400
2000
LOAD CURRENT (mA)
AAM mode, VOUT = 5V
80
EFFICIENCY (%)
100
98
96
94
92
90
88
86
84
82
80
1000
Efficiency vs. Load Current
90
EFFICIENCY (%)
FCCM, VOUT = 3.3V
100
90
80
70
60
50
40
30
20
10
0
EFFICIENCY (%)
EFFICIENCY (%)
FCCM, VOUT = 3.3V
1600
1800
LOAD CURRENT (mA)
2000
24
22
20
18
16
14
12
10
8
6
4
2
0
1000
Vin=12V
Vin=24V
Vin=36V
Vin=45V
0.1
0.5
5
1
LOAD CURRENT (mA)
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12
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH (7), fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
EFFICIENCY (%)
EFFICIENCY (%)
FCCM, VOUT = 5V
Vin=12V
Vin=24V
Vin=36V
Vin=45V
10
50
100
500
1000
FCCM, VOUT = 5V
100
98
96
94
92
90
88
86
84
82
80
1000
1200
1400
LOAD CURRENT (mA)
Vin=12V
Vin=24V
Vin=36V
Vin=45V
1600
1800
2000
LOAD CURRENT (mA)
Load Regulation
Load Regulation
AAM mode, VOUT = 3.3V
FCCM, VOUT = 3.3V
0.10
0.09
VIN=12V
VIN=24V
VIN=36V
VIN=45V
0.06
LOAD REGULATION (%)
LOAD REGULATION (%)
0.12
0.03
0.00
-0.03
-0.06
100
LOAD CURRENT (mA)
1000
0.04
0.01
-0.02
-0.05
-0.08
2000
10
100
1000
LOAD CURRENT (mA)
Line Regulation
Line Regulation
AAM mode, VOUT = 3.3V
FCCM, VOUT = 3.3V
0.08
0.08
0.06
0.06
LINE REGULATION (%)
LINE REGULATION (%)
10
VIN=12V
VIN=24V
VIN=36V
VIN=45V
0.07
Io=10mA
Io=1A
Io=2A
0.04
0.02
0.00
-0.02
-0.04
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
40
45
0.04
2000
Io=10mA
Io=1A
Io=2A
0.02
0.00
-0.02
-0.04
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
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45
13
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH (7), fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Load Regulation
Load Regulation
AAM mode, VOUT = 5V
FCCM, VOUT = 5V
0.12
0.08
0.06
LOAD REGULATION (%)
LOAD REGULATION (%)
0.09
VIN=12V
VIN=24V
VIN=36V
VIN=45V
0.03
0.00
-0.03
-0.06
10
100
1000
0.05
VIN=12V
VIN=24V
VIN=36V
VIN=45V
0.02
-0.01
-0.04
2000
10
100
LOAD CURRENT (mA)
Line Regulation
Line Regulation
AAM mode, VOUT = 5V
FCCM, VOUT = 5V
0.08
0.08
Io=10mA
Io=1A
Io=2A
0.06
LINE REGULATION (%)
LINE REGULATION (%)
2000
LOAD CURRENT (mA)
0.10
0.04
0.02
0.00
-0.02
0.06
0.04
Io=10mA
Io=1A
Io=2A
0.02
0.00
-0.02
-0.04
5
10
15
20
25
30
35
40
45
5
10
15
INPUT VOLTAGE (V)
20
25
30
35
40
45
INPUT VOLTAGE (V)
Case Temperature Rise
Case Temperature Rise
VOUT = 3.3V
VOUT = 5V
10
CASE TEMPERATURE RISE
( C)
10
CASE TEMPERATURE RISE
(°C)
1000
8
6
4
2
0
0.0
0.5
1.0
1.5
LOAD CURRENT (A)
2.0
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH (7), fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
fSW vs. RFREQ
fSW vs. RFREQ
RFREQ = 30kΩ to 100kΩ
2400
2250
2100
1950
1800
1650
1500
1350
1200
1050
900
900
800
fSW (kHz)
fSW (kHz)
RFREQ = 10kΩ to 30kΩ
700
600
500
400
300
10 12 14 16 18 20 22 24 26 28 30
30
RFREQ (kΩ)
60
70
80
90
100
Low-Dropout Mode
5.2
Rfreq=62K
Rfreq=12K
4.9
4.6
VOUT (V)
fsw (kHz)
50
RFREQ (kΩ)
fSW vs. VIN
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
40
4.3
4.0
3.7
IOUT=0A
3.4
3.1
IOUT=1A
2.8
IOUT=2A
2.5
6 9 12 15 18 21 24 27 30 33 36 39 42 45
VIN (V)
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
VIN (V)
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, IOUT = 2A, L = 5.6μH (7), fSW = 470kHz, TA = 25°C, unless otherwise noted. (8)
CISPR25 Class 5 Peak Conducted
Emissions
CISPR25 Class 5 Average Conducted
Emissions
150kHz to 108MHz
AVG CONDUCTED EMI (dBuV)
PK CONDUCTED EMI (dBuV)
150kHz to 108MHz
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
CISPR25 CLASS 5 PK LIMITS
PK NOISE FLOOR
1
0.1
Frequency (MHz)
108
10
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
CISPR25 CLASS 5 AVG LIMITS
0.1
CISPR25 Class 5 Peak Radiated
Emissions
PK RADIATED EMI (dBuV)
AVG RADIATED EMI (dBuV)
PK NOISE FLOOR
1
Frequency (MHz)
30
10
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
AVG RADIATED EMI (dBuV)
PK RADIATED EMI (dBuV)
CISPR25 CLASS 5 PK LIMITS
PK NOISE FLOOR
230
330
430
530
630
Frequency (MHz)
1
Frequency (MHz)
30
10
Horizontal, 30MHz to 1GHz
HORIZONTAL POLARIZATION
130
AVG NOISE FLOOR
CISPR25 Class 5 Average Radiated
Emissions
Horizontal, 30MHz to 1GHz
30
108
10
CISPR25 CLASS 5 AVG LIMITS
0.1
CISPR25 Class 5 Peak Radiated
Emissions
55
50
45
40
35
30
25
20
15
10
5
0
-5
Frequency (MHz)
150kHz to 30MHz
CISPR25 CLASS 5 PK LIMITS
0.1
1
CISPR25 Class 5 Average Radiated
Emissions
150kHz to 30MHz
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
AVG NOISE FLOOR
730
830
930
55
50
45
40
35
30
25
20
15
10
5
0
-5
HORIZONTAL POLARIZATION
CISPR25 CLASS 5 AVG LIMITS
AVG NOISE FLOOR
30
130
230
330
430
530
630
Frequency (MHz)
730
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830
930 1000
16
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, IOUT = 2A, L = 5.6μH (7), fSW = 470kHz, TA = 25°C, unless otherwise noted. (8)
CISPR25 Class 5 Peak Radiated
Emissions
CISPR25 Class 5 Average Radiated
Emissions
Vertical, 30MHz to 1GHz
VERTICAL POLARIZATION
AVG RADIATED EMI (dBuV)
PK RADIATED EMI (dBuV)
Vertical, 30MHz to 1GHz
55
50
45
40
35
30
25
20
15
10
5
0
-5
CISPR25 CLASS 5 PK LIMITS
PK NOISE FLOOR
30
130
230
330
430
530
630
Frequency (MHz)
730
830
930 1000
55
50
45
40
35
30
25
20
15
10
5
0
-5
VERTICAL POLARIZATION
CISPR25 CLASS 5 AVG LIMITS
AVG NOISE FLOOR
30
130
230
330
430
530
630
Frequency (MHz)
730
830
930 1000
Notes:
7)
8)
Inductor part number: XAL6060-562MEC. DCR = 14.5mΩ.
The EMC test results are based on the application circuit with EMI filters (see Figure 11 on page 34).
MPQ4312 Rev. 1.0
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17
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Steady State
Steady State
IOUT = 0A, AAM mode
IOUT = 0A, FCCM
CH2:
VOUT/AC
50mV/div.
CH3: PG
5V/div.
CH1: VSW
5V/div.
CH2:
VOUT/AC
5mV/div.
CH4: IL
1A/div.
CH4: IL
500mA/div.
CH1: VSW
5V/div.
2μs/div.
40ms/div.
Steady State
Start-Up through VIN
IOUT = 2A
IOUT = 0A, AAM mode
CH3: PG
5V/div.
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH2:
VOUT/AC
5mV/div.
CH2: VOUT
1V/div.
CH4: IL
1A/div.
CH4: IL
1A/div.
CH1: VSW
10V/div.
2μs/div.
1ms/div.
Start-Up through VIN
Start-Up through VIN
IOUT = 0A, FCCM
IOUT = 2A
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH2: VOUT
2V/div.
R1: PG
5V/div
CH4: IL
2A/div.
CH2: VOUT
2V/div.
R1: PG
5V/div
CH4: IL
2A/div.
1ms/div.
1ms/div.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Shutdown through VIN
Shutdown through VIN
IOUT = 0A, AAM mode
IOUT = 0A, FCCM
CH3: VIN
5V/div.
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH4: IL
1A/div.
CH2: VOUT
1V/div.
CH2: VOUT
2V/div.
R1: PG
5V/div
CH4: IL
1A/div.
CH1: VSW
5V/div.
10ms/div.
10ms/div.
Shutdown through VIN
Start-Up through EN
IOUT = 2A
IOUT = 0A, AAM mode
CH3: VEN
2V/div.
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH2: VOUT
1V/div.
CH2: VOUT
2V/div.
R1: PG
5V/div
CH4: IL
2A/div.
CH4: IL
2A/div.
CH1: VSW
10V/div.
4ms/div.
1ms/div.
Start-Up through EN
Start-Up through EN
IOUT = 0A, FCCM
IOUT = 2A
CH3: VEN
2V/div.
CH3: VEN
2V/div.
CH1: VSW
5V/div.
CH1: VSW
5V/div.
CH2: VOUT
2V/div.
R1: PG
5V/div
CH4: IL
2A/div.
CH2: VOUT
2V/div.
R1: PG
5V/div
CH4: IL
2A/div.
1ms/div.
1ms/div.
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
Shutdown through EN
Shutdown through EN
IOUT = 0A, AAM mode
IOUT = 0A, FCCM
CH3: VEN
2V/div.
CH3: VEN
2V/div.
CH1: VSW
5V/div.
R1: PG
5V/div
CH2: VOUT
2V/div.
CH4: IL
1A/div.
CH4: IL
1A/div.
CH2: VOUT
1V/div.
CH1: VSW
5V/div.
100ms/div.
100ms/div.
Shutdown through EN
SCP Entry
IOUT = 2A
IOUT = 0A, AAM mode
CH3: VEN
2V/div.
CH2: VOUT
2V/div.
CH3: VPG
5V/div.
CH1: VSW
5V/div.
R1: PG
5V/div
CH2: VOUT
2V/div.
CH4: IL
2A/div.
CH4: IL
5A/div.
CH1: VSW
10V/div.
100µs/div.
20ms/div.
SCP Entry
SCP Entry
IOUT = 0A, FCCM
IOUT = 2A
CH3: VPG
5V/div.
CH3: VPG
5V/div.
CH1: VSW
5V/div.
CH1: VSW
5V/div.
CH2: VOUT
2V/div.
CH2: VOUT
2V/div.
CH4: IL
5A/div.
CH4: IL
5A/div.
20ms/div.
20ms/div.
MPQ4312 Rev. 1.0
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
SCP Recovery
SCP Recovery
IOUT = 0A, AAM mode
IOUT = 0A, FCCM
CH3: VPG
5V/div.
CH2: VOUT
2V/div.
CH3: VPG
5V/div.
CH1: VSW
5V/div.
CH4: IL
5A/div.
CH2: VOUT
2V/div.
CH1: VSW
10V/div.
CH4: IL
5A/div.
10ms/div.
10ms/div.
SCP Recovery
SCP Steady State
IOUT = 2A
CH3: VPG
5V/div.
CH3: VPG
5V/div.
CH1: VSW
5V/div.
CH1: VSW
5V/div.
CH2: VOUT
2V/div.
CH2: VOUT
2V/div.
CH4: IL
5A/div.
CH4: IL
5A/div.
10ms/div.
10ms/div.
Load Transient
SYNC Operation
IOUT = 1A to 2A, 1.6A/μs
IOUT = 2A, fSYNC = 350kHz
CH3:
SYNCIN
2V/div.
CH2: VOUTAC
100mV/div.
CH1: VSW
5V/div.
CH2: VOUT
2V/div.
CH4: IL
2A/div.
CH4: IOUT
1A/div.
100µs/div.
2µs/div.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
SYNC Operation
SYNCO Operation
IOUT = 2A, fSYNC = 1000kHz
IOUT = 2A, fSYNC = 350kHz
CH3:
SYNCIN
2V/div.
CH3:
SYNCO
2V/div.
CH2: VOUT
1V/div.
CH4: IL
2A/div.
CH1: VSW
5V/div.
CH2: VOUT
1V/div.
CH4: IL
2A/div.
CH1: VSW
5V/div.
1µs/div.
2µs/div.
SYNCO Operation
PG in Start-Up through VIN
IOUT = 2A, fSYNC = 1000kHz
IOUT = 0A, AAM mode
CH3:
SYNCO
2V/div.
CH3: VIN
5V/div.
CH2: VOUT
2V/div.
CH2: VOUT
1V/div.
CH4: IL
2A/div.
CH1: VSW
5V/div.
CH4: VPG
2V/div.
CH1: VSW
10V/div.
1µs/div.
1ms/div.
PG in Shutdown through VIN
PG in Start-Up through EN
IOUT = 0A, AAM mode
IOUT = 0A, AAM mode
CH3: VEN
2V/div.
CH3: VIN
5V/div.
CH2: VOUT
2V/div.
CH2: VOUT
2V/div.
CH4: VPG
2V/div.
CH4: VPG
2V/div.
CH1: VSW
5V/div.
CH1: VSW
5V/div.
20ms/div.
1ms/div.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
PG in Shutdown through EN
Low-Dropout Mode
IOUT = 0A, AAM mode
VIN = 3.3V, VOUT set to 3.3V, IOUT = 0A
CH3: VEN
2V/div.
CH4: IL
50mA/div.
CH2: VOUT
2V/div.
CH3: VIN
500mV/div.
CH1: VSW
1V/div.
CH2: VOUT
500mV/div.
CH4: VPG
2V/div.
CH1: VSW
5V/div.
100ms/div.
4µs/div.
Low-Dropout Mode
Load Dump
VIN = 3.3V, VOUT set to 3.3V, IOUT = 2A
VIN = 12V to 36V, IOUT = 2A
CH3: VIN
10V/div.
CH1: VSW
10V/div.
CH1: VSW
1V/div.
CH3: VIN
500mV/div.
CH4: IL
2A/div.
CH2: VOUT
500mV/div.
CH2: VOUT
2V/div.
CH4: IL
2A/div.
4µs/div.
100ms/div.
Cold Crank
VIN Ramping Up and Down
VIN = 12V to 3.3V to 5V, IOUT = 2A
IOUT = 0.1A
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH3: VIN
1V/div.
CH2: VOUT
1V/div.
CH2: VOUT
2V/div.
CH4: IL
2A/div.
40ms/div.
1s/div.
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23
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 5.6μH, fSW = 470kHz, AAM mode, TA = 25°C, unless otherwise noted.
VIN Ramping Down and Up
VIN Ramping Down and Up
IOUT = 1mA
IOUT = 2A
4.5V
CH3: VIN
10V/div.
4.5V
CH3: VIN
5V/div.
CH1: VSW
5V/div.
CH2: VOUT
2V/div.
CH4: IL
2A/div.
CH2: VOUT
2V/div.
CH4: IL
2A/div.
CH1: VSW
20V/div.
10s/div.
10s/div.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
VCC
Regulator
VREF
EN
Reference
BST
Regulator
BST
FREQ
ISW
Oscillator
SYNCIN
SYNCO
PG
+
-
VPG_REF
VFB
Control Logic
SW
VCC
ISS
Error Amplifier
VREF
SS
VIN
VCC
VFB
+
+
-
VCOMP
1.15M
2pF
ILS
60pF
PGND
FB
AGND
MODE
Figure 1: Functional Block Diagram
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
TIMING SEQUENCE
VIN
0
SW
0
EN
Threshold
EN
0
VCC
Threshold
VCC
0
VOUT
15µs
95% of
VREF
93.5% of
VREF
95% of
VREF
106.5% Of
VREF
105% of VREF
93.5% of VREF
70% of VREF
SS
0
IL = I LIMIT
IL
0
PG
35µs
35µs
35µs
35µs
35µs
35µs
0
Start-Up
N o r m al
N o r m al
OCP
OV
N o r m al
Shutdown
OC
Release
Figure 2: Timing Sequence
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
OPERATION
The MPQ4312 is a synchronous, step-down
switching converter with integrated internal highside and low-side power MOSFETs (HS-FET
and LS-FET, respectively). The device provides
2A of highly efficient output current (IOUT) with
current mode control.
The MPQ4312 features a wide input voltage (VIN)
range, configurable switching frequency (fSW),
external soft start (SS), and a precise current
limit. The device’s low operational quiescent
current (IQ) makes it well-suited for batterypowered applications.
PWM Control
At moderate to high output currents, the
MPQ4312 operates with fixed-frequency, peak
current control to regulate the output voltage
(VOUT). A PWM cycle is initiated by the internal
clock. At the rising edge of the clock, the HS-FET
turns on. The HS-FET remains on for at least
100ns, until its current reaches the value set by
the internal COMP voltage (VCOMP).
When the HS-FET is off, the LS-FET
immediately turns on, and remains on until the
next cycle starts. The LS-FET remains on for at
least 80ns before the next cycle starts.
If the current in the HS-FET does not reach the
value set by COMP within one PWM period, then
the HS-FET remains on, which saves a turn-off
operation. The HS-FET is forced off after about
10µs, even if it does not reach the value set by
COMP.
Light-Load Operation
Under light-load conditions, the MPQ4312 can
work in two different operation modes based on
the MODE pin.
The MPQ4312 works in forced continuous
conduction mode (FCCM) when the MODE pin
is pulled above 1.8V. In FCCM, the device works
with a fixed frequency from no-load to full-load
conditions. The advantage of FCCM is its
controllable frequency and lower output ripple
under light loads.
The chip works in advanced asynchronous
modulation (AAM) mode when the MODE pin is
pulled below 0.4V. AAM mode optimizes
efficiency under
conditions.
light-load
and
no-load
When AAM mode is enabled, the MPQ4312
enters asynchronous operation while the
inductor current (IL) approaches 0A under light
loads (see Figure 3). If the load is further
decreased or there is no load, VCOMP drops to the
set value, and the MPQ4312 enters AAM mode.
Inductor
Current
Load
Decreases
Inductor
Current
AAM
FCCM
t
t
Load
t Decreases
t
t
t
Figure 3: AAM and FCCM
In AAM mode, the internal clock resets when
VCOMP crosses the set value. The crossover time
is used as the benchmark for the next clock.
When the load increases and VCOMP exceeds the
set value, the device operates in discontinuous
conduction mode (DCM) or CCM, both of which
have a constant fSW.
Error Amplifier (EA)
The error amplifier (EA) compares the FB pin
voltage (VFB) to the internal reference voltage
(VREF, typically 0.815V), and outputs a current
proportional to the difference between the two
voltages. IOUT charges the compensation
network to form VCOMP, which controls the
MOSFET current.
During normal operation, the minimum VCOMP is
clamped to 0.9V, and its maximum is clamped to
2V. COMP is internally pulled down to GND
when the device shuts down.
Internal Regulator VCC
The internal 4.9V regulator (VCC) powers most
of the internal circuitry. This regulator uses VIN
as the input and operates in the full VIN range.
When VIN exceeds 4.9V, VCC is in full regulation.
When VIN is below 4.9V, the VCC output
degrades.
Bootstrap (BST) Charging
The bootstrap (BST) capacitor (CBST) is charged
and regulated to about 5V by the dedicated
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
internal BST regulator. When the voltage
between the BST and SW nodes drops below its
regulated value, a P-channel MOSFET pass
transistor connected from VCC to BST turns on
to charge CBST. The external circuit should
provide enough voltage headroom to facilitate
charging. When the HS-FET is on, BST exceeds
VCC, which means that CBST cannot be charged.
Under higher duty cycles, there is less time for
CBST to charge, so it may not be charged
sufficiently. If the external circuit has an
insufficient voltage (or not enough time) to
charge CBST, use additional external circuitry to
ensure that the BST voltage (VBST) remains in the
normal operation range.
Low-Dropout Mode and BST Refresh
To improve dropout, the MPQ4312 is designed
to operate at close to 100% duty cycle when the
difference between the voltages on the BST and
SW pins exceeds 2.5V. When the voltage from
BST to SW drops below 2.5V, the HS-FET turns
off using an under-voltage lockout (UVLO) circuit.
This allows the LS-FET to conduct and refresh
the charge on CBST. In DCM or pulse-skip mode
(PSM), the LS-FET is forced on to refresh VBST.
Since the supply current sourced from CBST is
low, the HS-FET can remain on for more
switching cycles than are required to refresh the
capacitor. As a result, the effective duty cycle of
the switching regulator is high.
The regulator’s effective duty cycle during
dropout is mainly influenced by the voltage drops
across the power MOSFET, the inductor
resistance, the low-side diode, and the PCB
resistance.
Enable Control
EN is a digital control pin that turns the
MPQ4312 on and off.
Enabled by an External Logic (High/Low)
Signal
When EN is pulled below its falling threshold
voltage (about 0.85V), the chip operates in the
lowest shutdown current mode. Pull EN above its
rising threshold voltage (about 1V) to enable the
part.
Configurable VIN Under-Voltage Lockout
(UVLO)
When VIN is sufficiently high, the chip can be
enabled and disabled via the EN pin. With an
internal current source, the circuit can generate
a configurable VIN UVLO threshold and
hysteresis. Use resistor dividers to set the EN
voltage (see Figure 4).
VIN
REN1
EN
REN2
Figure 4: Enable Divider Circuit
Configurable Frequency and Foldback
The MPQ4312’s oscillating frequency can be
configured via an external resistor (RFREQ)
connected from the FREQ pin to ground, or by a
logic level SYNC signal.
To set fSW, select RFREQ using the fSW vs. RFREQ
curve on page 15. When fSW is set high, it may
fold back at high input voltages to avoid
triggering a minimum on time and forcing the
output out of regulation.
In car-battery applications, fSW is between
350kHz and 1000kHz. Table 1 lists the
recommended RFREQ values for common
frequencies. Higher frequencies can be used in
applications that do not have a critical fSW limit,
as well as applications with a low and stable VIN.
Table 1: RFREQ vs. fSW
RFREQ (kΩ)
86.6
80.6
75
62
59
54.9
49.9
45.3
41.2
37.4
34
30.9
28.7
26.1
fSW (kHz)
350
380
410
470
500
530
590
640
700
760
830
910
960
1000
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
Frequency Spread Spectrum
The MPQ4312 uses a 12kHz modulation
frequency with a fixed 128-step triangular profile
to spread the internal oscillator frequency across
a 20% (±10%) window (see Figure 5). The steps
are fixed and independent of the set oscillator
frequency, which optimizes frequency spread
spectrum (FSS) performance.
128 steps are
fixed
power MOSFETs. When the temperature falls
below the lower threshold (150°C), the chip
starts up again and resumes normal operation.
Current Comparator and Current Limit
The power MOSFET current is accurately
sensed via a current-sense MOSFET. This
current is then fed to the high-speed current
comparator for current mode control. The current
comparator uses this sensed current as one of
its inputs.
fSPAN = 20% x fSW
fMOD = 12kHz
Figure 5: Frequency Spread Spectrum Scheme
Side bands are created by modulating fSW with a
triangle modulation waveform. This reduces the
emission power of the fundamental fSW, as well
as its harmonics, which then reduces peak
electromagnetic interference (EMI) noise.
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter’s VOUT from overshooting during startup.
When SS begins, an internal current source
begins charging the external soft-start capacitor
(CSS). When the soft-start voltage (VSS) is below
the internal VREF, VSS overrides VREF and the EA
uses VSS as the reference. When VSS exceeds
VREF, the EA uses VREF as the reference.
CSS can be calculated with Equation (1):
CSS (nF) =
t SS (ms) ISS (A)
= 13.5 t SS (ms) (1)
VREF (V)
The SS pins can be used for tracking and
sequencing.
Pre-Biased Start-Up
If VFB exceeds VSS - 150mV during start-up, this
means that the output has a pre-biased voltage.
In the scenario, the HS-FET and LS-FET do not
turn on until VSS exceeds VFB.
Thermal Shutdown
Thermal shutdown is implemented to protect the
chip from thermal runaway. If the silicon die
temperature exceeds its upper threshold
(typically 170°C), the device shuts down the
When the HS-FET turns on, the comparator is
blanked until the end of the turn-on transition to
mitigate noise. The comparator compares the
MOSFET current to the value set by VCOMP.
When the sensed current exceeds the value set
by COMP, the comparator outputs low to turn off
the HS-FET. The MOSFET’s maximum current
is internally limited cycle by cycle.
Hiccup Protection
If the output is shorted to ground, VOUT may drop
below 70% of its nominal output. If this occurs,
the MPQ4312 shuts down momentarily and
begins discharging CSS. The device restarts with
a full soft start once CSS is fully discharged. This
process is repeated until the fault condition is
removed.
Start-Up and Shutdown
If both VIN and EN exceed their respective
thresholds, the chip starts. The reference block
starts first, generating a stable reference voltage
and currents, and then the internal regulator is
enabled. The regulator provides a stable supply
for the remaining circuitries.
While the internal supply rail is up, an internal
timer holds the power MOSFET off for about
50µs to blank the start-up glitches. When the
soft-start block is enabled, the SS output
remains low to ensure that the remaining
circuitries are ready before slowly ramping up.
Three events can shut down the chip: EN going
low, VIN going low, and thermal shutdown. When
shutdown is initiated, the signaling path is first
blocked to avoid any fault triggering. Next, VCOMP
and the internal supply rail are pulled down. The
floating driver is not subject to this shutdown
command, but its charging path is disabled.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
Power Good (PG) Output
The MPQ4312 includes an open-drain power
good (PG) output. If this function is used, a pullup resistor to power source is required. If VOUT is
within 95% to 105% of the nominal voltage, then
the PG pin goes high. If VOUT is above 106.5% or
below 93.5% of the nominal voltage, then PG
goes low
SYNCIN and SYNCO
fSW can be synchronized to the rising edge of the
clock signal applied at SYNCIN. The
recommended SYNCIN frequency range is
350kHz to 1000kHz. Ensure that SYNCIN’s off
time is shorter than the internal oscillator period.
Otherwise, the internal clock may turn on the HSFET before the rising edge of SYNCIN.
If the pulse width is too short, a clear rising and
falling edge may not be seen due to the parasitic
capacitance. It is recommended to make the
pulse longer than 100ns.
When using SYNCIN in AAM mode, drive
SYNCIN below its specified threshold (about
0.4V), or float the SYNCIN pin before starting up
the MPQ4312. Then add the external SYNCIN
clock. If using this function, connect a resistor
(10kΩ to 51kΩ) from SYNCIN to GND and do not
float SYNCIN.
The SYNCO pin provides a default 180° phaseshifted clock for the internal oscillator. If there is
no external SYNCIN clock, SYNCO can provide
a clock that is phase-shifted 180° compared to
the internal clock.
There is no limit for the SYNCIN pulse width, but
there is always parasitic capacitance on the pad.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider connected to FB
sets VOUT (see Figure 6).
MPQ4312
ICIN = ILOAD
VOUT
ICIN =
RFB2
(3)
Calculate RFB2 with Equation (2):
RFB1
VOUT
−1
0.815V
(2)
Table 2 lists the recommended feedback resistor
values for common output voltages.
Table 2: Resistor Selection for Output Voltages
VOUT (V)
RFB1 (kΩ)
RFB2 (kΩ)
3.3
100 (1%)
32.4 (1%)
5
100 (1%)
19.6 (1%)
ILOAD
2
(4)
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
Figure 6: Feedback Network
RFB2 =
VOUT
V
(1 − OUT )
VIN
VIN
The worst-case condition occurs at VIN = 2 x
VOUT, calculated with Equation (4):
RFB1
FB
The RMS current in the input capacitor (ICIN) can
be estimated with Equation (3):
Selecting the Input Capacitor
The step-down converter has a discontinuous
input current, and requires a capacitor to supply
AC current to the converter while maintaining the
DC input voltage. For the best performance, use
low-ESR capacitors. Ceramic capacitors with
X5R or X7R dielectrics are highly recommended
due to their low ESR and small temperature
coefficients.
For most applications, a 4.7µF to 10µF capacitor
is sufficient. It is strongly recommended to use
another, lower-value capacitor (e.g. 0.1µF) with
a small package size (0603) to absorb highfrequency switching noise. Place the smaller
capacitor as close to VIN and GND as possible.
Since the input capacitor (CIN) absorbs the input
switching current, it requires an adequate ripple
current rating.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, place a small, high-quality ceramic
capacitor (e.g. 0.1μF) as close to the device as
possible.
When using ceramic capacitors, ensure that they
have enough capacitance to provide a sufficient
charge to prevent an excessive voltage ripple at
the input. The input voltage ripple (∆VIN) caused
by the capacitance can be estimated with
Equation (5):
VIN =
ILOAD
V
V
OUT (1 − OUT )
fSW CIN VIN
VIN
(5)
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic, tantalum, or low-ESR
electrolytic capacitors. For the best results, use
low-ESR capacitors to keep the output voltage
ripple low. The output voltage ripple (∆VOUT) can
be calculated with Equation (6):
VOUT =
VOUT
V
1
(1 − OUT ) (RESR +
) (6)
fSW L
VIN
8 fSW COUT
Where L is the inductance, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency and causes the majority of the output
voltage ripple.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
For simplification, the output voltage ripple
(∆VOUT) can be estimated with Equation (7):
VOUT =
VOUT
V
(1 − OUT )
8 fSW L COUT
VIN
2
(7)
VIN and EN can be used to achieve a higher
equivalent UVLO threshold (see Figure 7).
VIN
RUP
EN
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output voltage
ripple (∆VOUT) can be calculated with Equation
(8):
VOUT
V
V
= OUT (1 − OUT ) RESR
fSW L
VIN
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
at least 25% greater than the maximum load
current is recommended for most applications.
For higher efficiency, choose an inductor with a
lower DC resistance. A larger-value inductor
results in less ripple current and a lower output
ripple voltage; however, it also has a larger
physical size, higher series resistance, and lower
saturation current. A good rule for determining
the inductance is to allow the inductor ripple
current to be approximately 30% of the
maximum load current. The inductance (L) can
then be calculated with Equation (9):
(9)
VIN_UVLO_RI SING = (1+
RUP
) VEN_RISING (11)
RDOWN
VIN_UVLO_FA LLING = (1+
RUP
) VEN_FALLING (12)
RDOWN
Where VEN_RISING is 1V, and VEN_FALLING is 0.85V.
Selecting the External BST Diode and
Resistor
An external BST diode can enhance the
regulator’s efficiency when the duty cycle is high.
A power supply between 2.5V and 5V can be
used to power the external bootstrap diode. It is
recommended to make VCC or VOUT the power
supply in the circuit (see Figure 8).
VCC
RBST
External BST Diode
IN4148
BST
VCC / VOUT
Choose the inductor ripple current to be
approximately 30% of the maximum load current.
The maximum inductor peak current (ILP) can be
calculated with Equation (10):
VOUT
V
(1 − OUT )
2fSW L
VIN
The UVLO rising and falling thresholds can be
calculated with Equation (11) and Equation (12),
respectively:
CBST
Where ∆IL is the peak-to-peak inductor ripple
current.
ILP = ILOAD +
RDOWN
Figure 7: Adjustable UVLO Using EN Divider
(8)
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MPQ4312 can be optimized for a wide range of
capacitance and ESR values.
VOUT
V
L=
(1 − OUT )
fSW IL
VIN
VIN
(10)
VIN Under-Voltage Lockout (UVLO) Setting
The MPQ4312 has an internal, fixed undervoltage lockout (UVLO) threshold. The rising
threshold is 3V, and the falling threshold is about
2.7V. For the applications that require a higher
UVLO point, an external resistor divider between
L
VOUT
SW
COUT
Figure 8: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the recommended CBST value is
between 0.1µF and 1μF. Connect a resistor
(RBST) in series with CBST to reduce the SW rising
rate and voltage spikes. This improves EMI
performance and reduces voltage stress at
higher input voltages. A higher resistance
reduces SW spikes but compromises efficiency,
so an appropriate tradeoff for the application
must be made. It is recommended for RBST to be
≤20Ω.
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
Selecting the VCC Capacitor
The VCC capacitor should be 10 times greater
than the boost capacitor. A VCC capacitor above
68µF (nominal) is not recommended.
PCB Layout Guidelines (9)
Efficient PCB layout, is critical for stable
operation. A 4-layer layout is strongly
recommended to achieve better thermal
performance. For the best results, refer to Figure
9 and follow the guidelines below:
1.
Place symmetric input capacitors as close to
the VIN and GND pins as possible.
2.
Connect a large ground plane directly to
PGND.
3.
Add vias near PGND if the bottom layer is a
ground plane.
4.
Ensure that the high-current paths at GND
and VIN have short, direct, and wide traces.
5.
Place the ceramic input capacitor, especially
the small package size (0603) input bypass
capacitor, as close to VIN and PGND as
possible to minimize high-frequency noise.
6.
Keep the connection of the input capacitor
and VIN as short and wide as possible.
7.
Place the VCC capacitor as close to the
VCC and GND pins as possible.
8.
Route SW and BST away from sensitive
analog areas, such as FB.
9.
Place the feedback resistors close to the
chip to ensure that the trace that connects to
FB is as short as possible.
Top Layer
Mid-Layer 1
Mid-Layer 2
10. Use multiple vias to connect the power
planes to the internal layers.
Note:
9) The recommended PCB layout is based on Figure 10 on page
34.
Bottom Layer
Figure 9: Recommended PCB Layout
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MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
6
TYPICAL APPLICATION
VIN = 3.3V to 45V
C1A C1B
GND
3, 12
C1C
EN
VIN
C1D
10µF 10µF 0.1µF
Typ 5.5A
ILIMIT
MPQ4312
0.85V 1V
9 EN
20
FREQ
2
SS
VOUT
GND
R5
32.4k
PG 14
PG
R6
100k
SYNCIN
16
VCC
R3
51k
C6
4.7µF FCCM
3
NC 15
MODE 1
2
JP1
AAM
4, 5,
10, 11
17 AGND
PGND
13 SYNCO
1
SYNCO
R4
100k
Typ 0.815V
C3
22nF
SYNCIN
3.3V/2A
C2A C2B
C5
47µF 47µF
10V
47pF 10V
1210 1210
5.6µH
18
FB
R2
62k
19
L1
7, 8
SW
R1
100k
0.1µF
C4
0.1µF
BST
U1
Figure 10: VOUT = 3.3V, fSW = 470kHz
4.7µH VIN
BLM41PG600SN1L
VEMI
CIN1
CIN2
1nF
10nF
GND
L1
GND
C1B
C1C
CIN5
47µF
C4
0.1µF
BST
VIN
C1D
10µF 10µF 0.1µF 0.1µF
L2
SW
R1
7, 8
L3
Typ 5.5A 5.6µH
ILIMIT
100k
MPQ4312
9
EN
20
FREQ
FB Typ 0.815V
SS
PG
47pF
10V
1210
10V
1210
10nF 1nF
10nF 1nF
GND
R5
19.6k
COUT2
COUT4
PG
R6
100k
NC
17
PGND
MODE
16
15
C6
4.7µF
3
VCC
SYNCO
AGND
13
SYNCIN
1
2
JP1
4, 5,
10, 11
2
R3
51k
C2B
47µF
5V/2A
VOUT
COUT3
14
C3
22nF
SYNCIN
C2A
47µF
18
R2
62k
19
C5
R4
100k
EN 0.85V 1V
SYNCO
COUT1
1
C1A
3, 12
CIN4
1µF
6
U1
VIN = 3.3V to 45V
CIN3
1µF
Figure 11: VOUT = 5V, fSW = 470kHz with EMI Filters
MPQ4312 Rev. 1.0
www.MonolithicPower.com
10/13/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
34
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
PACKAGE INFORMATION
QFN-20 (4mmx4mm)
Wettable Flank
PIN 1 ID
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
0.10x45°
TOP VIEW
BOTTOM VIEW
SIDE VIEW
SECTION A-A
NOTE:
1) THE LEAD SIDE IS WETTABLE.
2) ALL DIMENSIONS ARE IN MILLIMETERS.
3) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MPQ4312 Rev. 1.0
www.MonolithicPower.com
10/13/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
35
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
CARRIER INFORMATION
Pin1
1
1
ABCD
1
1
ABCD
ABCD
ABCD
Feed Direction
Part Number
Package
Description
Quantity/
Reel
Quantity/
Tube (10)
Quantity/
Tray
Reel
Diameter
Carrier
Tape
Width
Carrier
Tape
Pitch
MPQ4312GRE
-AEC1-Z
QFN-20
(4mmx4mm)
5000
N/A
N/A
13in
12mm
8mm
Note:
10) N/A indicates “not available” in tubes. For 500 pieces tape & reel prototype quantities, contact MPS. (Order code for 500 pieces partial reel
is “-P”. The tape & reel dimensions are the same as for full reel.)
MPQ4312 Rev. 1.0
www.MonolithicPower.com
10/13/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
36
MPQ4312 – 45V, 2A, LOW IQ, SYNC STEP-DOWN CONVERTER WITH FSS
REVISION HISTORY
Revision #
Revision Date
1.0
10/13/2021
Description
Pages Updated
Initial Release
-
Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that thirdparty Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume
any legal responsibility for any said applications.
MPQ4312 Rev. 1.0
www.MonolithicPower.com
10/13/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
37
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