MPQ4458DQT-LF-Z

MP2005 800mA High PSRR, ULDO Linear Regulator DESCRIPTION FEATURES The MP2005 is a micropower, ultra low-dropout LDO linear regulator. It has a 1.0V to 5.5V input voltage range and can regulate the output voltage from as low as 0.5V. The MP2005 can supply up to 800mA of load current with a typical dropout voltage of 90mV. It requires a bias supply (2.7V to 5.5V) separate from VIN to run the internal reference and LDO drive circuitry. The output current comes directly from the input voltage supply for high efficiency regulation. The 0.5V internal reference voltage allows the output to be programmed to a wide range of voltages (0.5V to 4V).       A low bias current of 100µA makes the MP2005 ideal for use in battery-powered applications. The bias supply VBIAS can be directly applied from the battery while VIN is powered from the high efficiency buck regulator (or other secondary supply). This reduces output noise and the size of the decoupling capacitor. Other features of MP2005 include thermal overload and current limit protection, stability with ultra low ESR ceramic capacitors as low as 1μF, and fast transient response. The MP2005 is available in a 8-pin QFN (2mm x 3mm) package.       Wide 1.0V to 5.5V Input Voltage Range Stable with 1μF Ceramic Capacitor Ultra-Low Dropout (ULDO) voltage: 90mV@800mA 2% Accurate Output Voltage Adjustable Output Range of 0.5V to 4V High PSRR o 65dB at 1KHz o 48dB at 1MHz Better Than 0.0005%/mA Load Regulation Stable With Low-ESR Output Capacitors Low 100μA Ground Current Internal Thermal Protection Current Limit Protection 1µA Typical Quiescent Current at Shutdown APPLICATIONS        Low Current Regulators Low Power Handheld Devices Battery Powered Systems Cellular Phones Portable Electronic Equipment Post Regulation for Switching Supplies Power Supplies Power All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 1 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR ORDERING INFORMATION Part Number* MP2005DD Package QFN-8 (2mm x 3mm) Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP2005DD–Z) For RoHS compliant packaging, add suffix –LF (e.g. MP2005DD–LF–Z) TOP MARKING N3: product code of MP2005DD; Y: year code; W: week code: LLL: lot number; PACKAGE REFERENCE MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 2 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance VBIAS, VIN to GND .......................... –0.3V to +6V FB, EN to GND ............................... –0.3V to 6V OUT ................................................ –0.3V to 6V Continuous Power Dissipation (TA = +25°C) (2) ..................................................................2.3W Junction Temperature .............................. 150C Lead Temperature ................................... 260C Storage Temperature ............. –65°C to +150C QFN-8 (2mm x 3mm) ............. 55 ...... 12 ... C/W Recommended Operating Conditions (3) Input Voltage VIN ............................ 1.0V to 5.5V Input Voltage VBIAS ......................... 2.7V to 5.5V Output Voltage ............................... 0.5V to 4.0V Load Current.......................... 800mA Maximum Operating Temperature............. –40C to +85C MP2005 Rev. 1.01 7/12/2018 (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 3 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR ELECTRICAL CHARACTERISTICS VIN = 1.5V, VBIAS = 3.6V, VOUT = 1.2V, C2 =4.7µF, C3 = 1µF, TA = +25C, unless otherwise noted. Parameter VIN Operating Voltage VBIAS Operating Voltage VIN Operating Current VBIAS Operating Current Symbol Condition FB Regulation Voltage Dropout Voltage VIN Line Regulation VBIAS Line Regulation Load Regulation VOUT = 1.2V IOUT = 10µA, VOUT = 1.2V IOUT = 1mA to 800mA –40C  TA  +85C, VOUT = 0.5 V IOUT = 800mA, VBIAS = 3.6V IOUT = 1mA, VIN = 1.0V to 5.5V VBIAS = 3.6V VOUT = 0.5V IOUT = 100mA, VBIAS = 2.7V to 5.5V VOUT = 0.5V VIN = 1.5V IOUT = 1mA to 800mA Min 1.0 2.7 0.490 0.487 VIN > VOUT + 0.5V, C2 = 10μF, VIN(AC) = 100mV, f = 1MHz PSRR EN Input High Voltage Typ 4 100 0.500 0.500 70 Max 5.5 5.5 10 150 0.510 0.512 90 mV %/V 0.04 %/V 0.0005 %/mA 48 dB 1.3 V 0.8 VEN = 1.2V V 0.002 EN Input Low Voltage EN Input Bias Current Units V V μA μA –1 +1 V μA Thermal Protection 155 C Thermal Protection Hysteresis 30 C μA GND Current ILOAD = 500mA 110 150 PIN FUNCTIONS Pin # Name Description 1 2 3, 6 4 IN BIAS NC GND 5 EN 7 FB 8 OUT Power Source Input. Bypass IN to GND with a 1µF or greater capacitor. Bias Voltage. Bypass to GND with a 1μF capacitor (or greater) No Connect. Ground. Enable Input. Drive EN high to turn on the MP2005, drive EN low to turn it off. For automatic startup, connect EN to Bias or VIN, and make sure EN voltage ≥1.3V. Feedback Input. Connect a resistive voltage divider from OUT to FB to set the output voltage. OUT feedback threshold is 0.5V. Regulator Output. OUT is the output of the linear regulator. Bypass OUT to GND with a 1µF or greater capacitor. MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 4 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS C1=C3=2.2uF, C2=4.7uF, VEN=VBIAS=3.6V, TA=25ºC, unless otherwise noted MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 5 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=C3=2.2uF, C2=4.7uF, VEN=VBIAS=3.6V, TA=25ºC, unless otherwise noted MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 6 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=C3=2.2uF, C2=4.7uF, VEN=VBIAS=3.6V, VIN=3.6V, TA=25ºC, unless otherwise noted MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 7 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR BLOCK DIAGRAM Figure 1—Block Diagram of Super Low Dropout Regulator MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 8 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR APPLICATION INFORMATION Setting the Output Voltage The MP2005 has an adjustable output voltage, set by using a resistive voltage divider from the output voltage to FB pin. The voltage divider divides the output voltage down to the feedback voltage by the ratio: VFB  VOUT R2 R1  R2 Where VFB is the feedback threshold voltage (VFB = 0.5V), and VOUT is the output voltage. Thus the output voltage is: VOUT  0.5  R1  R2 R2 R2 can be as high as 100kΩ, but a typical value is 10kΩ. Using that value, R1 is determined by: V  VFB R1  R2   OUT V FB     For example, for a 1.8V output voltage, R2 is 10kΩ, and R1 is 26kΩ. You can select a standard 26kΩ (±1%) resistor for R1. MP2005 Rev. 1.01 7/12/2018 The following table lists the selected R1 for various output voltages. Table 1—Adjustable Output Voltages R1 Values VOUT (V) R1 (kΩ) 1.25 15 1.5 1.8 2 2.5 2.8 3 3.3 20 26 30 40 46 50 56 4 70 R2 (kΩ) 10 Bias Input The bias input is designed for low drop application. The bias pin must be at least 2.7V, and at least 1.5V higher than the output. If VIN supply voltage meets these requirements, the bias pin can be tied to VIN. Feed Forward Capacitor Feed forward capacitor which a ceramic type capacitor parallels with R1 affects loop stability. According to actual application, MP2005 improves load transient performance by add a suitable feed forward capacitor. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 9 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR PCB Layout Guide 1) PCB layout is very important to achieve good regulation, ripple rejection, transient response and thermal performance. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take Figure 2 for reference. IN 2) 3) Input and output bypass ceramic capacitors are suggested to be put close to the IN Pin and OUT Pin respectively. Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. Connect IN, OUT and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. OUT C1 IN 1 8 OUT BIAS 2 7 FB NC 3 6 NC GND 4 5 EN C3 C2 R1 C4 R3 R2 BIAS GND Top Layer Bottom Layer Figure 2—PCB Layout MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 10 MP2005 – 800mA, HIGH PSRR, ULDO LINEAR REGULATOR PACKAGE OUTLINE DRAWING FOR 8L QFN (2x3mm) MF-PO-D-0039 revision 0.0 PACKAGE INFORMATION QFN8 (2mm x 3mm) 2.90 3.10 PIN 1 ID MARKING 0.30 0.50 0.18 0.30 1.90 2.10 PIN 1 ID INDEX AREA PIN 1 ID SEE DETAIL A 1.65 1.85 8 1 1.50 1.70 0.50 BSC 4 5 TOP VIEW BOTTOM VIEW PIN 1 ID OPTION A 0.30x45ºTYP. 0.80 1.00 PIN 1 ID OPTION B R0.20 TYP. 0.20 REF 0.00 0.05 SIDE VIEW DETAIL A 2.90 0.70 NOTE: 1.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VCED-2. 5) DRAWING IS NOT TO SCALE. 0.25 1.60 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2005 Rev. 1.01 7/12/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 11