MPQ6528GVE-AEC1-P

MPQ6528 5V to 60V, H-Bridge Gate Driver, AEC-Q100 Qualified DESCRIPTION FEATURES The MPQ6528 is an H-bridge gate driver IC that can drive two half-bridges with four N-channel power MOSFETs across a wide 5V to 60V input voltage (VIN) range. • • • The device’s integrated, regulated charge pump generates gate driver power (VREG), and a bootstrap (BST) capacitor generates the supply voltage for the high-side MOSFET (HS-FET) driver. An internal trickle-charge circuit maintains a sufficient HS-FET gate driver voltage even at 100% duty cycle. Full protection features include configurable short-circuit protection (SCP), over-current protection (OVP), under-voltage lockout (UVLO) protection, adjustable dead time (DT) control, and thermal shutdown. The MPQ6528 is available in a QFN-28 (4mmx5mm) package with an exposed thermal pad. • • • • • • • • • • • Wide 5V to 60V Input Voltage (VIN) Range Charge Pump Gate Driver Supply Bootstrap (BST) High-Side MOSFET (HSFET) Driver with Trickle-Charge Circuit for 100% Duty Cycle Operation Low-Power Sleep Mode Configurable Short-Circuit Protection (SCP) Over-Current Protection (OCP) Under-Voltage Lockout (UVLO) Protection Adjustable Dead Time (DT) Control to Prevent Shoot-Through Thermal Shutdown Fault Indication Output Thermally Enhanced Surface-Mount Package Available in a QFN-28 (4mmx5mm) Package Available in a Wettable Flank Package Available in AEC-Q100 Grade 1 APPLICATIONS • • • • • Brushed DC Motors Automotive Actuators Gate Openers Audio Amplifiers Power Converters All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. MPQ6528 Rev. 1.0 MonolithicPower.com 9/8/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 1 MPQ6528 – 5V TO 60V, H-BRIDGE GATE DRIVER, AEC-Q100 QUALIFIED TYPICAL APPLICATION CPA 0.47µF DT CPB RDEAD VIN VREG MPQ6528 VIN 10µF nFAULT CIN OC_REF BSTA 0.1µF nSLEEP ENA ENB GHA SHA DCM To Phase B GLA PWMA PWMB LSS Phase A (Repeat for B) GND MPQ6528 Rev. 1.0 MonolithicPower.com 9/8/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 2 MPQ6528 – 5V TO 60V, H-BRIDGE GATE DRIVER, AEC-Q100 QUALIFIED ORDERING INFORMATION Part Number MPQ6528GVE-AEC1* Package QFN-28 (4mmx5mm) Top Marking See Below MSL Rating 2 * For Tape & Reel, add suffix -Z (e.g. MPQ6528GVE-AEC1-Z). TOP MARKING MPS: MPS prefix Y: Year code WW: Week code MP6528: Part number LLLLLL: Lot number E: Wettable flank PACKAGE REFERENCE GND DT OC_REF nSLEEP nFAULT ENA 28 27 26 25 24 23 TOP VIEW VIN 1 22 GND CPA 2 21 ENB CPB 3 20 PWMA VREG 4 19 GND BSTA 5 18 PWMB SHA 6 17 LSS GHA 7 16 GLB GLA 8 15 GHB 9 10 11 12 13 14 NC NC NC NC BSTB SHB The exposed pad on the back side is connected to GND. MPQ6528 QFN-28 (4mmx5mm) MPQ6528 Rev. 1.0 MonolithicPower.com 9/8/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 3 MPQ6528 – 5V TO 60V, H-BRIDGE GATE DRIVER, AEC-Q100 QUALIFIED PIN FUNCTIONS Pin # Name 1 VIN 2 3 4 CPA CPB VREG 5 BSTA 6 7 8 9, 10, 11, 12 SHA GHA GLA 13 BSTB 14 15 16 17 SHB GHB GLB LSS 18 PWMB 19, 22, 28 GND 20 21 23 24 25 26 27 NC Description Input supply voltage. Use a ceramic capacitor to bypass the VIN pin to ground. Additional bulk capacitors may be required. (1) Charge pump capacitor. Connect a ceramic capacitor between the CPA and CPB pins. (1) Charge pump capacitor connection terminal. Gate driver output. Connect a ceramic capacitor between the VREG pin and ground. (1) Phase A bootstrap (BST). Connect a ceramic capacitor between the BSTA and SHA pins. (1) Phase A high-side MOSFET (HS-FET) source connection. Phase A HS-FET gate driver. Phase A low-side MOSFET (LS-FET) gate driver. No connection. Phase B bootstrap (BST). Connect a ceramic capacitor between the BSTB and SHB pins. (1) Phase B HS-FET source connection. Phase B HS-FET gate driver. Phase B LS-FET gate driver. Phase A and phase B LS-FETs source connection. Phase B pulse-width modulation (PWM) input. Pull the PWMB pin high to drive phase B high; pull PWMB low to drive phase B low. PWMB has an internal pull-down resistor. Ground. Phase A PWM input. Pull the PWMA pin high to drive phase A high; pull PWMA low to drive phase A low. PWMA has an internal pull-down resistor. Phase B Enable (EN). Pull the ENB pin high to turn the gate driver on for phase B; pull ENB ENB low to turn the gate driver off for phase B. ENB has an internal pull-down resistor. Phase A Enable (EN). Pull the ENA pin high to turn the gate driver on for phase A; pull ENA ENA low to turn the gate driver off for phase A. ENA has an internal pull-down resistor. Fault indicator. The nFAULT pin is an open-drain output. If a fault occurs, nFAULT is nFAULT pulled low. Sleep mode input. Pull the nSLEEP pin low to enter low-power sleep mode; pull nSLEEP nSLEEP high to exit sleep mode. nSLEEP has an internal pull-down resistor. OC_REF Over-current protection (OCP) reference voltage (VREF) input. DT Dead time (DT) setting. Connect a resistor to ground to set the dead time (DT). (1) PWMA Note: 1) For more information, see the Application Information section on page 14. MPQ6528 Rev. 1.0 MonolithicPower.com 9/8/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 4 MPQ6528 – 5V TO 60V, H-BRIDGE GATE DRIVER, AEC-Q100 QUALIFIED θJA θJC ABSOLUTE MAXIMUM RATINGS (2) Thermal Resistance (5) Input voltage (VIN) ........................ -0.3V to +62V CPA ............................................. -0.3V to +55V CPB .......................................... -0.3V to +12.5V CPB (transient,