MPQ6626GF-AEC1-Z

MPQ6626 40V, 0.8A, Hex Half-Bridge Motor Driver with Serial Input Control, AEC-Q100 Qualified DESCRIPTION FEATURES The MPQ6626 is a 6-channel half-bridge DMOS output driver with integrated power MOSFETs. The input voltage ranges from 5.5V to 40V, with the up to 0.8A output current capability.   The six half-bridges of the MPQ6626 can be controlled separately via a standard serial data interface, and have various diagnostic functions. The device has very low quiescent current in standby mode. Full protections include short-circuit protection (SCP), under-voltage protection (UVP), and thermal shutdown. The MPQ6626 requires a minimal number of readily available, standard external components. It is available in a TSSOP-28 EP package.             Wide 5.5V to 40V Operating Input Range High-Side and Low-Side Drivers Connected in Half-Bridge Configurations Up to 0.8A Output Current Typical 1.3Ω RDS(ON) (HS + LS) Very Low Quiescent Current in Standby Mode versus Total Temperature Range Outputs are Short-Circuit Protected Over-Temperature Protection and PreWarning Under-Voltage Lockout (UVLO) and OverVoltage Lockout (OVLO) Serial Data Interface Diagnostic Functions Include: Shorted Output, Open Load, Over-Temperature (OT), Over-Voltage (OV), and UnderVoltage (UV) Serial Interface Clock Frequency Up to 5MHz Supports 3.3V and 5V Systems Available in a TSSOP-28 EP Package Available in AEC-Q100 Grade 1 APPLICATIONS   Automotive and Industrial Applications DC Motors All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 1 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 TYPICAL APPLICATION VS VBATT VS CS OUT1 DI MCU M CLK OUT2 DO OUT3 EN M OUT4 OUT5 VCC M VCC OUT6 GND MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 2 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 ORDERING INFORMATION Part Number* MPQ6626GF-AEC1 Package TSSOP-28 EP Top Marking See Below MSL Rating 2A * For Tape & Reel, add suffix -Z (e.g. MPQ6626GF-AEC1-Z). TOP MARKING MPS: MPS prefix YY: Year code WW: Week code MP6626: Part number LLLLLLLLL: Lot number PACKAGE REFERENCE NC NC GND GND OUT1 OUT2 OUT5 NC NC VS1 DI CLK VCC DO Exposed Pad On Bottom CS TEST EN TEST NC VS2 OUT6 NC OUT4 OUT3 GND GND NC NC TSSOP-28 EP MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 3 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 PIN FUNCTIONS Pin # Name 1, 5, 10, 14, 15, 18, 25, 28 2, 13, 16, 27 3 4 6 7 GND OUT1 OUT5 DI VCC 8 DO 9 EN 11 12 17 19 20, 21 22 OUT6 OUT4 OUT3 VS2 TEST CS 23 CLK 24 VS1 26 OUT2 NC Description No connection. Ground. Half-bridge output 1. Half-bridge output 5. Serial data input. Logic supply voltage Serial data output. Enable pin. Pull this pin low to set the MPQ6626 to standby mode; pull it high to set the MPQ6626 to normal operation. Half-bridge output 6. Half-bridge output 4. Half-bridge output 3. Power supply for drivers 3, 4 and 6. Connect this pin to VS1 externally. Test pin for internal use. Connect this pin to ground. Chip select input, active low. Serial clock input. Power supply for drivers 1, 2 and 5, all pre−drivers, and the charge pump. Connect this pin to VS2 externally. Half-bridge output 2. MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 4 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 θJA θJC ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (5) Supply voltage (VVS) ....................................45V VOUTx .................................... -0.3V to VVS + 0.3V Logic supply voltage (VVCC) ............ -0.3V to +6V Logic input voltage ............... -0.3 to VVCC + 0.3V Logic output voltage............. -0.3 to VVCC + 0.3V All other pins ............................... -0.3V to +6.5V Continuous power dissipation (TA = 25°C) (2) ...... TSSOP-28EP ............................................3.9W Junction temperature ............................... 150°C Lead temperature .................................... 260°C Storage temperature ................ -65°C to +150°C TSSOP-28EP….….….….….….32…....6….°C/W ESD Ratings (3) Human body model (OUTx and VSx) ........... 4kV Human body model (all other pins) .............. 2kV Machine mode (MM) ..................................200V Charge device model (CDM)......................750V Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ (MAX), the junction-toambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX) - TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Devices are ESD-sensitive. It is recommended to handle them with caution. 4) The device is not guaranteed to function outside of its operating conditions. 5) Measured on JESD51-7, 4-layer PCB. Recommended Operating Conditions (4) Supply voltage (VVS) ....................... 5.5V to 40V Logic supply voltage (VVCC) ........ 3.15V to 5.25V Operating junction temp (TJ) .... -40°C to +150°C MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 5 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 ELECTRICAL CHARACTERISTICS 5.5V ≤ VVS ≤ 40V, 3.15V ≤ VVCC ≤ 5.25V, EN = VVCC, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units Operating supply current (VS) IVSO VVS < 28V, EN = VCC, no load 5.5 6.5 mA Operating supply current (VCC) IVCCO 3.15V < VVCC < 5.25V, EN = high, DI = CLK = ;ow, CS = high, no load 100 150 μA Quiescent current (VS) IVSQ VVS = 13.2V, VVCC = 0V or VVCC = 5V, EN = low 1 5 μA Quiescent current (VCC) IVCCQ 3.15V < VVCC < 5.25V, EN = low, DI = CLK = low, CS = high 1 5 μA Discharge current (VSx) IVS Power-on reset threshold VVCC Power-on reset delay VS under-voltage lockout threshold VS under-voltage lockout threshold hysteresis VS under-voltage lockout delay time VUVOFF VS over-voltage lockout threshold VOVOFF VVS VVS = 40V, EN = low 3 mA VCC increasing 2.3 2.7 3 V After switching on VVCC 30 100 160 μs VS decreasing 3.5 4.5 V 0.5 V 21 ms 0.1 7 OVLO = 1, VS increasing VS over-voltage lockout threshold hysteresis Output specification HS + LS switch on resistance Over-current limit RDS(ON) tDOC Open load detection current IOLD Open load delay time Output enable time Output disable time tDOLD Output rise time Output fall time 33 36 39 V 1 2.5 4 V 1.3 2.2 2.8 Ω Ω 1 1.3 2.5 A 10 25 50 μs 1 16 45 mA 200 350 50 50 600 65 65 μs 75 105 μs 65 95 27 20 42 27 TJ = -40°C to +125°C TJ = 150°C IOCP Over-current shutdown delay time Delay time 0.3 VVS = 13.2V VVS = 13.2V, LS switch on VVS = 13.2V, RLOAD = 50Ω HBCNFx high to OUTx high VVS = 13.2V, RLOAD = 50Ω HBCNFx low to OUTx low VVS = 13.2V, RLOAD = 50Ω VVS =13.2V, 10% to 90% VOUT, RLOAD = 50Ω 13 11 MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. μs 6 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 ELECTRICAL CHARACTERISTICS (continued) 5.5V ≤ VVS ≤ 40V, 3.15V ≤ VVCC ≤ 5.25V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol Condition VVS = 13V, RLOAD = 50Ω Dead time EN Input EN low-level threshold EN high-level threshold EN threshold hysteresis Pull-down resistor Serial Interface: Logic Inputs DI, CLK, CS Typ 0.6 V V V kΩ 0.6 V V 0.4 125 VEN = VVCC 2.0 150 125 125 VDI, VCLK = VVCC VCS = 0V CIN 15 mV kΩ kΩ pF 0.4 V VVCC 0.6 High-level output Leakage current (tri-state) Thermal Shutdown and Pre-Warning (6) 0V < VDO < VVCC, VCS = VVCC V -5 TJW 120 TJSD 150 1.05 Units μs 1.5 Low-level output Thermal pre-warning threshold Thermal pre-warning hysteresis Thermal shutdown threshold Thermal shutdown hysteresis Ratio thermal shutdown/thermal pre-warning Max 2.0 Input low-level threshold Input high-level threshold Input threshold hysteresis Pull-down resistor of DI, CLK pin Pull-up current of CS pin Input capacitance (6) Serial Interface: Logic Output DO Min 140 20 175 20 +5 μA 170 °C °C °C °C 200 1.2 MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 7 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 SERIAL INTERFACE TIMING CHARACTERISTICS (6) 5.5V < VVS < 40V, 3.15V ≤ VVCC ≤ 5.25V, TJ = -40°C to +125°C, unless otherwise noted. Parameters Symbol CLK frequency fCLK CLK period time tPCLK Condition Min VCC = 5V 200 VCC = 3.3V CLK high time CLK low time CLK set-up time (high to low) CLK set-up time (low to high) DI set-up time DI hold time t5 t6 t7 t3 t11 t12 500 85 85 85 85 50 50 CS set-up time (low to high) CS set-up time (high to low) CS high time DO enable after CS falling edge DO disable after CS rising edge DO falling/rising time DO valid time t8 t4 t9 100 100 5 EN low valid time Typ Max Units 5 MHz ns ns ns ns ns ns ns ns ns μs t1 CDO = 40pF 200 ns t2 CDO = 40pF 200 ns 25 50 ns ns t10 CDO = 40pF CDO = 40pF VCC = 5V, EN high to low (50%) to OUTx turning off (50%) 10 20 EN high to SPI valid Time between two consecutive SRR commands μs 50 100 100 μs μs Note: 6) Not tested in production. Specified by design. MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 8 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 SERIAL INTERFACE TIMING DIAGRAM 1 2 CS DO 9 CS 4 7 CLK 5 3 8 6 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High Level = 0.7 x V CC, Low Level = 0.3 x VCC Output DO: High Level = 0.8 x VCC, Low Level = 0.2 x VCC MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 9 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS VVS = 13V, VVCC = 3.3V, TA = 25°C, unless otherwise noted. Start-Up through VS Shutdown through VS HS on, IOUT = 800mA HS on, IOUT = 800mA CH1: VOUT CH1: VOUT CH2: VVS CH2: VVS CH4: IOUT CH4: IOUT Start-Up through VS Shutdown through VS LS on, IOUT = 800mA LS on, IOUT = 800mA CH1: VOUT CH1: VOUT CH2: VVS CH2: VVS CH4: IOUT CH4: IOUT SCP SCP OUT short to GND OUT short to VVS CH1: VOUT1 CH1: VOUT1 CH4: IOUT CH4: IOUT MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 10 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) VVS = 13V, VVCC = 3.3V, TA = 25°C, unless otherwise noted. SCP Two outputs short circuit CH1: VOUT1 CH2: VOUT2 CH4: IOUT MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 11 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 FUNCTIONAL BLOCK DIAGRAM Charge Pump GH1 GH2 DI CLK . . . HS Gate Driver CS Serial Interface GH5 GH6 Control Logic VS1/VS2 GL1 GL2 DO EN . . . LS Gate Driver GL5 GL6 VS1 VS2 GH1 GH2 GH3 GH4 GH5 GH6 OUT1 OUT2 OUT3 VCC Power-On Reset OUT4 OUT5 OUT6 Fault Handling GND UVLO and OVLO OverCurrent and Under-Load Thermal Warning and Shutdown GL1 GL2 GL3 GL4 GL5 GL6 GND Figure 1: Functional Block Diagram MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 12 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 OPERATION The MPQ6626 is a 6-channel half-bridge DMOS output driver with integrated power MOSFETs. The six half-bridges of the MPQ6626 can be controlled separately from a standard serial data interface, and have various diagnostic functions. falling edge of CS. In addition to the 16-bit status data, a pseudo-bit (PRE_15) can also be retrieved from the DO output. The latched thermal shutdown (TSD) status bit (PRE_15) is available on DO until the first rising CLK edge after CS goes low. DO changes its state with the rising edge of CLK, and remains stable until the next rising edge of CLK. When CS is high, the DO pin is in a tri-state condition. Serial Interface Data transfer starts with the falling edge of the CS signal. Execution of new input data is enabled on the rising edge of the CS signal. Data must appear when the DI pin is synchronized to the CLK pin. Then the data is accepted on the falling edge of the CLK signal. For DI, the MSB (SRR, bit[15]) has to be transferred first. The last 16 bits clocked into DI are transferred to the device’s data register if there no frame error. Otherwise, all DI data is ignored, and the previous input data is preserved. The following conditions must be met for a valid TSD read to be captured:    CLK and DI are low before the CS cycle CS transitions from high to low CS set-up time is satisfied Figure 2 shows the SPI communication. Table 1 lists the input control registers. Table 2 lists the output diagnostic registers. The output data at the DO pin is enabled on the CS DI 15 CLK DO DO 15 PRE_15 15 14 14 14 13 13 13 12 12 11 11 12 10 10 11 9 9 10 8 8 9 7 7 8 6 6 7 5 5 6 4 4 5 3 3 4 2 2 3 1 1 2 0 0 1 0 Figure 2: Data Transfer Table 1: Input Control Registers Input Data (7) Bit Input Register Function This bit resets the status register. 15 SRR 14 CH_SEL (8) CH_SEL = 0. OLSD_EN This bit enables open load detection shutdown (OLD_SD) for half-bridges 1–6. This feature allows the affected output stage to be switched off if a true open load or under-load condition has been detected. 13 1: Reset. The errors bits of the corresponding status register in the output data register are set to low 1: Enabled Enables half-bridge 6. 12 HBEN6 11 HBEN5 1: Half-bridge 6 is active 0: Half-bridge 6 is in Hi-Z Enables half-bridge 5. 1: Half-bridge 5 is active 0: Half-bridge 5 is in Hi-Z MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 13 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 Enables half-bridge 4. 10 HBEN4 1: Half-bridge 4 is active 0: Half-bridge 4 is in Hi-Z Enables half-bridge 3. 9 HBEN3 1: Half-bridge 3 is active 0: Half-bridge 3 is in Hi-Z Enables half-bridge 2. 8 HBEN2 1: Half-bridge 2 is active 0: Half-bridge 2 is in Hi-Z Enables half-bridge 1. 7 HBEN1 1: Half-bridge 1 is active 0: Half-bridge 1 is in Hi-Z Configures half-bridge 6. 6 HBCNF6 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Configures half-bridge 5. 5 HBCNF5 4 HBCNF4 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Configures half-bridge 4. 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Configures half-bridge 3. 3 HBCNF3 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Configures half-bridge 2. 2 HBCNF2 1 HBCNF1 0 OVLO 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Configures half-bridge 1. 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on This bit enables VSx over-voltage lockout (OVLO). 1: Enabled Note: 7) 8) All input bits are set to 0 after a VCC power-on reset. CH_SEL enables bridge selection for the MPQ6527 and MPQ6628 devices. It is recommended to set the MPQ6626’s CH_SEL bit to 0. MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 14 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 Table 2: Output Diagnostic Registers Output Data Bit PRE_15 Input Register TSD Function This bit indicates if latched thermal shutdown occurs. The error is latched and the corresponding output is switched off if thermal shutdown occurs. The bit can only be reset via SRR or a power-on reset. 1: Thermal shutdown has occurred 15 OC This bit indicates if latched over-current (OC) shutdown occurs. If an OC fault (e.g. an overload or short-circuit fault) is detected on any half-bridge between half-bridge 1 and half-bridge 6, the error is latched, and the corresponding output is switched off. The bit can only be reset via SRR or a power-on reset. 1: An OC fault has occurred 14 PSF This bit indicates if a power supply failure occurs. This bit is set if there is an overvoltage or under-voltage condition on VS1 or VS2, and all outputs switch off. This bit automatically resets if VSx returns to its normal operating range. 1: A power supply failure has occurred 13 OLD This bit indicates if an open load fault has occurred. If there is a true open load or under-load condition on any half-bridge between half-bridge 1 and half-bridge 6, the error is latched. The corresponding output is switched off if input bit[13] (OLD_SD) is high. The bit can only be reset via SRR or a power-on reset. 1: An open load fault has occurred Half-bridge 6 output status. 12 SHBEN6 11 SHBEN5 10 SHBEN4 1: Half-bridge 6 is active 0: Half-bridge 6 is in Hi-Z Half-bridge 5 output status. 1: Half-bridge 5 is active 0: Half-bridge 5 is in Hi-Z Half-bridge 4 output status. 1: Half-bridge 4 is active 0: Half-bridge 4 is in Hi-Z Half-bridge 3 output status. 9 SHBEN3 8 SHBEN2 1: Half-bridge 3 is active 0: Half-bridge 3 is in Hi-Z Half-bridge 2 output status. 1: Half-bridge 3 is active 0: Half-bridge 2 is in Hi-Z Half-bridge 1 output status. 7 SHBEN1 6 HBCNF6 1: Half-bridge 1 is active 0: Half-bridge 1 is in Hi-Z Half-bridge 6 configuration status. 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 15 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 Half-bridge 5 configuration status. 5 HBCNF5 4 HBCNF4 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Half-bridge 4 configuration status. 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Half-bridge 3 configuration status. 3 HBCNF3 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Half-bridge 2 configuration status. 2 HBCNF2 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on Half-bridge 1 configuration status. 1 0 HBCNF1 TW 1: The high-side (HS) half-bridge is on, and the low-side (LS) half-bridge is off 0: The HS half-bridge is off, and the LS half-bridge is on This bit indicates if a thermal warning has been detected. This bit is treated as an early warning, and is set high if the junction temperature reaches T JW. The output remains on until one or more sensors reach TSD. This bit automatically resets if the junction temperature drops below the thermal warning recovery point. 1: A thermal warning has been detected Enable Control (EN) The MPQ6626 enters low-power mode (or sleep mode) when the EN pin is pulled low. The EN input has an internal pull-down resistor. In sleep mode, all output stages turn off, and the SPI register banks are reset. The output stages can be activated again by pulling EN high. Status Register Reset (SRR) The status register reset (SRR) command bit is executed at the end of the SPI transmission (CS low to high). Sending SRR = 1 clears the status memory and reactivates faulted outputs for channels. If a fault is still present when SRR is sent, the protection can be triggered, and the device may shutdown again. The device can be reset by toggling the EN pin or by a VCC power-on reset. Open Load Detection While the device is on, open load detection (OLD) is implemented in the low-side (LS) switches of the bridge outputs. If the current through the LS transistor is below the reference current (IOLD) for longer than the OLD delay time (tDOLD), the corresponding OLD diagnostic bit is set. If an under-load condition occurs in another channel after the global timer has started, the delay for any subsequent under-load condition is the remainder of the timer. The timer runs continuously if the under-load condition remains. If the OLSD_EN bit is set, and an open load is detected on the LS switch, the respective output is disabled, and the open load error bit is latched. Otherwise, the output remains on, and only the open load error bit is set. If OLSD_EN is set, the error remains latched, and the output stays off until an SRR or power-on reset is performed. For example, consider a motor that is connected between outputs OUT1 and OUT2 with a broken wire (see Figure 3). Table 3 shows the corresponding diagnostic information. Open Load OUT1 M OUT2 Figure 3: Half-Bridge Open Load Example MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 16 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 Table 3: Open Load Diagnostic Example Control LS1 0 1 0 0 1 HS1 0 0 1 1 0 LS2 0 0 1 0 1 HS2 0 1 0 1 0 In motor applications, it is often advantageous to actively brake the motor by turning on both highside (HS) or low-side (LS) drivers in two halfbridge channels. If the configuration has two LS drivers (LS brake), an under-load condition occurs as the motor current decays normally. Use an HS brake to avoid an under-load notification. Discharge Circuit Many typical applications use an inverse-polarity protection diode, such as D1 in Figure 4. D1 MPQ6626 C1 VBATT VPK Figure 4: Functional Principle of the Discharger Circuit Diagnostic Information Motor Motor Connected Disconnected OLD (Output Bit[13]) 0 0 0 1 0 1 0 0 1 1 However, this method poses certain risks. During inhibit mode, the IC consumes an extremely low current (IVS) that is about 20μA maximum. Any peaks on the supply voltage gradually charge the blocking capacitor. D1 prevents the capacitor from discharging via the power supply. Due to the extremely small quiescent current, discharging via the IC can also be ignored. This means that during long periods in inhibit mode, the IC’s supply voltage could increase continuously, until the device exceeds the maximum supply voltage limit (about 40V). This could damage the IC. The MPQ6626 features a discharger circuit to protect the device. If the VS voltage exceeds its threshold (about 37V), the blocking capacitor is discharged via an integrated resistor until VS falls below the threshold. Diagnostics and Protections Overview Table 4 lists diagnostic protections. Table 4: Diagnostic Classes and Functions Fault Qualifier Thermal Shutdown Over-Current Shutdown OLSD_EN = 1 OLSD_EN = 0 OVLO = 1 OVLO = 0 - Open Load Detection Over-Voltage Lockout Under-Voltage Lockout Thermal Warning OUTx State and Recovery Output Register Hi-Z, use SRR to reset Unaffected Hi-Z, non-latched (9) Unaffected Hi-Z, non-latched (9) Unaffected TSD = 1, use SRR to reset OC = 1, use SRR to reset OLD = 1, use SRR to reset PSF = 1, non-latched (10) TW = 1, non-latched (10) Notes: 9) OUTx returns to its previous state if the fault is removed. 10) The corresponding output register returns to its no-fault state if the fault is removed MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 17 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 Over-Current Protection (OCP) The MPQ6626 has internal overload and shortcircuit protection (SCP). The currents in both the high-side and low-side MOSFETs are measured, and if the current exceeds the current limit, an internal timer starts. If the permanent over-current shutdown delay time (tOC) is reached, the short-circuit detection bit (OC) is set, and the shorted output is disabled. Reset the OC bit and enable the disabled output by writing a high to the SRR bit in the input register. Thermal Shutdown and Pre-Warning Thermal monitoring is integrated into the MPQ6626. Each half-bridge monitors the driver pair’s (one channel including the high-side and low-side MOSFETs) thermal sensor. If the junction temperature rises above the thermal pre-warning threshold, the temperature prewarning bit (TW) in the output register is set. When the temperature falls below the thermal pre-warning threshold, this bit is reset. If the junction temperature rises above the thermal shutdown threshold, the channel’s HS and LS drivers latch off, the TW bit remains set, and the TSD (PRE_15) bit is set. The TSD bit is cleared, and all affected channels in a group resume immediately once the following conditions are met:  The junction temperature falls below the thermal shutdown threshold  A high has been written to the SRR bit in the input register. The thermal pre-warning and thresholds have hysteresis values. VS Under-Voltage Lockout (UVLO) If the voltage on the VS pin falls below the undervoltage lockout (UVLO) threshold, an internal timer starts. The power supply fail bit (PSF) in the output register is set, and all outputs are disabled if the permanent UVLO delay time is reached. Operation resumes immediately when VS rises above the UVLO threshold, and the PSF bit is cleared. VCC Under-Voltage Lockout (UVLO) The SPI interface does not function if VCC is below the under-voltage lockout (UVLO) threshold. If this occurs, all outputs turn off, then the input and status output registers are cleared. Once the VCC voltage rises above the UVLO threshold, the under-voltage event is cleared, and SRR is released. VS Over-Voltage Lockout (OVLO) If the supply voltage on VS rises above the switch off voltage (VOVOFF), all outputs switch off if the over-voltage lockout input bit is set (OVLO = 1), and the PSF error bit is set. The error is not latched. This means that if the VS voltage falls below the switch-on threshold, the power stages restart, and the error flags reset. shutdown MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 18 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 APPLICATION INFORMATION PCB Layout Guidelines PCB layout is critical for the stable operation. For the best results, follow the guidelines below: 1. Place a supply-rated X5R or X7R bypass capacitor as close as possible to the IC. 2. Place as much copper as possible on the long pads. 3. Place thermal vias inside the pad area to dissipate heat to the copper layers. Place vias just outside the pad area if via-in-pad construction is not applicable. 4. Place a bulk capacitor on the VS pin to absorb the energy flowing from the motor or power supply. This capacitor should be sized according to the application requirements. Figure 5: Recommended PCB Layout MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 19 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 PACKAGE INFORMATION TSSOP-28 EP 6.00 TYP 9.60 9.80 0.65 BSC 0.40 TYP 28 15 1.60 TYP 4.30 4.50 PIN 1 ID 3.20 TYP 6.20 6.60 5.80 TYP 14 1 TOP VIEW RECOMMENDED LAND PATTERN 0.80 1.05 1.20 MAX SEATING PLANE 0.19 0.30 0.65 BSC 0.00 0.15 SEE DETAIL "A" FRONT VIEW SIDE VIEW GAUGE PLANE 0.25 BSC 5.40 5.90 0o-8o DETAIL A 2.60 3.10 BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION, OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AET. 6) DRAWING IS NOT TO SCALE. MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 20 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 CARRIER INFORMATION Pin1 1 1 1 1 ABCD ABCD ABCD ABCD Feed Direction Part Number Package Description Quantity/Reel Quantity/Tube Reel Diameter MPQ6626GF-AEC1-Z TSSOP-28EP 2500 50 13in Carrier Tape Width 16mm MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. Carrier Tape Pitch 8mm 21 MPQ6626 – 40V, 0.8A, HEX HALF-BRIDGE DRIVER WITH SERIAL INPUT, AEC-Q100 REVISION HISTORY Revision # 1.0 Revision Date 9/24/2021 Description Pages Updated Initial Release - Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ6626 Rev. 1.0 MonolithicPower.com 9/24/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2021 MPS. All Rights Reserved. 22