MPQ8626
The Future of Analog IC Technology
DESCRIPTION
The MPQ8626 is a fully integrated, highfrequency, synchronous, buck converter. The
MPQ8626 offers a very compact solution that
achieves up to 6A of output current with
excellent load and line regulation over a wide
input supply range. The MPQ8626 operates at
high efficiency over a wide output current load
range.
The
MPQ8626
adopts
an
internally
compensated constant-on-time (COT) control
that provides fast transient response and eases
loop stabilization.
The operating frequency can be set to 600kHz,
1100kHz, or 2000kHz easily with MODE
configuration, allowing the MPQ8626 frequency
to remain constant regardless of the input and
output voltages.
The output voltage start-up ramp is controlled
by an internal 1.5ms timer, which can be
increased by adding a capacitor on TRK/REF.
An open-drain power good (PGOOD) signal
indicates if the output is within its nominal
voltage range. PGOOD is clamped at around
0.7V with an external pull-up voltage when the
input supply fails to power the MPQ8626.
Full protection features include over-current
protection (OCP), over-voltage protection
(OVP), under-voltage protection (UVP), and
over-temperature protection (OTP).
The MPQ8626 requires a minimal number of
readily
available,
standard,
external
components and is available in a QFN-14
(2mmx3mm) package.
FEATURES
Wide Input Voltage Range
o 2.85V to 16V with External 3.3V VCC
Bias
o 4V to 16V with Internal VCC Bias or
External 3.3V VCC Bias
6A Output Current
Programmable Accurate Current Limit Level
Low RDS(ON) Integrated Power MOSFETs
16V, 6A, High Efficiency, Synchronous,
Step-Down Converter with
Adjustable Current Limit
Proprietary Switching Loss Reduction
Technique
Adaptive Constant-On-Time (COT) for
Ultrafast Transient Response
Stable with Zero ESR Output Capacitor
0.5% Reference Voltage Over 0°C to +70°C
Junction Temperature Range
1% Reference Voltage Over -40°C to
+125°C Junction Temperature Range
Selectable Forced CCM or Pulse-Skip
Operation
Excellent Load Regulation
Output Voltage Tracking
Output Voltage Discharge
PGOOD Active Clamped at Low Level
during Power Failure
Programmable Soft-Start Time from 1ms
and Up
Pre-Bias Start-Up
Selectable Switching Frequency from
600kHz, 1100kHz, and 2000kHz
Non-Latch for OCP, OVP, UVP, OTP, and
UVLO
Output Adjustable from 0.6V to 0.9 x VIN Up
to 6V Max
Available in a QFN-14 (2mmx3mm)
Package
APPLICATIONS
Telecom and Networking Systems
Server, Cloud-Computing, Storage
Base Stations
General Purpose Point-of-Load (PoL)
12V Distribution Power Systems
High-end TV
Game Consoles and Graphic Cards
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
MPQ8626 Rev. 1.02
www.MonolithicPower.com
12/12/2018
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1
MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
TYPICAL APPLICATION CIRCUIT
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
ORDERING INFORMATION
Part Number*
MPQ8626GD
Package
QFN-14 (2mmx3mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MPQ8626GD–Z)
TOP MARKING
AWR: Product code of MPQ8626GD
Y: Year code
WW: Week code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-14 (2mmx3mm)
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (6) θJB
Supply voltage (VIN) ..................................... 18V
VSW (DC)............................... -0.3V to VIN + 0.3V
VSW (25ns) (2)...................................... -3V to 25V
VSW (25ns) .......................................... -5V to 25V
VBST........................................................ VSW + 4V
VCC, EN ....................................... -0.3V to 4.5V
All other pins .................................. -0.3V to 4.3V
Junction temperature ................................ 170°C
Lead temperature...................................... 260°C
Storage temperature .................-65°C to +170°C
QNF-14 (2mmx3mm) .......... 6.8 ...... 17.4 ... °C/W
Recommended Operating Conditions (3)
Supply voltage (VIN) ........................... 4V to 16V
VIN(DC) - VSW(DC) (4) ................. -0.3V to VIN + 0.3V
VSW(DC) (5) .............................. -0.3V to VIN + 0.3V
Output voltage (VOUT) ......................... 0.6V to 6V
External VCC bias (VCC_EXT) ......... 3.12V to 3.6V
Maximum output current (IOUT_MAX) ................. 6A
Maximum output current limit (IOC_MAX) ........... 8A
Maximum peak inductor current (IL_PEAK) ...... 10A
EN voltage (VEN) .......................................... 3.6V
Operating junction temp. (TJ). ...-40°C to +125°C
θJC_TOP
NOTES:
1) Exceeding these ratings may damage the device.
2) Measured by using a differential oscilloscope probe.
3) The device is not guaranteed to function outside of its
operating conditions.
4) The voltage rating can be in the range of -5V to 24V for a
period of 25ns or less with a maximum repetition rate of 2MHz
when the input voltage is 16V.
5) The voltage rating can be in the range of -3V to 24V for a
period of 25ns or less with a maximum repetition rate of 2MHz
when the input voltage is 16V.
6) θJB is the thermal resistance from the junction to the board
around the PGND soldering point.
θJC_TOP is the thermal resistance from the junction to the top of
the package.
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to 125°C, unless otherwise noted.
Parameters
VIN Supply Current
Supply current (shutdown)
Supply current (quiescent)
MOSFET
Switch leakage
HS on-state resistance
LS on-state resistance
Current Limit
Current limit threshold
ICS to IOUT ratio
Low-side negative current limit
Negative current limit time-out (7)
Timer
Switching frequency (8)
Symbol
Condition
Min
Typ
Max
Units
IIN
IIN
VEN = 0V
VEN = 2V, VFB = 0.7V
0
650
10
850
μA
μA
SWLKG_HS
SWLKG_LS
RDS_ON_HS
RDS_ON_HS
VEN = 0V, VSW = 0V
VEN = 0V, VSW = 12V
VEN = 2V @ 25°C
VEN = 2V @ 25°C
0
0
22.6
8.1
10
30
μA
1.15
36
1.2
40
-8
80
1.25
44
V
μA/A
A
ns
530
935
1870
660
1100
2200
790
1265
2530
50
180
kHz
kHz
kHz
ns
ns
113%
77%
116%
80%
119%
83%
VREF
VREF
594
597
600
600
15
6
2.2
606
603
mV
mV
μA
μA
ms
-3
0
50
3
100
mV
nA
1.17
1.22
200
0
1.27
V
mV
μA
VLIM
ICS/IOUT
IOUT ≥ 2A
ILIM_NEG_10
tNCL_Timer
fSW
Minimum on time (7)
TON_MIN
Minimum off time (7)
TOFF_MIN
VFB = 1000mV
Over-Voltage (OVP) and Under-Voltage Protection (UVP)
OVP threshold
VOVP
UVP threshold
VUVP
Feedback Voltage and Soft Start (SS)
TJ = -40°C to +125°C
Feedback voltage
VREF
TJ = 0°C to +70°C
TRK/REF sourcing current
ITRACK_Source VTRK/REF = 0V
TRK/REF sinking current
ITRACK_Sink
VTRK/REF = 0.7V
Soft-start time
tSS
CTRACK = 1nF
Error Amplifier (EA)
Error amplifier offset
VOS
Feedback current
IFB
VFB = REF
Enable (EN)
Enable input rising threshold
VIHEN
Enable hysteresis
VEN-HYS
Enable input current
IEN
VEN = 2V
Soft shutdown discharge
RON_DISCH
MOSFET
VIN UVLO
VIN under-voltage lockout
VINVth-Rise
threshold rising
VCC = 3.3V
VIN under-voltage lockout
VINVth-Fall
threshold falling
VCC Regulator
VCC under-voltage lockout
VCCVth_Rise
threshold rising
VCC under-voltage lockout
VCCVth_Fall
threshold falling
VCC output voltage
VCC
VCC load regulation
ICC = 25mA
1.6
mΩ
mΩ
80
Ω
2.25
2.55
2.85
V
1.7
2
2.3
V
2.65
2.8
2.95
V
2.35
2.5
2.65
V
2.88
3.00
0.5
3.12
V
%
MPQ8626 Rev. 1.02
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12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Power Good (PGOOD)
Power good high threshold
Power good low threshold
Power good low-to-high delay
Power good sink current
capability
Power good leakage current
Power good low-level output
voltage
Symbol
PGVth_Hi_Rise
PGVth_Lo_Rise
PGVth_Lo_Fall
PGTd
VPG
IPG_LEAK
VOL_100
VOL_10
Thermal Protection (OTP)
OTP shutdown (7)
OTP shutdown hysteresis (7)
Condition
FB from low to high
FB from low to high
FB from high to low
TJ = 25°C
Min
Typ
Max
Units
89.5%
113%
77%
0.7
92.5%
116%
80%
1
95.5%
119%
83%
1.3
VREF
VREF
VREF
ms
0.4
V
3
µA
IPG = 10mA
VPG = 3V
VIN = 0V, pull PGOOD up to
3.3V through a 100kΩ
resistor
VIN = 0V, pull PGOOD up to
3.3V through a 10kΩ resistor
TSD
TSD_Hys
650
850
mV
800
150
160
20
1000
°C
°C
NOTES:
7) Specified by design and characterization, not tested in production.
8) Specified by design.
MPQ8626 Rev. 1.02
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12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.8V, L = 1µH, TA = +25°C, unless otherwise noted.
Load Regulation
95
95
90
90
1100kHz
85
80
0.8
0.6
1100kHz
85
80
600kHz
Forced CCM
0.2
600kHz
0.0
75
-0.2
70
70
-0.4 Pulse Skip
-0.6
60
65
2000kHz
0
1
2
3
4
5
OUTPUT CURRENT (A)
60
6
Switching Frequency vs.
Output Current
2400
Forced CCM
2000kHz
0
-0.8
1
2
3
4
5
OUTPUT CURRENT (A)
6
2000kHz
Efficiency
1.1MHz
100
40
1100kHz
1200
VOUT=5V
600kHz
1
2
3
4
5
OUTPUT CURRENT (A)
20
0
6
2750
2750
2500
FREQUENCY (kHz)
2500
2MHz
2000
1750
1.1MHz
1250
600kHz
2
3
4
5
6
70
0
1
2
3
4
IOUT (A)
5
6
2250
VIN = 12V, Load = 2A
2MHz
2000
1750
1500
1.1MHz
1250
1000
600kHz
750
750
500
1
VOUT=0.9V
Switching Frequency vs.
Output Voltage
V
= 1.8V, Load = 2A
3000 OUT
1000
75
VOUT=0.9V
IOUT (A)
Switching Frequency vs.
Input Voltage
1500
80
VOUT=2.5V
25
VOUT=2.5V
85
30
600
2250
VOUT=5V
90
35
1000
400
0
6
95
45
1600
800
1
2
3
4
5
OUTPUT CURRENT (A)
50
1800
1400
0
1.1MHz, No air-flow
55
2000
-1.0
Thermal Results
60
2200
FREQUENCY (kHz)
0.4
75
65
FREQUENCY (kHz)
1.0
4
6
8
10
12
14
INPUT VOLTAGE (V)
16
500
1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT VOLTAGE (V)
MPQ8626 Rev. 1.02
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12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.8V, L = 1µH, TA = +25°C, unless otherwise noted.
MPQ8626 Rev. 1.02
www.MonolithicPower.com
12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.8V, L = 1µH, TA = +25°C, unless otherwise noted.
MPQ8626 Rev. 1.02
www.MonolithicPower.com
12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.8V, L = 1µH, TA = +25°C, unless otherwise noted.
MPQ8626 Rev. 1.02
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12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
PIN FUNCTIONS
PIN #
Name
1, 14
PGND
2, 11
SW
3
VIN
4
CS
5
EN
6
FB
7
AGND
8
TRK/REF
9
PGOOD
10
BST
12
MODE
13
VCC
Description
System ground. PGND is the reference ground of the regulated output voltage.
PGND requires careful consideration during PCB layout. Connect PGND using wide
PCB traces.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven
up to VIN by the high-side switch during the on-time of the PWM duty cycle. The
inductor current drives SW low during the off-time. Connect SW using wide PCB
traces.
Input voltage. VIN supplies power to the internal MOSFET and regulator. Input
capacitors are needed to decouple the input rail. Connect VIN using wide PCB
traces.
Current limit. Connect a resistor from CS to ground to set the current limit trip
point. See Table 2 for additional details.
Enable. EN is an input signal that turns the regulator on or off. Drive EN high to turn
on the regulator; drive EN low to turn off the regulator. Connect EN to VIN through a
pull-up resistor or a resistive voltage divider for automatic start-up. Do not float EN.
Feedback. An external resistor divider from the output to AGND tapped to FB sets
the output voltage. It is recommended to place the resistor divider as close to FB as
possible. Vias should be avoided on the FB traces.
Analog ground. Select AGND as the control circuit reference point.
External tracking voltage input. The output voltage tracks this input signal.
Decouple TRK/REF with a ceramic capacitor placed as close to it as possible.
Ceramic capacitors with X7R or X5R grade dielectrics are recommended for their
stable temperature characteristics. The capacitance of this capacitor determines the
soft-start time. See Equation 2 and 3 for additional details.
Power good output. PGOOD is an open-drain signal. A pull-up resistor connected
to a DC voltage is required to indicate a logic high signal if the output voltage is
within regulation. There is a delay of about 1ms from the time FB is greater than or
equal to 92.5% and PGOOD pulling high.
Bootstrap. Connect a capacitor between SW and BS to form a floating supply
across the high-side switch driver.
Operation mode selection. Program MODE to select CCM, pulse-skip mode, or
the operating switching frequency. See Table 1 for additional details.
Internal 3V LDO output. The driver and control circuits are powered from VCC.
Decouple VCC with a minimum 1µF ceramic capacitor as close to it as possible.
Ceramic capacitors with X7R or X5R grade dielectrics are recommended for their
stable temperature characteristics.
MPQ8626 Rev. 1.02
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12/12/2018
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
OPERATION
Constant-On-Time (COT) Control
The MPQ8626 employs constant-on-time (COT)
control to achieve fast load transient response.
Figure 2 shows the details of the control stage
of the MPQ8626.
A dead short occurs between VIN and PGND if
both the HS-FET and the LS-FET are turned on
at the same time. This is called a shoot-through.
To avoid shoot-through, a dead time (DT) is
generated internally between the HS-FET off
and the LS-FET on period or the LS-FET off
and the HS-FET on period.
The operational amplifier (AMP) corrects any
error voltage between FB and REF. The
MPQ8626 can use AMP to provide excellent
load regulation over the entire load range,
whether it is operating in forced continuous
conduction mode (CCM) or pulse-skip mode.
The MPQ8626 has internal ramp compensation
to support low ESR MLCC output capacitor
solutions. The adaptive internal ramp is
optimized so that the MPQ8626 is stable in the
entire operating input/output voltage range with
a proper design of the output L/C filter.
Figure 3: Heavy-Load Operation (PWM)
Figure 2: COT Control
Pulse-Width Modulation (PWM) Operation
Figure 3 shows how the pulse-width modulation
(PWM) signal is generated. AMP corrects any
error between FB and REF and generates a
fairly smooth DC voltage (COMP). The internal
ramp is superimposed onto COMP. The
superimposed COMP is compared with the FB
signal. Whenever FB drops below the
superimposed COMP, the integrated high-side
MOSFET (HS-FET) is turned on and remains
on for a fixed turn-on time. The fixed on time is
determined by the input voltage, output voltage,
and selected switching frequency. After the on
period elapses, the HS-FET turns off. The HSFET turns on again when FB drops below the
superimposed COMP. By repeating this
operation, the MPQ8626 regulates the output
voltage. The integrated low-side MOSFET (LSFET) turns on when the HS-FET is in its off
state to minimize conduction loss.
Continuous
Conduction
Mode
(CCM)
Operation
Continuous conduction mode (CCM) occurs
when the output current is high and the inductor
current is always above zero amps (see Figure
3). The MPQ8626 can also be configured to
operate in forced CCM operation when the
output current is low. See the MODE Selection
section on page 14 for details.
In CCM operation, the switching frequency is
fairly constant (PWM mode), so the output
ripple remains almost constant throughout the
entire load range.
Pulse-Skip Operation (PSM)
At light-load condition, the MPQ8626 can be
configured to work in pulse-skip mode (PSM) to
optimize efficiency. When the load decreases,
the inductor current decreases as well. Once
the inductor current reaches zero, the
MPQ8626 transitions from CCM to PSM if the
MPQ8626 is configured in this way. See the
MODE Selection section on page 14 for details.
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
Figure 4 shows PSM operation at light-load
condition. When FB drops below the
superimposed COMP, the HS-FET turns on for
a fixed interval. When the HS-FET turns off, the
LS-FET turns on until the inductor current
reaches zero. In PSM operation, FB does not
reach the superimposed COMP when the
inductor current approaches zero. The LS-FET
driver turns into tri-state (Hi-Z) when the
inductor current reaches zero. A current
modulator takes over the control of the LS-FET
and limits the inductor current to less than
-1mA. Therefore, the output capacitors
discharge slowly to PGND through the LS-FET.
In light-load condition, the HS-FET is not turned
on as frequently in PSM as it is in forced CCM.
As a result, the efficiency in PSM is improved
greatly compared to that in forced CCM
operation.
The MPQ8626 enters PWM mode once the
output current exceeds the critical level.
Afterward, the switching frequency remains
fairly constant over the output current range.
The MPQ8626 can be configured to operate in
forced CCM, even in light-load condition (see
Table 1).
MODE Selection
The MPQ8626 provides both forced CCM
operation and pulse-skip operation in light-load
condition. The MPQ8626 has three options for
switching frequency: 600kHz, 1100kHz, and
2000kHz. Selecting the operation mode under
light-load condition and the switching frequency
is done by choosing the resistance value of the
resistor connected between MODE and AGND
or VCC (see Table 1).
Table 1: MODE Selection
MODE
AGND
30.1kΩ (±20%)
to AGND
60.4kΩ (±20%)
to AGND
121kΩ (±20%)
to AGND
243kΩ (±20%)
to AGND
VCC
Figure 4: Pulse Skip in Light Load
As the output current increases from light-load
condition, the current modulator regulation time
period becomes shorter. The HS-FET is turned
on more frequently, and the switching
frequency increases accordingly. The output
current reaches critical levels when the current
modulator time is zero. The critical level of the
output current can be determined with Equation
(1):
IOUT
( VIN VOUT ) VOUT
2 L FSW VIN
Light-Load
Mode
Forced CCM
Switching
Frequency
1100kHz
Forced CCM
2000kHz
Forced CCM
600kHz
Pulse skip
600kHz
Pulse skip
2000kHz
Pulse skip
1100kHz
Soft Start (SS)
The minimum soft-start time is limited to 1ms.
This can be increased by choosing the
capacitance between TRK/REF and AGND. A
minimum value of 3.3nF for this capacitor is
always required to stabilize the reference
voltage.
The capacitance of this capacitor can be
determined with Equation (2) and Equation (3):
CREF(nF) 3.3~33
C REF (nF)
(tSS = 2.2ms) (2)
t ss (m s) 10 A
(tSS > 2.2ms) (3)
0.6 V
(1)
Where FSW is the switching frequency.
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
Output Voltage Tracking and Reference
The MPQ8626 provides an analog input pin
(TRK/REF) to track another power supply or
accept an external reference voltage (VREF).
When an external voltage signal is connected to
TRK/REF, it acts as a reference for the
MPQ8626 output voltage. The FB voltage (VFB)
follows this external voltage signal exactly, and
the soft-start settings are ignored. The
TRK/REF input signal can be in the range of
0.3V to 1.4V. During the initial start-up, the
TRK/REF must reach 600mV or above first to
ensure proper operation. Afterward, TRK/REF
can be set to any value between 0.3V and 1.4V.
Pre-Bias Start-Up
The MPQ8626 has been designed for
monotonic start-up into pre-biased loads. If the
output is pre-biased to a certain voltage during
start-up, the IC disables switching for both the
HS-FET and LS-FET until the voltage on the
TRK/REF capacitor exceeds the sensed output
VFB. Before the TRK/REF voltage reaches the
pre-biased FB level, if the BST voltage (from
BST to SW) is lower than 2.3V, the LS-FET is
turned on to allow the BST voltage to be
charged through VCC. The LS-FET is turned on
for very narrow pulses, so the drop in the prebiased level is negligible.
Output Voltage Discharge
When the MPQ8626 is disabled through EN,
the output voltage discharge mode is enabled.
This causes both the HS-FET and the LS-FET
to latch off. A discharge MOSFET connected
between SW and PGND is turned on to
discharge the output voltage. The typical switch
on resistance of this MOSFET is about 80Ω.
Once VFB drops below 10% * REF, the
discharge MOSFET turns off.
Current Sense and Over-Current Protection
(OCP)
The MPQ8626 features an on-die current sense
and a programmable positive current limit
threshold. The current limit is active when the
MPQ8626 is enabled. During the LS-FET on
state, the SW current (inductor current) is
sensed and mirrored to CS with the ratio of GCS.
By using a resistor (RCS) from CS to AGND, the
CS voltage (VCS) is proportional to the SW
current cycle-by-cycle. The HS-FET is only
allowed to turn on when VCS is below the
internal over-current protection (OCP) voltage
threshold (VOCP) during the LS-FET on state to
limit the SW valley current cycle-by-cycle.
Generally, the current limit threshold setting is
calculated from RCS with Equation (4):
R CS ( )
G CS (ILIM
VOCP
(VIN VO ) VO
1
)
VIN
2 L fs
(4)
Where VOCP is 1.2V, GCS is 40µA/A, and ILIM is
the desired output current limit.
There is some offset for the low current limit
threshold setting. Refer to Table 2 for a more
accurate setting.
Table 2: Threshold Setting
RCS (KΩ)
LLIM_DC (A)
8
3.83
7.5
4.02
7
4.32
6.5
4.64
6
4.87
5.5
5.49
5
5.9
4.5
6.49
4
7.15
The OCP HICCUP is active 3ms after the
MPQ8626 is enabled, Once OCP HICCUP is
active, if the MPQ8626 detects over-current
condition for consecutive 31 cycles, or if the FB
drops below under-voltage protection (UVP)
threshold, it enters HICCUP mode. In HICCUP
mode, the MPQ8626 latches off the HSFET
immediately, and latches off LSFET after ZCD
is detected. Meanwhile, the TRK/REF capacitor
is also discharged. After about 14ms, the
MPQ8626 will try to soft start automatically. If
the over-current condition still holds after 3ms
of running, the MPQ8626 repeats this operation
cycle until the over-current condition disappears,
and the output voltage rises smoothly back to
the regulation level.
Negative Inductor Current Limit
When the LS-FET detects a -8A current, the
MPQ8626 turns off the LS-FET and turns on
the HS-FET for 100ns to limit the negative
current.
Output Sinking Mode (OSM)
The MPQ8626 employs output sinking mode
(OSM) to regulate the output voltage to the
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
targeted value. When VFB is higher than 105% *
REF but below the over-voltage protection
(OVP) threshold, OSM is triggered. During
OSM, the LS-FET remains on until it reaches
the -4A negative current limit. The LS-FET is
then turned off, the HS-FET is turned on
momentarily for 100ns, and then the LS-FET is
turned on again. The MPQ8626 repeats this
operation until VFB drops below 102% * REF.
The MPQ8626 exits OSM after 15 consecutive
cycles of forced CCM.
Over-Voltage Protection (OVP)
The MPQ8626 monitors the output voltage by
connecting FB to the tap of the output voltage
feedback resistor divider to detect an overvoltage condition. This provides hiccup OVP.
If VFB exceeds 116% of VREF, OVP is triggered.
PG is pulled low until the over-voltage (OV)
condition is cleared. The LS-FET is turned on
until it reaches the low-side negative current
limit of -8A (NOCP). The LS-FET is then turned
off momentarily for 100ns, and the HS-FET is
turned on. After 100ns, the LS-FET is turned on
again. The MPQ8626 continues this operation
to discharge the over-voltage condition on the
output. The device exits OVP discharge mode
when VFB drops below 105% * REF. PGOOD is
pulled high again a 1ms delay.
extra zero to the system, which improves loop
response. R1 and CFF are selected so that the
zero formed by R1 and CFF is located around
20 ~ 60kHz. fZ can be determined with Equation
(6):
fZ
1
2 R1 C FF
(6)
Power Good (PGOOD)
The MPQ8626 has a power good (PGOOD)
output. PGOOD is the open drain of a MOSFET.
Connect PGOOD to VCC or another external
voltage source less than 3.6V through a pull-up
resistor (typically 10kΩ). After applying the input
voltage, the MOSFET turns on, so PGOOD is
pulled to GND before TRK/REF is ready. After
VFB reaches 92.5% of VREF, PGOOD is pulled
high after a 0.8ms delay.
When VFB drops to 80% of VREF or exceeds
116% of the nominal VREF, PGOOD is latched
low. PGOOD can be pulled high again only
after a new SS.
If the input supply fails to power the MPQ8626,
PGOOD is clamped low, even though PGOOD
is tied to an external DC source through a pullup resistor. The relationship between the
PGOOD voltage and the pull-up current is
shown in Figure 5.
Over-Temperature Protection (OTP)
The MPQ8626 has over-temperature protection
(OTP). The MPQ8626 monitors the junction
temperature
internally.
If
the
junction
temperature exceeds the threshold value
(typically 160°C), the converter shuts off. There
is a hysteresis of about 20°C. Once the junction
temperature drops to around 140°C, a new SS
is initiated.
Output Voltage Setting and Remote Output
Voltage Sensing
First, choose a value for R1. Then R2 can be
determined with Equation (5):
VREF
R 2 (k )
R 1(k )
VO VREF
(5)
Where VREF is 600mV.
To optimize the load transient response, a feedforward capacitor (CFF) is recommended to be
added in parallel to R1. R1 and CFF add an
Figure 5: PGOOD Clamped Voltage vs. Pull-Up
Current
Enable (EN) Configuration
The MPQ8626 turns on when EN goes high
and turns off when EN goes low. EN cannot be
left floating for proper operation. EN can be
driven by an analog or digital control logic
signal to enable or disable the MPQ8626.
MPQ8626 Rev. 1.02
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
The MPQ8626 provides accurate EN thresholds,
so a resistor divider (R3/R4 in Figure 2) from
VIN to AGND can be used to program the input
voltage at which the MPQ8626 is enabled. This
is highly recommended for applications where
there is no dedicated EN control logic signal to
avoid possible under-voltage lockout (UVLO)
bouncing during power-up and power-down.
The resistor divider values can be determined
with Equation (7):
VIN _ START ( V) VIHEN
RUP RDOWN
RDOWN
(7)
Where VIHEN is 1.22V, typically.
RUP and RDOWN should be chosen so that VEN
does not exceed 3.6V when VIN reaches the
maximum value.
EN can also be connected to VIN directly
through a pull-up resistor (RUP). RUP should be
chosen so that the maximum current going to
EN is 50µA. RUP can be calculated with
Equation (8):
RUP (k)
VINMAX (V)
0.05(mA)
(8)
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
APPLICATION INFORMATION
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the step-down
converter while maintaining the DC input
voltage. Use ceramic capacitors for the best
performance. During layout, place the input
capacitors as close to VIN as possible.
The capacitance can vary significantly with the
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over a wide temperature
range. The capacitors must have a ripple
current rating that exceeds the converter’s
maximum input ripple current. Estimate the
input ripple current with Equation (9):
ICIN IOUT
V
VOUT
(1 OUT )
VIN
VIN
(9)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (10):
ICIN
IOUT
2
(10)
For simplification, choose an input capacitor
with an RMS current rating that exceeds half
the maximum load current.
The input capacitance value determines the
converter input voltage ripple. Select a
capacitor value that meets any input voltage
ripple requirement.
Estimate the input voltage ripple with Equation
(11):
VIN
IOUT
V
V
OUT (1 OUT )
FSW C IN
VIN
VIN
(11)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (12):
VIN
IOUT
1
4 FSW C IN
(12)
Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic capacitors or POSCAPs.
Estimate the output voltage ripple with Equation
(13):
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (13)
FSW L
VIN
8 FSW COUT
When
using
ceramic
capacitors,
the
capacitance dominates the impedance at the
switching frequency. The capacitance also
dominates the output voltage ripple. For
simplification, estimate the output voltage ripple
with Equation (14):
VOUT
VOUT
2
8 FSW L C OUT
(1
VOUT
) (14)
VIN
The ESR dominates the switching frequency
impedance for POSCAPs. For simplification,
the output ripple can be approximated with
Equation (15):
VOUT
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(15)
Inductor
The inductor supplies a constant current to the
output load while being driven by the switching
input voltage. A larger value inductor results in
less ripple current and lower output ripple
voltage, but also has a larger physical size, a
higher series resistance, and a lower saturation
current. Generally, select an inductor value that
allows the inductor peak-to-peak ripple current
to be 30% to 40% of the maximum switch
current limit. Also design for a peak inductor
current that is below the maximum switch
current limit. Calculate the inductance value
with Equation (16):
L
VOUT
V
(1 OUT )
FSW IL
VIN
(16)
Where ∆IL is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated with
Equation (17):
I LP I OUT
V OUT
V
(1 OUT )
VIN
2 FSW L
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(17)
18
MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For the best performance, refer to
Figure 7 and follow the guidelines below.
5. Place the VCC decoupling capacitor close
to the device.
1. Place the input MLCC capacitors as close
to VIN and PGND as possible.
7. Place the BST capacitor as close to BST
and SW as possible.
2. Place the major MLCC capacitors on the
same layer as the MPQ8626.
8. Use traces with a width of 20mil or wider to
route the path.
3. Maximize the VIN and PGND copper plane
to minimize parasitic impedance.
9. Use a 0.1µF to 1µF bootstrap capacitor.
4. Place as many PGND vias as possible as
close to PGND as possible to minimize both
parasitic impedance and thermal resistance.
6. Connect AGND and PGND at the point of
the VCC capacitor's ground connection.
10. Place the REF capacitor close to TRK/REF
to AGND.
Figure 7: Example of PCB Layout (Placement & Top Layer PCB)
NOTE: Via size is 20/10mils.
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MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT
PACKAGE INFORMATION
QFN-14 (2mmx3mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MPQ8626 Rev. 1.02
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