MPQ8633AGLE-Z

MPQ8633A The Future of Analog IC Technology 16V, 12A, Synchronous Step-Down Converter with Adjustable Current Limit, Programmable Frequency, and Voltage Tracking DESCRIPTION The MPQ8633A is a fully integrated, highfrequency, synchronous buck converter. It offers a very compact solution to achieve up to 12A output current over a wide input supply range with excellent load and line regulation. The MPQ8633A operates at high efficiency over a wide output current load range. The MPQ8633A adopts internally compensated constant-on-time (COT) control mode that provides fast transient response and eases loop stabilization. The operating frequency is set easily to 600kHz, 800kHz, or 1000kHz with the MODE configuration, allowing the MPQ8633A frequency to remain constant regardless of the input/output voltages. The output voltage start-up ramp is controlled by an internal 1ms timer. It can be increased by adding a capacitor on TRK/REF. An open-drain power good(PGOOD) signal indicates the output is within its nominal voltage range. The PGOOD is clamped to around 0.7V with external pull-up voltage when the input supply fails to power the MPQ8633A. Fully integrated protection features include overcurrent protection (OCP), over-voltage protection (OVP), under-voltage protection (UVP), and overtemperature protection (OTP). The MPQ8633A requires a minimum number of readily available, standard, external components and is available in a QFN 3mm x 4mm package. FEATURES      Wide Input Voltage Range from 2.7V: o 2.7V to 16V with External 3.3V VCC Bias o 4 V to 16V with Internal Bias or External 3.3V VCC Bias Differential Output Voltage Remote Sense Programmable Accurate Current Limit Level 12A Output Current Low RDS(ON) Integrated Power MOSFETs                 Proprietary Switching Loss Reduction Technique Adaptive COT for Ultrafast Transient Response Stable with Zero ESR Output Capacitor 0.5% Reference Voltage over 0C to +70C Junction Temperature Range 1% Reference Voltage from -40C to +125C Junction Temperature Range Selectable Pulse Skip or Forced CCM Operation Excellent Load Regulation Output Voltage Tracking Output Voltage Discharge PGOOD Active Clamped Low Level during Power Failure Programmable Soft-Start Time from 1ms Pre-Bias Start-Up Selectable Switching Frequency from 600kHz, 800kHz, and 1000kHz Non-Latch OCP, UVP, UVLO, Thermal Shutdown, and Latch-Off for OVP. Output Adjustable from 0.6V to 90%*Vin, up to 5.5V Max. Available in a QFN 3mm x 4mm Package APPLICATIONS        Telecom and Networking Systems Server, Cloud-Computing, Storage Base Stations General Purpose Point-of-Load (PoL) 12V Distribution Power Systems High-end TV Game Consoles and Graphic Cards All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 1 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING TYPICAL APPLICATION MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 2 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING ORDERING INFORMATION Part Number Package Top Marking MPQ8633AGLE* QFN-21 (3mm x 4mm) See Below MPQ8633AGL** QFN-20 (3mm x 4mm) See Below * For Tape & Reel, add suffix –Z (e.g. MPQ8633AGLE–Z) ** For Tape & Reel, add suffix –Z (e.g. MPQ8633AGL–Z) **MPQ8633AGL is not recommended for new design TOP MARKING (MPQ8633AGLE) TOP MARKING (MPQ8633AGL) (Not recommended for new design) MP: MPS prefix Y: Year code W: Week code 8633A: First five digits of the part number LLL: Lot number E: MPQ8633AGLE MP: MPS prefix Y: Year code W: Week code 8633A: First five digits of the part number LLL: Lot number PACKAGE REFERENCE TOP VIEW QFN (3mm x 4mm) (QFN-21) (QFN-20) (Not recommended for new design) MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 3 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING ABSOLUTE MAXIMUM RATINGS 1) Supply voltage (VIN) ...................................... 18V VSW (DC) ............................................... -0.3V to VIN VSW (25 ns) 2) ...................................... -3V to 25V VSW (25ns) .......................................... -5V to 25V VBST........................................................ VSW + 4V VCC, EN........................................................ 4.5V All other pins .................................. -0.3V to 4.3V Junction temperature ................................ 170°C Lead temperature...................................... 260°C Storage temperature .................-65°C to +170°C Thermal Resistance 5) θJB θJC_TOP QFN (3mm x 4mm)...…….....9….....21.....°C/W NOTES: 1) Exceeding these ratings may damage the device. 2) Measured by using differential oscilloscope probe. 3) The device is not guaranteed to function outside of its operating conditions. 4) The voltage rating can be in the range of -3V to 23V for a period of 25ns or less with a maximum repetition rate of 1000kHz when the input voltage is 16V. 5) ΘJB: Thermal resistance from junction to board around PGND pin soldering point. ΘJC_TOP: Thermal resistance from junction to top of package. Recommended Operating Conditions 3) Supply voltage (VIN) ............................ 4V to 16V VIN(DC)- VSW(DC) 4) ..................... -0.3V to VIN + 0.3V VSW(DC) 4) ................................. -0.3V to VIN + 0.3V Output voltage (VOUT) ...................... 0.6V to 5.5V External VCC Bias (VCC_EXT) ......... 3.12V to 3.6V Maximum output current (IOUT_MAX) ............... 12A Maximum output current limit (IOC_MAX) ......... 16A Maximum peak inductor current (IL_PEAK) ...... 18A EN Voltage (VEN) ......................................... 3.6V Operating junction temp. (TJ). ...-40°C to +125°C MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 4 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING ELECTRICAL CHARACTERISTICS VIN = 12V, TJ = -40C to +125C, unless otherwise noted. Parameters SUPPLY CURRENT Supply current (shutdown) Supply current (quiescent) Symbol IIN IIN Condition Min Typ Max Units VEN = 0V VEN = 2V, VFB = 0.62V 0 650 10 850 μA μA VEN = 0V, VSW = 0V VEN = 0V, VSW = 12V VEN = 2V @ 25oC VEN = 2V @ 25oC 0 0 13.3 3.8 10 30 μA 1.15 18 1.2 20 -9 200 1.25 22 V μA/A A ns 480 600 720 kHZ 680 800 920 kHZ 850 1000 1150 kHZ 50 180 ns ns MOSFET Switch leakage HS on-state resistance LS on-state resistance CURRENT LIMIT Current limit threshold ICS to IOUT ratio Low-side negative current limit Negative current limit time-out6) SWITCHING FREQUENCY SWLKG_HS SWLKG_LS RDS_ON_HS RDS_ON_LS VLIM ICS/IOUT ILIM_NEG tNCL_Timer IOUT ≥2A MODE = GND, IOUT =0A, VOUT=1V, MODE = 30.1K, IOUT =0A, Switching frequency7) fSW VOUT=1V, MODE = 60.4K, IOUT =0A, VOUT=1V, Minimum on time 6) TON_MIN VFB = 500mV 6) Minimum off time TOFF_MIN VFB = 500mV OVER-VOLTAGE AND UNDER-VOLTAGE PROTECTION OVP threshold VOVP UVP threshold VUVP FEEDBACK VOLTTAGE AND SOFT-START FEEDBACK voltage TRK/REF sourcing current TRK/REF sinking current VREF ITRACK_Source ITRACK_Sink Soft-start time tSS ERROR AMPLIFIER Error amplifier offset Feedback current VOS IFB mΩ mΩ 113% 77% 116% 80% 119% 83% VREF VREF TJ = -40C to +125C 594 600 606 mV TJ = 0C to +70C VTRK/REF = 0V VTRK/REF = 1V 597 600 603 mV CTRACK = 1nF, TJ = 25C 0.75 1 1.25 ms -3 0 50 3 100 mV nA VFB = REF 42 12 MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. μA μA 5 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40C to +125C, unless otherwise noted. ENABLE AND UVLO Enable input rising threshold Enable hysteresis VIHEN VEN-HYS Enable input current Soft shutdown discharge FET IEN 1.17 VEN = 2V 1.22 200 1.27 0 RON_DISCH V mV μA 80 150 Ω 2.1 2.4 2.7 V VINVth_Fall 1.55 1.85 2.15 V VCCVth_Rise 2.65 2.8 2.95 V VCCvth_Fall 2.35 2.5 2.65 V 2.88 3.00 0.5 3.12 V % VIN UVLO VIN under-voltage lockout threshold rising VIN under-voltage lockout threshold falling VCC REGULATOR VCC under-voltage lockout threshold rising VCC under-voltage lockout threshold falling VCC regulator VCC load regulation POWER GOOD Power good high threshold Power good low threshold VINVth_Rise VCC = 3.3V VCC Icc = 25mA PGVth_Hi_Rise FB from low to high 89.5% 92.5% 95.5% VREF PGVth_Lo_Rise PGVth_Lo_Fall FB from low to high FB from high to low 113% 77% 116% 80% 119% 83% VREF VREF 0.63 0.9 1.17 ms 0.5 V 3 µA 650 800 mV 750 900 mV Power good low to high delay Power good sink current capability Power good leakage current PGTd TJ = 25C VPG IPG = 10mA IPG_LEAK VOL_100 Power good low-level output voltage VOL_10 VPG = 3.3V VIN = 0V, Pull PGOOD up to 3.3V through a 100KΩ resistor @ 25oC. VIN = 0V, Pull PGOOD up to 3.3V through a 10KΩ resistor @ 25oC. THERMAL PROTECTION Thermal shutdown 6) Thermal shutdown hysteresis6) TSD 160 30 °C °C NOTE: 6) Guaranteed by design. 7) Guaranteed by design over temperature.. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 6 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted. Thermal Results 800kHz, No air-flow Switching Frequency vs. Input Voltage 1300 1.208 1200 1.207 1.206 1.205 Forced CCM 1.204 Pulse Skip 1.203 0 2 4 6 8 10 12 FREQUENCY (kHz) 1.209 VOUT = 1.2V, 3A Load 1100 1000 900 600kHz 800 800kHz 1MHz 700 600 4 6 8 10 12 14 16 INPUT VOLTAGE (V) Switching Frequency vs. Input Voltage V = 12V, 3A Load 1300 IN FREQUENCY (kHz) 1200 1100 1000 900 600kHz 800 700 800kHz 1MHz 600 1 1.5 2 2.5 3 3.5 4 4.5 5 OUTPUT VOLTAGE (A) MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 7 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted. Steady State Steady State Steady State IOUT = 0A, Pulse Skip IOUT = 0.5A, Pulse Skip IOUT = 12A, Pulse Skip VSW 4V/div. VSW 4V/div. VOUT/AC 10mV/div. VOUT/AC 10mV/div. VSW 4V/div. VOUT/AC 10mV/div. Steady State Steady State Load Transient IOUT = 0A, Forced CCM IOUT = 12A, Forced CCM IOUT = 0A-6A, Pulse Skip VOUT/AC 50mV/div. VSW 4V/div. VSW 4V/div. VOUT/AC 10mV/div. VOUT/AC 10mV/div. VOUT/AC 50mV/div. VSW 4V/div. IOUT 5A/div. VSW 4V/div. IOUT 5A/div. Load Transient Power Up through EN Power Up through EN IOUT = 0A-6A, Forced CCM IOUT = 0A, Pulse Skip IOUT = 12A, Pulse Skip VEN 2V/div. VEN 2V/div. VOUT 500mV/div. VOUT 500mV/div. IL 5A/div. IL 5A/div. VPGOOD 2V/div. VPGOOD 2V/div. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 8 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted. Power Up through EN Power Up through EN Power Down through EN IOUT = 0A, Forced CCM IOUT = 12A, Forced CCM IOUT = 0A, Pulse Skip VEN 2V/div. VEN 5V/div. VEN 2V/div. VOUT 500mV/div. VOUT 500mV/div. VOUT 500mV/div. IL 5A/div. IL 5A/div. VPGOOD 2V/div. VPGOOD 2V/div. VPGOOD 2V/div. IL 2A/div. Power Down through EN Power Down through EN Power Down through EN IOUT = 12A, Pulse Skip IOUT = 0A, Forced CCM IOUT = 12A, Forced CCM VEN 5V/div. VEN 5V/div. VEN 5V/div. VOUT 500mV/div. VOUT 500mV/div. VOUT 500mV/div. VPGOOD 2V/div. IL 2A/div. IL 5A/div. IL 5A/div. Pre-bias Start Up Pre-bias Start Up Pulse Skip Forced CCM VEN 2V/div. VEN 2V/div. VOUT 500mV/div. VOUT 500mV/div. VSW 5V/div. VSW 5V/div. VPGOOD 2V/div. VPGOOD 2V/div. Over-Current Protection Entry VOUT 500mV/div. VTRK/REF 500mV/div. IL 5A/div. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 9 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted. Over-Current Protection Recovery OSM Operation Over-voltage Protection Pulse Skip Mode Pulse Skip Mode IL 2A/div. VPGOOD 1V/div. VOUT 500mV/div. IL 5A/div. VTRK/REF 500mV/div. VOUT 500mV/div. VSW 5V/div. IL 5A/div. VOUT 500mV/div. Over-voltage Protection Forced CCM VPGOOD 1V/div. IL 5A/div. VOUT 500mV/div. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 10 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING PIN FUNCTIONS MPQ8633A (QFN-21) PIN # Name 1 BST 2 AGND 3 CS 4 MODE 5 TRK/REF 6 RGND 7 FB 8 EN 9 PGOOD 10, 21 VIN 11-18 PGND 19 VCC 20 SW Description Bootstrap. A capacitor connected between SW and BS is required to form a floating supply across the high-side switch driver. Analog ground. Select AGND as the control circuit reference point. Current limit. Connect a resistor to AGND to set the current limit trip point. See Equation 4 for additional details. Operation mode selection. Program MODE to select CCM, pulse skip mode, and the operating switching frequency. See Table 1 for additional details. External tracking voltage input. The output voltage tracks this input signal. Decouple with a ceramic capacitor as close to TRK/REF as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. The capacitance of this capacitor determines the soft-start time. See Equation 2 and 3 for additional details. Differential remote sense negative input. Connect this pin directly to the negative side of the voltage sense point. Short to GND if remote sense is not used. Feedback (Differential remote sense positive input). An external resistor divider from the output to RGND (tapped to FB) sets the output voltage. It is recommended to place the resistor divider as close to FB as possible. Vias should be avoided on the FB traces. Enable. EN is an input signal that turns the regulator on or off. Drive EN high to turn on the regulator, drive EN low to turn off the regulator. Connect EN to VIN through a pull-up resistor or a resistive voltage divider for automatic start-up. Do NOT float EN. Power good output. This is an open-drain signal. A pull-up resistor (connected to a DC voltage) is required to indicate high if the output voltage is within regulation. There is about 1ms delay from FB ≥ 92.5% to PGOOD pull-high. Input voltage. VIN supplies power for the internal MOSFET and regulator. The input capacitors are needed to decouple the input rail. Use wide PCB traces to make the connection. System ground. PGND is the reference ground of the regulated output voltage. For this reason, care must be taken in PCB layout. Use wide PCB traces to make the connection. Internal 3V LDO output. The driver and control circuits are powered from this voltage. Decouple with a minimum 1µF ceramic capacitor as close to VCC as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to the VIN voltage by the high-side switch during the on-time of the PWM duty cycle. The inductor current drives SW low during the off-time. Use wide PCB traces to make the connection. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 11 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING MPQ8633A (QFN20) PIN # Name 1 BST 2 AGND 3 CS 4 MODE 5 TRK/REF 6 RGND 7 FB 8 EN 9 PGOOD 10 VIN 11-18 PGND 19 VCC 20 SW Description Bootstrap. A capacitor connected between SW and BS is required to form a floating supply across the high-side switch driver. Analog ground. Select AGND as the control circuit reference point. Current limit. Connect a resistor to AGND to set the current limit trip point. See equation 4 for additional details. Operation mode selection. Program MODE to select CCM, pulse skip mode, and the operating switching frequency. See Table 1 for additional details. External tracking voltage input. The output voltage tracks this input signal. Decouple with a ceramic capacitor as close to TRK/REF as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. The capacitance of this capacitor determines the soft-start time. See Equation 2 and 3 for additional details. Differential remote sense negative input. Connect this pin directly to the negative side of the voltage sense point. Short to GND if remote sense is not used. Feedback (Differential remote sense positive input). An external resistor divider from the output to RGND (tapped to FB) sets the output voltage. It is recommended to place the resistor divider as close to FB as possible. Vias should be avoided on the FB traces. Enable. EN is a input signal that turns the regulator on or off. Drive EN high to turn on the regulator, drive EN low to turn off the regulator. Connect EN to VIN through a pull-up resistor or a resistive voltage divider for automatic start-up. Do NOT float EN. Power good output. This is an open-drain signal. A pull-up resistor (connected to a DC voltage) is required to indicate high if the output voltage is within the regulation. There is about 1ms delay from FB ≥ 92.5% to PGOOD pull-high. Input voltage. VIN supplies power for the internal MOSFET and regulator. The input capacitors are needed to decouple the input rail. Use wide PCB traces to make the connection. System ground. PGND is the reference ground of the regulated output voltage. For this reason, care must be taken in PCB layout. Use wide PCB traces to make the connection. Internal 3V LDO output. The driver and control circuits are powered from this voltage. Decouple with a minimum 1µF ceramic capacitor as close to VCC as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to the VIN voltage by the high-side switch during the on-time of the PWM duty cycle. The inductor current drives SW low during the off-time. Use wide PCB traces to make the connection. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 12 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING FUNCTIONAL BLOCK DIAGRAM Figure 1—Functional block diagram MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 13 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING OPERATION COT Control The MPQ8633A employs constant-on-time (COT) control to achieve fast load transient response. In Figure 2, it shows the details of the control stage of MPQ8633A. The operational amplifier (AMP) corrects any error voltage between FB and VREF. With the help of AMP, MPQ8633A can provide excellent load regulation over the whole load range, no matter it operates in forced CCM or pulse skip mode. The dedicated RGND pin helps to provide the feature of the differential output voltage remote sense. The pair of the remote sense trace should be kept in low impedance to achieve the best performance. The MPQ8633A has internal RAMP compensation, so that it supports low ESR MLCC output capacitor solution. The adaptive internal RAMP is optimized so that the MPQ8633A is stable in the whole operating input/output voltage range with proper design of the output L/C filter. is in its off state to minimize conduction loss. A dead short occurs between VIN and PGND if both the HS-FET and the LS-FET are turned on at the same time (shoot-through). In order to avoid shoot-through, a dead time (DT) is generated internally between the HS-FET off and the LS-FET on period or the LS-FET off and the HS-FET on period. Figure 3—Heavy-load operation (PWM) CCM Operation FIGURE 2—COT CONTROL PWM Operation In Figure 3, it shows how the PWM is generated. The AMP corrects any error between FB and REF, and generates a fairly smooth DC voltage (COMP). The internal RAMP is superimposed onto COMP. The superimposed COMP is compared with the FB signal. Whenever FB drops below the superimposed COMP, it turns on the integrated high-side MOSFET (HS-FET). The HS-FET keeps on for a fixed turn-on time. The fixed on time is determined by the input voltage, output voltage and selected switching frequency. After the on period elapses, the HSFET turns off. It turns on again when FB drops below the superimposed COMP. By repeating this operation, the MPQ8633A regulates the output voltage. The integrated low-side MOSFET (LS-FET) turns on when the HS-FET Continuous conduction mode (CCM) occurs when the output current is high, and the inductor current is always above zero amps (see Figure 2). The MPQ8633A can also be configured to operate in forced CCM operation when the output current is low (See Mode Selection section for details). In CCM operation, the switching frequency is fairly constant (PWM mode), hence the output ripple keeps almost the same throughout the whole load range. Pulse Skip Operation At light load condition, the MPQ8633A can be configured to work in pulse skip mode to optimize the efficiency. When the load decreases, the inductor current will decrease as MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 14 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING well. Once the inductor current reaches zero, the part transitions from CCM to pulse skip mode if the MPQ8633A is configured so (see Mode Selection section for details). Figure 4 shows pulse skip mode operation at light-load condition. When FB drops below superimposed COMP, the HS-FET turns on for a fixed interval. When the HS-FET turns off, the LS-FET turns on until the inductor current reaches zero. In pulse skip mode operation, the FB does not reach superimposed COMP when the inductor current approaches zero. The LSFET driver turns into tri-state (high Z) when the inductor current hits zero. A current modulator takes over the control of the LS-FET and limits the inductor current to less than -1mA. Hence, the output capacitors discharge slowly to PGND through the LS-FET. At light load condition, the HS-FET is not turned on as frequently in pulse skip mode as it is in forced CCM. As a result, the efficiency in pulse skip mode is improved greatly, comparing with that in forced CCM operation. IOUT  The part enters PWM mode once the output current exceeds the critical level. After that, the switching frequency stays fairly constant over the output current range. The MPQ8633A can be configured to operate in forced CCM even in a light-load condition. See Table 1 for MODE configuration. Mode Selection The MPQ8633A provides both forced CCM operation and pulse skip mode operation in a light-load condition. The MPQ8633A has three options for switching frequency selection. Selecting the operation mode under light load condition and the switching frequency is done by choosing the resistance value of the resistor connected between MODE and AGND or VCC (see Table 1). Table 1—MODE selection VCC 243 kΩ (±20%) to GND 121 kΩ (±20%) to GND GND 30.1 kΩ (±20%) to GND 60.4 kΩ (±20%) to GND As the output current increases from the lightload condition, the time period within which the current modulator regulates becomes shorter. The HS-FET is turned on more frequently. Hence, the switching frequency increases accordingly. The output current reaches the critical level when the current modulator time is zero. The critical level of the output current is determined with Equation (1): (1) Where FSW is the switching frequency. MODE Figure 4—Pulse Skip at Light-load ( VIN  VOUT )  VOUT 2  L  FSW  VIN Light-Load Mode Pulse skip Switching Frequency 600 KHz Pulse skip 800 KHz Pulse skip 1000 KHz Forced CCM 600 KHz Forced CCM 800 KHz Forced CCM 1000 KHz Soft Start (SS) The minimum soft-start time is limited at 1ms. It can be increased by adding a SS capacitor between TRK/REF and RGND. The total SS capacitor value can be determined with Equation (2) and (3): t ss (ms)  36A 0.6(V) (2) CSS  CSS1 + CSS2 (3) CSS (nF)  where CSS2 is recommended minimum of 22nF. MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. to be 15 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING Output Voltage Tracking and Reference The MPQ8633A provides an analog input pin (TRK/REF) to track another power supply or accept external reference. When an external voltage signal is connected to TRK/REF, it acts as a reference for the MPQ8633A output voltage. The FB voltage follows this external voltage signal exactly; the soft-start settings are ignored. The TRK/REF input signal can be in the range of 0.3V to 1.4V. During the initial start-up, the TRK/REF needs to reach 600mV or above first to ensure proper operation. After that, it can be any value between 0.3V and 1.4V. resistor (RCS) from CS to AGND, the VCS voltage is proportional to the SW current cycleby-cycle. The HS-FET is only allowed to turn on when the VCS voltage is below the internal OCP voltage threshold VOCP (during the LS-FET on state) to limit the SW valley current cycle-bycycle. Pre-Bias Start-Up The MPQ8633A has been designed for a monotonic start-up into pre-biased loads. If the output is pre-biased to a certain voltage during start-up, the IC disables switching for both the high-side and low-side MOSFETs until the voltage on the TRK/REF capacitor exceeds the sensed output voltage at FB. Before TRK/REF voltage reaches pre-biased FB level, if the BST voltage (from BST to SW) is lower than 2.3V, the LS-FET is turned on to allow the BST voltage to be charged through VCC. The LSFET is turned on for very narrow pulses, so the drop in pre-biased level is negligible. Where, Output Voltage Discharge When the MPQ8633A is disabled through EN, it enables the output voltage discharge mode. This causes both the HS-FET and the LS-FET to latch off. A discharge FET connected between SW and PGND is turned on to discharge the output voltage. The typical switch on resistance of this FET is about 80Ω. Once the FB voltage drops below 10%*REF, the discharge FET is turned off. Current Sense and Over-Current Protection (OCP) The MPQ8633A features an on-die current sense and a programmable positive current limit threshold. The current limit is active when the MPQ8633A is enabled. During the LS-FET on state, the SW current (inductor current) is sensed and mirrored to CS with the ratio of GCS. By using a Equation (4) calculates threshold setting from RCS: RCS ()  GCS  ( I LIM the current VOCP (VIN  VO )  VO 1 )   2  L  fs V IN limit (4) VOCP =1.2 V, GCS = 20 µA/A, and ILIM = the desired output current limit. The OCP HICCUP is active 3ms after the MPQ8633A is enabled, Once OCP HICCUP is active, if the MPQ8633A detects over-current condition for consecutive 31 cycles, or if the FB drops below under-voltage protection (UVP) threshold, it enters HICCUP mode. In HICCUP mode, the MPQ8633A latches off the HSFET immediately, and latches off LSFET after ZCD is detected. Meanwhile, the TRK/REF capacitor is also discharged. After about 11ms, the MPQ8633A will try to soft start automatically. If the over-current condition still holds after 3ms of running, the MPQ8633A repeats this operation cycle until the over-current condition disappears, and the output voltage rises smoothly back to the regulation level. Negative Inductor Current limit When the LS-FET detects a -9A current, the part turns off the LS-FET for 200ns to limit the negative current. Output Sinking Mode (OSM) The MPQ8633A employs output sinking mode (OSM) to regulate the output voltage to the targeted value. When the FB voltage is higher than 104%*REF but is below the OVP threshold, it triggers OSM. During OSM operation, the LSFET remains on until it hits the -5.5A negative current limit. Upon hitting -5.5A, the LS-FET is momentarily turned off for 200ns and is then MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 16 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING turned on again. The MPQ8633A keeps this operation until the FB drops below 102%*REF. Once it does, the MPQ8633A exits OSM after 15 consecutive cycles of forced CCM. Over-Voltage Protection (OVP) The MPQ8633A monitors the output voltage by connecting FB to the tap of the output voltage feedback resistor divider to detect an overvoltage condition. This provides latch-off OVP mode. If the FB voltage exceeds 116% of the REF voltage, it enters latch-off OVP mode. The HSFET latches off and PGOOD latches low until power recycle of VCC or EN. Meanwhile, the LS-FET remains on until it hits the low-side negative current limit (NOCP). Once it hits NOCP, the LS-FET is momentarily turned off for 200ns and is then turned on again. The MPQ8633A keeps this operation to try to bring down the output voltage. When the FB voltage drops below 50% of the REF voltage, the LSFET is turned off for pulse skip mode, and keeps turning on for forced CCM operation. If FB rises back to more than 116% of the REF voltage, the LS-FET turns on again with NOCP until FB drops back below 50% of the REF voltage. It needs power recycle of the EN or VIN to clear the OVP fault. The OVP function is enabled after TRK/REF reaches 600mV. Over-Temperature Protection (OTP) The MPQ8633A has over-temperature protection (OTP). The IC monitors internally the junction temperature. If the junction temperature exceeds the threshold value (160ºC, typically), the converter shuts off and discharge the TRK/REF capacitors. This is a non-latch protection. There is about 30ºC hysteresis. Once the junction temperature drops to about 130ºC, it initiates a soft start. The OTP function is effective once the MPQ8633A is enabled. Output Voltage Setting and Remote Output Voltage Sensing First, choose a value for RFB1. Then RFB2 can be determined with Equation (5): RFB2 (k )  VREF  RFB1(k ) VO  VREF (5) To optimize the load transient response, a feedforward capacitor (CFF) is recommended in parallel with RFB1. RFB1 and CFF add an extra zero to the system, which improves loop response. RFB1 and CFF are selected so that the zero formed by RFB1 and CFF is located around 20kHz~60kHz. See Equation (6): 1 fZ  2  RFB1  CFF (6) Power Good (PGOOD) The MPQ8633A has a power good (PGOOD) output. PGOOD is the open-drain of a MOSFET. Connect PGOOD to VCC or another external voltage source (less than 3.6V) through a pullup resistor (10kΩ, typically). After applying the input voltage, the MOSFET turns on, so PGOOD is pulled to GND before TRK/REF is ready. After the FB voltage reaches 92.5% of the REF voltage, PGOOD is pulled high after a 0.8ms delay. When the FB voltage drops to 80% of the REF voltage or exceeds 116% of the nominal REF voltage, PGOOD is latched low. PGOOD can only be pulled high again after a new SS. If the input supply fails to power the MPQ8633A, PGOOD is clamped low even though PGOOD is tied to an external DC source through a pullup resistor. The relationship between the PGOOD voltage and the pull-up current is shown in Figure 5 below: MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 17 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING 2 1.8 1.6 I_PG( mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.6 0.7 0.8 0.9 V_PG(V) Figure 5: PGOOD clamped voltage v.s. pull-up current EN Configuration The MPQ8633A turns on when EN goes high, and it turns off when EN goes low. The EN pin can’t be left floating for proper operation. It can be driven by an analog or digital control logic signal to enable/disable the MPQ8633A. The MPQ8633A provides accurate EN thresholds, so a resistor divider from VIN to AGND can be used to program the input voltage at which the MPQ8633A is enabled. This is highly recommended for the application where there is no dedicated EN control logic signal, to avoid possible UVLO bouncing during power up and power down. The resistor divider values can be determined by equation (7): VIN _ START ( V )  VIHEN  R UP  R DOWN R DOWN (7) VIHEN=1.22V (typical) RUP and RDOWN should be chosen that VEN doesn’t exceed 3.6V when VIN reaches the maximum value. The EN can also be directly connected to VIN through a pull-up resistor (RUP). But the RUP should be chosen that the maximum current going to EN is 50μA. A easy calculation of the RUP is given in equation (8): RUP (K)  VINMAX (V) 0.05(mA) (8) MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 18 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING APPLICATION INFORMATION VOUT  Input Capacitor The input current to the step-down converter is discontinuous, and therefore, requires a capacitor to supply the AC current to the stepdown converter while maintaining the DC input voltage. Use ceramic capacitors for best performance. During layout, place the input capacitors as close to VIN pin as possible. The capacitance can vary significantly with temperature. Use capacitors with X5R and X7R ceramic dielectrics because they are fairly stable over a wide temperature range and they offer very low ESR. The capacitors must have a ripple current rating that exceeds the converter’s maximum input ripple current. Estimate the input ripple current with Equation (9) and Equation (10): VOUT V  (1  OUT ) VIN VIN ICIN  IOUT  (9) The worst-case condition occurs at VIN = 2VOUT, where: I ICIN  OUT (10) 2 For simplification, choose an input capacitor with an RMS current rating that exceeds half the maximum load current.The input capacitor value determines the converter input voltage ripple. If there is an input voltage ripple requirement in the system, select an input capacitor that meets the specification. Estimate the input voltage ripple with Equation (11) and Equation (12): IOUT V V (11) VIN   OUT  (1  OUT ) FSW  CIN VIN VIN The worst-case condition occurs at VIN = 2VOUT, where: IOUT 1 (12) V   IN 4 FSW  CIN Output Capacitor The output capacitor maintains the DC output voltage. Use POSCAP or ceramic capacitors. Estimate the output voltage ripple with Equation (13): VOUT V 1 )  (1  OUT )  (RESR  FSW  L VIN 8  FSW  COUT (13) When using ceramic capacitors, the capacitance dominates the impedance at the switching frequency. The capacitance also dominates the output voltage ripple. For simplification, estimate the output voltage ripple with Equation (14): VOUT  VOUT 2 8  FSW  L  COUT  (1  VOUT ) VIN (14) The ESR dominates the switching frequency impedance for the POSCAP capacitors. For simplification, the output ripple can be approximated with Equation (15): VOUT  VOUT V  (1  OUT )  RESR FSW  L VIN (15) Inductor The inductor supplies constant current to the output load while being driven by the switching input voltage. A larger value inductor results in less ripple current and lower output ripple voltage but has a larger physical size, a higher series resistance, and/or a lower saturation current. Generally, select an inductor value that allows the inductor peak-to-peak ripple current to be 30 percent to 40 percent of the maximum switch current limit. Also, design for a peak inductor current that is below the maximum switch current limit. Calculate the inductance value using Equation (16): L VOUT V  (1  OUT ) FSW  IL VIN (16) Where ∆IL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated with Equation (17): ILP  IOUT  VOUT V  (1  OUT ) 2  FSW  L VIN MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. (17) 19 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING 4. Place the VCC decoupling capacitor close to the device. Connect AGND and PGND at the point of the VCC capacitor's ground connection. PCB Layout Guidelines Efficient PCB layout is critical for stable operation. For optimal performance, refer to Figure 6 and Figure 7 and follow the guidelines below: 5. Place the BST capacitor as close to BST and SW as possible. Use traces with a width of 20mil or wider to route the path. It is recommended to use a 0.1µF to 1µF bootstrap capacitor. 1. Place the input MLCC capacitors as close to the VIN and PGND pins as possible. The major MLCC capacitors should be placed on the same layer as the MPQ8633A. Maximize the VIN and PGND copper plane to minimize the parasitic impedance. 6. Place the REF capacitor close to TRK/REF to RGND. 7. Place via at least 10mm away from the positive side of the first input decoupling capacitor close to the IC if it must be placed on the PGOOD pad. 2. A 0402 capacitor with a minimum 1µF value is required. Place the capacitor on the right side of the IC. VIN is extended to the right side to connect the capacitor. At least two 20/10mil vias should be placed on the ground side of the capacitor to the inner solid ground plane. 8. Place the OSENSE capacitor in between the output sense lines and close to the device. 3. Place PGND vias (as many as possible and as close to PGND as possible) to minimize both parasitic impedance and thermal resistance. COSENSE VOSENSE+ VOSENSE- RFB1 CFF CSS2 V O CSS1 RCS RFB2 EN FB RGND REF/TRK MODE CS AGND BST 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 PGND PGND PGND PGND PGND PGND PGND PGND CIN3 PGOOD RBST 21 VIN 20 SW 10 VIN CIN2 CIN1 VCC CVCC Figure 6—Recommended PCB layout (QFN-21) MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 20 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING VOSENSE+ VOSENSE- CSS2 V O RCS RFB2 RBST CVCC Figure 7—Recommended PCB layout (QFN-20) (Not recommended for new design) MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 21 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING PACKAGE INFORMATION QFN-21 (3mm x 4mm) PIN 1 ID 0.15 X 45 TYP PIN 1 ID MARKING PIN 1 ID INDEX AREA TOP VIEW BOTTOM VIEW SIDE VIEW 0.15 X 45 NOTE: 1) LAND PATTERN OF PIN1,9,10,11,19,20 AND 21 HAVE THE SAME WIDTH. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN MPQ8633A Rev.1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 22 MPQ8633A- 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER W/ADJUSTABLE CURRENT LIMIT, PROGRAMMABLE FREQUENCY, AND VOLTAGE TRACKING PACKAGE INFORMATION QFN-20 (3mm x 4mm) (Not recommended for new design) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ8633A Rev. 1.06 www.MonolithicPower.com 8/27/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. 23