MPQ8634A
The Future of Analog IC Technology
16V, 12A, Sync, Step-Down Converter
with Adjustable Current Limit,
Programmable Frequency, and Voltage Tracking
DESCRIPTION
The MPQ8634A is a fully integrated, highfrequency, synchronous, buck converter. The
MPQ8634A offers a very compact solution that
achieves up to 12A output current with excellent
load and line regulation over a wide input
supply range. The MPQ8634A operates at high
efficiency over a wide output current load range.
The
MPQ8634A
adopts
an
internally
compensated constant-on-time (COT) control
mode that provides fast transient response and
eases loop stabilization.
The operating frequency can be set to 600kHz,
800kHz, or 1000kHz easily with MODE
configuration,
allowing
the
MPQ8634A
frequency to remain constant regardless of the
input/output voltages.
The output voltage start-up ramp is controlled
by an internal 1.5ms timer. It can be increased
by adding a capacitor on TRK/REF. An opendrain power good (PGOOD) signal indicates
when the output is within its nominal voltage
range. PGOOD is clamped at around 0.7V with
an external pull-up voltage when the input
supply fails to power the MPQ8634A.
Fully integrated protection features include
over-current protection (OCP), over-voltage
protection (OVP), under-voltage protection
(UVP), and over-temperature protection (OTP).
The MPQ8634A requires a minimal number of
readily
available,
standard,
external
components and is available in a QFN-21
(3mmx4mm) package.
FEATURES
Wide Input Voltage Range:
o 2.85V to 16V with External 3.3V VCC
Bias
o 4V to 16V with Internal VCC Bias or
External 3.3V VCC Bias
Differential Output Voltage Remote Sense
Programmable Accurate Current Limit Level
12A Output Current
Low RDS(ON) Integrated Power MOSFETs
Proprietary Switching Loss Reduction
Technique
Adaptive COT for Ultrafast Transient
Response
Stable with Zero ESR Output Capacitor
0.5% Reference Voltage over 0°C to
+70°C Junction Temperature Range
1% Reference Voltage from -40°C to
+125°C Junction Temperature Range
Pin-Selectable Pulse-Skip Mode or Forced
CCM Operation
Excellent Load Regulation
Output Voltage Tracking
Output Voltage Discharge
PGOOD Actively Clamped at a Low Level
during Power Failure
Programmable Soft-Start Time from 1.5ms
Pre-Bias Start-Up
Selectable Switching Frequency from
600kHz, 800kHz, and 1000kHz
Latch-Off OCP, UVP, UVLO, Thermal
Shutdown, and Latch-Off for OVP
Output Adjustable from 0.9V to 90%*VIN,
up to 6V Max
Available in a QFN-21 (3mmx4mm)
Package
APPLICATIONS
Telecom and Networking Systems
Servers, Cloud-Computing, Storage
Base Stations
General Purpose Point-of-Load (PoL)
12V Distribution Power Systems
High-end TV
Game Consoles and Graphic Cards
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
MPQ8634A Rev. 1.02
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1
MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
TYPICAL APPLICATION
MPQ8634A Rev. 1.02
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2
MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
ORDERING INFORMATION
Part Number*
MPQ8634AGLE
Package
QFN-21 (3mmx4mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MPQ8634AGLE–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
8634A: First five digits of the part number
LLL: Lot number
E: MPQ8634AGLE
PACKAGE REFERENCE
TOP VIEW
QFN-21 (3mmx4mm)
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ..................................... 18V
VSW (DC)............................... -0.3V to VIN + 0.3V
VSW (25ns) (2) ...................................... -3V to 25V
VSW (25ns) .......................................... -5V to 25V
VBST........................................................ VSW + 4V
VCC, EN ..................................................... 4.5V
All other pins .................................. -0.3V to 4.3V
Junction temperature ................................ 170°C
Lead temperature...................................... 260°C
Storage temperature .................-65°C to +170°C
Thermal Resistance (5)
θJB θJC_TOP
QFN-21 (3mmx4mm) ........... 9 ......... 21 ..... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) Measured by using differential oscilloscope probe.
3) The device is not guaranteed to function outside of its
operating conditions.
4) The voltage rating can be in the range of -3V to 23V for a
period of 25ns or less with a maximum repetition rate of
1000kHz when the input voltage is 16V.
5) θJB: Thermal resistance from the junction to the board around
the PGND soldering point.
θJC_TOP: Thermal resistance from the junction to the top of the
package.
Recommended Operating Conditions (3)
Supply voltage (VIN) ........................... 4V to 16V
VIN (DC) - VSW (DC) (4) ................ -0.3V to VIN + 0.3V
VSW(DC) (4) ............................... -0.3V to VIN + 0.3V
Output voltage (VOUT) ......................... 0.9V to 6V
External VCC bias (VCC_EXT) ......... 3.12V to 3.6V
Maximum output current (IOUT_MAX) ............... 12A
Maximum output current limit (IOC_MAX) ......... 16A
Maximum peak inductor current (IL_PEAK) ...... 18A
EN voltage (VEN) ......................................... 3.6V
Operating junction temp. (TJ). ...-40°C to +125°C
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Supply Current
Supply current (shutdown)
Supply current (quiescent)
Symbol
IIN
IIN
Condition
Min
Typ
Max
Units
VEN = 0V
VEN = 2V, VFB = 1V
0
650
10
850
μA
μA
VEN = 0V, VSW = 0V
VEN = 0V, VSW = 12V
VEN = 2V @ 25oC
VEN = 2V @ 25oC
0
0
13.3
3.8
10
30
μA
1.15
18
1.2
20
-9
200
1.25
22
V
μA/A
A
ns
480
600
720
kHZ
680
800
920
kHZ
850
1000
1150
kHZ
50
180
ns
ns
MOSFET
Switch leakage
HS on-state resistance
LS on-state resistance
Current Limit
Current limit threshold
ICS to IOUT ratio
Low-side negative current limit
Negative current limit timeout (6)
Switching Frequency
Switching frequency (7)
SWLKG_HS
SWLKG_LS
RDS_ON_HS
RDS_ON_LS
VLIM
ICS/IOUT
ILIM_NEG
tNCL_Timer
fSW
IOUT ≥ 2A
MODE = GND, IOUT = 0A,
VOUT = 1V
MODE = 30.1kΩ, IOUT = 0A,
VOUT = 1V
MODE = 60.4kΩ, IOUT = 0A,
VOUT = 1V
Minimum on time (6)
TON_MIN
Minimum off time (6)
TOFF_MIN
VFB = 800mV
Over-Voltage (OVP) and Under-Voltage Protection (UVP)
OVP threshold
VOVP
UVP threshold
VUVP
Feedback Voltage and Soft Start (SS)
TJ = -40°C to +125°C
Feedback voltage
VREF
TJ = 0°C to +70°C
TRK/REF sourcing current
ITRACK_Source VTRK/REF = 0V
TRK/REF sinking current
ITRACK_Sink
VTRK/REF = 1V
Soft-start time
tSS
CSS = 1nF
Error Amplifier (EA)
Error amplifier offset
VOS
Feedback current
IFB
VFB = REF
Enable (EN) and Under-Voltage Lockout (UVLO)
Enable input rising threshold
VIHEN
Enable hysteresis
VEN-HYS
Enable input current
Soft shutdown discharge
MOSFET
IEN
RON_DISCH
VEN = 2V
mΩ
mΩ
113%
77%
116%
80%
119%
83%
VREF
VREF
891
895
900
900
42
12
1.5
909
905
mV
mV
μA
μA
ms
-3
0
50
3
100
mV
nA
1.17
1.22
200
1.27
V
mV
1
0
80
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μA
150
Ω
5
MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
2.1
2.4
2.7
V
VINVth-Fall
1.55
1.85
2.15
V
VCCVth_Rise
2.65
2.8
2.95
V
VCCVth_Fall
2.35
2.5
2.65
V
VCC
2.88
3.00
0.5
3.12
V
%
VIN UVLO
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold falling
VCC Regulator
VCC under-voltage lockout
threshold rising
VCC under-voltage lockout
threshold falling
VCC regulator
VCC load regulation
Power Good (PGOOD)
Power good high threshold
Power good low threshold
Power good low to high delay
Power good sink current
capability
Power good leakage current
VINVth-Rise
VCC = 3.3V
ICC = 25mA
PGVth_Hi_Rise
FB from low to high
89%
92.5%
95%
VREF
PGVth_Lo_Rise
PGVth_Lo_Fall
PGTd
FB from low to high
FB from high to low
TJ = +25°C
113%
77%
0.63
116%
80%
0.9
119%
83%
1.17
VREF
VREF
ms
0.5
V
3
µA
650
800
mV
750
900
mV
VPG
IPG_LEAK
VOL_100
Power good low-level output
voltage
VOL_10
Thermal Protection
Thermal shutdown (6)
TSD
IPG = 10mA
VPG = 3.3V
VIN = 0V, pull PGOOD up
to 3.3V through a 100kΩ
resistor @ 25oC
VIN = 0V, pull PGOOD up
to 3.3V through a 10kΩ
resistor @ 25oC
150
160
°C
NOTES:
6) Guaranteed by design.
7) Guaranteed by design over temperature.
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted.
MPQ8634A Rev. 1.02
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted.
Steady State
Steady State
Steady State
IOUT = 0A, Pulse Skip
IOUT = 0.5A, Pulse Skip
IOUT = 12A, Pulse Skip
VSW
4V/div.
VSW
4V/div.
VOUT/AC
10mV/div.
VOUT/AC
10mV/div.
VSW
4V/div.
VOUT/AC
10mV/div.
Steady State
Steady State
Load Transient
IOUT = 0A, Forced CCM
IOUT = 12A, Forced CCM
IOUT = 0A-6A, Pulse Skip
VOUT/AC
50mV/div.
VSW
4V/div.
VSW
4V/div.
VOUT/AC
10mV/div.
VOUT/AC
10mV/div.
VOUT/AC
50mV/div.
VSW
4V/div.
IOUT
5A/div.
VSW
4V/div.
IOUT
5A/div.
Load Transient
Power Up through EN
Power Up through EN
IOUT = 0A-6A, Forced CCM
IOUT = 0A, Pulse Skip
IOUT = 12A, Pulse Skip
VEN
2V/div.
VEN
2V/div.
VOUT
500mV/div.
VOUT
500mV/div.
IL
5A/div.
IL
5A/div.
VPGOOD
2V/div.
VPGOOD
2V/div.
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted.
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, TA = 25˚C, VOUT = 1.2V, FS = 800kHz unless otherwise noted.
MPQ8634A Rev. 1.02
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
PIN FUNCTIONS
PIN #
Name
1
BST
2
AGND
3
CS
4
MODE
5
TRK/REF
6
VSNS-
7
FB
8
EN
9
PGOOD
10, 21
VIN
11-18
PGND
19
VCC
20
SW
Description
Bootstrap. Connect a capacitor between SW and BS to form a floating supply
across the high-side switch driver.
Analog ground. Select AGND as the control circuit reference point.
Current limit. Connect a resistor to ground to set the current limit trip point. See
Equation 4 for additional details.
Operation mode selection. Program MODE to select continuous conduction mode
(CCM), pulse-skip mode, and the operating switching frequency (See Table 1 for
additional details.).
External tracking voltage input. The output voltage tracks this input signal.
Decouple TRK/REF with a ceramic capacitor as close to TRK/REF as possible. X7R
or X5R grade dielectric ceramic capacitors are recommended for their stable
temperature characteristics. The capacitance of this capacitor determines the softstart time (See Equation 2 and 3 for additional details.).
Differential remote sense negative input. Connect VSNS- to the negative side of
the voltage sense point directly. Short VSNS- to AGND if the remote sense is not
being used.
Feedback (differential remote sense positive input). An external resistor divider
from the output to VSNS- tapped to FB sets the output voltage. Place the resistor
divider as close to FB as possible. Vias should be avoided on the FB traces.
Enable. EN is an input signal that turns the regulator on or off. Drive EN high to turn
on the regulator; drive EN low to turn off the regulator. Connect EN to VIN through a
pull-up resistor or a resistive voltage divider for automatic start-up. Do not float EN.
Power good output. PGOOD is an open-drain signal. A pull-up resistor connected
to a DC voltage is required to indicate high if the output voltage is within regulation.
There is ~1ms of delay from FB ≥ 92.5% to when PGOOD is asserted.
Input voltage. VIN supplies power for the internal MOSFET and regulator. Input
capacitors are needed to decouple the input rail. Make the connection using wide
PCB traces.
System ground. PGND is the reference ground of the regulated output voltage and
requires careful consideration during PCB layout. Make the connection using wide
PCB traces.
Internal 3V LDO output. The driver and control circuits are powered from VCC.
Decouple VCC with a minimum 1µF ceramic capacitor as close to VCC as possible.
X7R or X5R grade dielectric ceramic capacitors are recommended for their stable
temperature characteristics.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven
up to VIN by the high-side switch during the on-time of the PWM duty cycle. The
inductor current drives SW low during the off-time. Make the connection using wide
PCB traces.
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
OPERATION
Constant-On-Time (COT) Control
The MPQ8634A employs constant-on-time
(COT) control to achieve a fast load transient
response (see Figure 2).
The operational amplifier (AMP) corrects any
error voltage between FB and the reference
voltage (VREF). The MPQ8634A can use AMP to
provide excellent load regulation over the entire
load range, no matter if the device is operating
in forced continuous conduction mode (CCM) or
pulse-skip mode.
COMP. By repeating this operation,
MPQ8634A regulates the output voltage.
the
The integrated low-side MOSFET (LS-FET)
turns on when the HS-FET is in its off state to
minimize conduction loss. A dead short occurs
between VIN and PGND if both the HS-FET
and the LS-FET are turned on at the same time.
This is called a shoot-through. To prevent
shoot-through, a dead time (DT) is generated
internally between the HS-FET off and the LSFET on period or the LS-FET off and the HSFET on period.
The dedicated VSNS- pin helps provide
differential output voltage remote sensing. The
pair of the remote sense trace should be kept at
a low impedance to achieve the best
performance.
The MPQ8634A has an internal ramp
compensation that supports a low ESR MLCC
output capacitor solution. The adaptive internal
ramp is optimized so that the MPQ8634A is
stable in the entire operating input/output
voltage range with the proper design of the
output L/C filter.
Figure 3: Heavy-Load Operation (PWM)
Figure 2: COT Control
Pulse-Width Modulation (PWM) Operation
Figure 3 shows how the pulse-width modulation
(PWM) is generated. AMP corrects any error
between FB and REF and generates a fairly
smooth DC voltage (COMP). The internal ramp
is superimposed onto COMP, which is
compared with the FB signal. Whenever FB
drops below the superimposed COMP, the
integrated high-side MOSFET (HS-FET) is
turned on. The HS-FET remains on for a fixed
turn-on time. The fixed on time is determined by
the input voltage, output voltage, and selected
switching frequency. After the on period
elapses, the HS-FET turns off and turns on
again when FB drops below the superimposed
Continuous Conduction Mode (CCM)
Continuous conduction mode (CCM) occurs
when the output current is high and the inductor
current is always above zero amps (see Figure
2). The MPQ8634A can also be configured to
operate in forced CCM operation when the
output current is low (see the MODE Selection
section on page 14 for details).
In CCM operation, the switching frequency is
fairly constant (PWM mode), and the output
ripple remains almost the same throughout the
entire load range.
Pulse-Skip Operation
In light-load condition, the MPQ8634A can be
configured to work in pulse-skip mode to
optimize efficiency. When the load decreases,
the inductor current decreases as well. Once
the inductor current reaches zero, the part
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
transitions from CCM to pulse-skip mode if the
MPQ8634A is configured so (see the MODE
Selection section on page 14 for details).
Figure 4 shows pulse-skip mode operation in
light-load condition. When FB drops below the
superimposed COMP, the HS-FET turns on for
a fixed interval. When the HS-FET turns off, the
LS-FET turns on until the inductor current
reaches zero. In pulse-skip mode operation, FB
does not reach the superimposed COMP when
the inductor current approaches zero. The LSFET driver turns into tri-state (Hi-Z) when the
inductor current reaches zero. A current
modulator takes over the control of the LS-FET
and limits the inductor current to less than
-1mA. The output capacitors discharge slowly
to PGND through the LS-FET. In light-load
condition, the HS-FET is not turned on as
frequently in pulse-skip mode as it is in forced
CCM. As a result, the efficiency in pulse-skip
mode is improved greatly compared with that in
forced CCM operation.
IOUT
( VIN VOUT ) VOUT
2 L FSW VIN
(1)
Where FSW is the switching frequency.
The part enters PWM mode once the output
current exceeds the critical level. Afterward, the
switching frequency remains fairly constant
over the output current range.
The MPQ8634A can be configured to operate in
forced CCM, even if in a light-load condition
(see Table 1).
MODE Selection
The MPQ8634A provides both forced CCM
operation and pulse-skip mode operation in
light-load condition. The MPQ8634A has three
options for switching frequency selection:
600kHz, 800kHz, and 1000kHz. Select the
operation mode under light-load condition and
the switching frequency by choosing the
resistance value of the resistor connected
between MODE and AGND or VCC (see Table
1).
Table 1: MODE Selection
Light-Load
Switching
MODE
Mode
Frequency
VCC
Pulse skip
600kHz
243kΩ (±20%)
Pulse skip
800kHz
to AGND
121kΩ (±20%)
Pulse skip
1000kHz
to AGND
GND
Forced CCM
600kHz
30.1kΩ (±20%)
Forced CCM
800kHz
to AGND
60.4kΩ (±20%)
Forced CCM
1000kHz
to AGND
Figure 4: Pulse Skip at Light Load
As the output current increases from the lightload condition, the current modulator regulation
time period becomes shorter. The HS-FET is
turned on more frequently, and the switching
frequency increases accordingly. The output
current reaches the critical level when the
current modulator time is zero. The critical level
of the output current is determined with
Equation (1):
Soft Start (SS)
The minimum soft-start time is limited at 1.5ms.
This time can be increased by adding a SS
capacitor between TRK/REF and VSNS-.
The total SS capacitor value can be determined
with Equation (2) and Equation (3):
CSS (nF)
t SS (ms) 36(uA)
0.9(V)
CSS CSS1 CSS2
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(2)
(3)
14
MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
Where CSS2 is recommended
minimum of 22nF.
to
be
Output Voltage Tracking and Reference
The MPQ8634A provides an analog input pin
(TRK/REF) to track another power supply or
accept an external reference. When an external
voltage signal is connected to TRK/REF, it acts
as a reference for the MPQ8634A output
voltage. The FB voltage (VFB) follows this
external voltage signal exactly. The soft-start
settings are ignored. The TRK/REF input signal
can be in the range of 0.3V to 1.4V. During the
initial start-up, TRK/REF must be at least
900mV to ensure proper operation. Afterward, it
can be any value between 0.3V and 1.4V.
Pre-Bias Start-Up
The MPQ8634A has been designed for
monotonic start-up into pre-biased loads. If the
output is pre-biased to a certain voltage during
start-up, the IC disables switching for both the
HS-FET and LS-FET until the voltage on the
TRK/REF capacitor exceeds the sensed output
voltage at FB. Before the TRK/REF voltage
reaches the pre-biased FB level, if the BST
voltage (from BST to SW) is lower than 2.3V,
the LS-FET is turned on to allow the BST
voltage to be charged through VCC. The LSFET is turned on for very narrow pulses, so the
drop in the pre-biased level is negligible.
Output Voltage Discharge
When the MPQ8634A is disabled through EN, it
enables the output voltage discharge mode.
This causes both the HS-FET and the LS-FET
to latch off. A discharge MOSFET connected
between SW and PGND is turned on to
discharge the output voltage. The typical switch
on resistance of this MOSFET is about 80Ω.
Once VFB drops below 10%*REF, the discharge
MOSFET is turned off.
Current Sense and Over-Current Protection
(OCP)
The MPQ8634A features an on-die current
sense and a programmable positive current
limit threshold. The current limit is active when
the MPQ8634A is enabled. During the LS-FET
on state, the SW current (inductor current) is
sensed and mirrored to CS with the ratio of GCS.
By using a resistor (RCS) from CS to AGND, the
CS voltage (VCS) is proportional to the SW
current cycle-by-cycle.
The HS-FET is only allowed to turn on when
VCS is below the internal over-current protection
(OCP) voltage threshold (VOCP) (during the LSFET on state) to limit the SW valley current
cycle-by-cycle.
Calculate the current limit threshold setting from
RCS with Equation (4):
RCS ()
VOCP
(VIN VO ) VO
1
GCS (ILIM
)
VIN
2 L fs
(4)
Where VOCP is 1.2V, GCS is 20µA/A, and ILIM is
the desired output current limit (A).
After SS finishes, the MPQ8634A latches off if it
detects an over-current condition for 31
consecutive cycles, or if FB drops below the
under-voltage protection (UVP) threshold. The
MPQ86934A is enabled by recycling the power
of VCC or EN.
Negative Inductor Current Limit
When the LS-FET detects a -9A current, the
part turns off the LS-FET for 200ns to limit the
negative current. After 200ns, the LS-FET is
turned on again.
Output Sinking Mode (OSM)
The MPQ8634A employs output sinking mode
(OSM) to regulate the output voltage to the
targeted value. When VFB is higher than
105%*REF but is lower than the OVP threshold,
OSM is triggered. During OSM operation, the
LS-FET remains on until it reaches the -6.5A
negative current limit. The LS-FET is
momentarily turned off for 200ns and is then
turned on again. The MPQ8634A maintains this
operation until VFB drops below 102%*REF.
Then the MPQ8634A exits OSM after 15
consecutive cycles of forced CCM.
Over-Voltage Protection (OVP)
The MPQ8634A monitors the output voltage by
connecting FB to the tap of the output voltage
feedback resistor divider to detect an overvoltage condition. This provides latch-off overvoltage protection (OVP) mode.
MPQ8634A Rev. 1.02
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
The OVP function is enabled after TRK/REF
reaches 900mV.
Over-Temperature Protection (OTP)
The MPQ8634A has an over-temperature
protection (OTP). The IC monitors the junction
temperature
internally.
If
the
junction
temperature exceeds the threshold value
(typically 160°C), the converter shuts off. This is
a latch-off protection. Enable the part by
recycling the power of VCC or EN.
Output Voltage Setting and Remote Output
Voltage Sensing
First choose a value for R1. Then R2 can be
determined with Equation (5):
VREF
R2 (k )
R1(k)
VO VREF
(5)
To optimize the load transient response, a feedforward capacitor (CFF) is recommended in
parallel with R1. R1 and CFF add an extra zero
to the system, which improves loop response.
R1 and CFF are selected so that the zero
formed by R1 and CFF is located around
20kHz ~ 60kHz. See Equation (6):
1
2 R1 CFF
When VFB drops to 80% of VREF or exceeds
116% of the nominal VREF, PGOOD is latched
low. PGOOD can only be pulled high again
after a new soft start.
If the input supply fails to power the MPQ8634A,
PGOOD is clamped low, even though PGOOD
is tied to an external DC source through a pullup resistor. The relationship between the
PGOOD voltage and the pull-up current is
shown in Figure 5.
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.6
Where VREF is 900mV.
fZ
Power Good (PGOOD)
The MPQ8634A has a power good (PGOOD)
output. PGOOD is the open-drain of a MOSFET.
Connect PGOOD to VCC or another external
voltage source (less than 3.6V) through a pullup resistor (typically 10kΩ). After applying the
input voltage, the MOSFET turns on, so
PGOOD is pulled to GND before TRK/REF is
ready. After VFB reaches 92.5% of VREF,
PGOOD is pulled high after 0.8ms of delay.
I_PG( mA)
If VFB exceeds 116% of VREF, the device enters
latch-off OVP mode. The HS-FET latches off
and PGOOD latches low until the power of VCC
or EN is recycled. Meanwhile, the LS-FET
remains on until it reaches the low-side
negative current limit (NOCP). Once it hits
NOCP, the LS-FET is momentarily turned off for
200ns and is then turned on again. The
MPQ8634A maintains this operation to bring
down the output voltage. When VFB drops below
50% of VREF, the LS-FET is turned off for pulseskip mode and keeps turning on for forced CCM
operation. If VFB rises back to more than 116%
of VREF, the LS-FET turns on again with NOCP
until VFB drops back below 50% of VREF. The
power of EN or VIN must be recycled to clear
the OVP fault.
0.7
0.8
0.9
V_PG(V)
Figure 5: PGOOD Clamped Voltage vs. Pull-Up
Current
Enable (EN) Configuration
The MPQ8634A turns on when EN goes high.
The MPQ8634A turns off when EN goes low.
EN cannot be left floating for proper operation.
EN can be driven by an analog or digital control
logic signal to enable or disable the MPQ8634A.
(6)
MPQ8634A Rev. 1.02
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
The MPQ8634A provides accurate EN
thresholds, so a resistor divider from VIN to
AGND can be used to program the input
voltage at which the MPQ8634A is enabled.
This is highly recommended for applications
where there is no dedicated EN control logic
signal to avoid possible UVLO bouncing during
power-up and power-down. The resistor divider
values can be determined with Equation (7):
VIN _ START ( V ) VIHEN
R UP R DOWN
R DOWN
RUP and RDOWN should be chosen so that the
EN voltage (VEN) does not exceed 3.6V when
VIN reaches the maximum value.
EN can also be connected to VIN directly
through a pull-up resistor (RUP). RUP should be
chosen so that the maximum current going to
EN is 50µA. RUP can be calculated with
Equation (8):
R UP (K)
(7)
VINMAX ( V )
0.05(mA )
(8)
Where VIHEN is 1.22V, typically.
MPQ8634A Rev. 1.02
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
APPLICATION INFORMATION
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the step-down
converter while maintaining the DC input
voltage. Use ceramic capacitors for the best
performance. During layout, place the input
capacitors as close to VIN as possible.
The capacitance can vary significantly with the
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over a wide temperature
range and offer very low ESR.
The capacitors must have a ripple current rating
that exceeds the converter’s maximum input
ripple current. Estimate the input ripple current
with Equation (9):
ICIN
VOUT
V
IOUT
(1 OUT )
VIN
VIN
VOUT
VOUT
V
1
)
(1 OUT ) (RESR
VIN
8 FSW COUT
FSW L
For simplification, choose an input capacitor
with an RMS current rating that exceeds half
the maximum load current. The input capacitor
value determines the converter input voltage
ripple. If there is an input voltage ripple
requirement in the system, select an input
capacitor that meets the specification.
Estimate the input voltage ripple with Equation
(11):
(13)
When
using
ceramic
capacitors,
the
capacitance dominates the impedance at the
switching frequency. The capacitance also
dominates the output voltage ripple. For
simplification, estimate the output voltage ripple
with Equation (14):
VOUT
VOUT
V
(1 OUT ) (14)
2
8 FSW L COUT
VIN
The ESR dominates the switching frequency
impedance for the POSCAP capacitors. For
simplification, the output ripple can be
approximated with Equation (15):
VOUT
(9)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (10):
I
ICIN OUT
(10)
2
IOUT
V
V
OUT (1 OUT )
FSW CIN
VIN
VIN
Estimate the output voltage ripple with Equation
(13):
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(15)
Selecting the Inductor
The inductor supplies constant current to the
output load while being driven by the switching
input voltage. A larger-value inductor results in
less ripple current and a lower output ripple
voltage, but also has a larger physical size,
higher series resistance, and lower saturation
current. Select an inductor value that allows the
inductor peak-to-peak ripple current to be 30 40% of the maximum switch current limit. Also
design for a peak inductor current that is below
the maximum switch current limit. Calculate the
inductance value using Equation (16):
L
VOUT
V
(1 OUT )
FSW IL
VIN
(16)
(11)
Where ∆IL is the peak-to-peak inductor ripple
current.
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (12):
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated with
Equation (17):
VIN
VIN
IOUT
1
4 FSW CIN
(12)
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Use POSCAP or ceramic capacitors.
ILP IOUT
VOUT
V
(1 OUT )
2 FSW L
VIN
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(17)
18
MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
6. Connect AGND and PGND at the point of
the VCC capacitor's ground connection.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For optimal performance, refer to
Figure 6 and follow the guidelines below.
1. Place the input MLCC capacitors as close to
VIN and PGND as possible.
7. Place the BST capacitor as close to BST
and SW as possible with 20 mil or wider
traces to route the path. It is recommended
to use a bootstrap capacitor of 0.1μF to 1μF.
2. Place the major MLCC capacitors on the
same layer as the MPQ8634A.
8. Place the REF capacitor close to TRK/REF
to VSNS-.
3. Maximize the VIN and PGND copper plane
to minimize parasitic impedance.
9. Place via at least 10mm away from the
positive side of the first input decoupling
capacitor close to the IC if it must be placed
on the PGOOD pad.
4. Place as many PGND vias as possible as
close to PGND as possible to minimize both
parasitic impedance and thermal resistance.
10. Place the OSENSE capacitor in between
the output sense lines and close to the
device.
5. Place the VCC decoupling capacitor close
to the device.
Cosense
RFB1
CFF
CSS1
REF/TRK
MODE
CS
AGND
BST
5
4
3
2
1
15
16
17
18
19
PGND
PGND
PGND
PGND
PGND
CIN3
PGND
14
PGND
PGND
13
12
6
11
7
8
FB
EN
9
VSNS-
PGOOD
21
VIN
20
SW
10
VIN
CIN2
CIN1
VCC
Figure 6: Recommended PCB Layout
MPQ8634A Rev. 1.02
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11/12/2018
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MPQ8634A – 16V, 20A, SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT,
PROGRAMMBALE FREQUENCY, AND VOLTAGE TRACKING
PACKAGE INFORMATION
QFN-21 (3mmx4mm)
PIN 1 ID
0.15 X 45° TYP
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.15 X 45°
NOTE:
1) LAND PATTERN OF PIN1,9,10,11,19,20 AND
21 HAVE THE SAME WIDTH.
2) ALL DIMENSIONS ARE IN MILLIMETERS.
3) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ8634A Rev. 1.02
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11/12/2018
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