MPQ8636A-10
High Efficiency, 10A, 18V
Synchronous, Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MPQ8636A-10 is a fully-integrated, highfrequency, synchronous, rectified, step-down,
switch-mode converter. It offers a very compact
solution to achieve 10A output current over a wide
input supply range, with excellent load and line
regulation. The MPQ8636A-10 operates at high
efficiency over a wide output-current–load range.
•
•
•
The MPQ8636A-10 uses Constant-On-Time
(COT) control to provide a fast transient response
and ease loop stabilization.
An external resistor programs the operating
frequency from 200kHz to 1MHz, and the
frequency keeps nearly constant as input
supply
varies
with
the
feed-forward
compensation.
The default under-voltage lockout threshold is
internally set at 4.1V, but a resistor network on
the enable pin can increase this threshold. The
soft-start pin controls the output-voltage startup
ramp. An open-drain power-good signal
indicates that the output is within nominal
voltage range.
It has fully-integrated protection features that
include over-current protection, over-voltage
protection and thermal shutdown.
The MPQ8636A-10 requires a minimal number of
readily-available standard external components
and is available in a 16-Pin QFN 3mm×4mm
package.
•
•
•
•
•
•
•
•
Wide 4.5V-to-18V Operating Input Range
10A Output Current
Optimal Low RDS(ON) Internal Power
MOSFETs Per Device
Proprietary Switching-Loss–Reduction
Technique
Adaptive COT for Ultrafast Transient
Response
0.5% Reference Voltage Over 0°C to 70°C
Junction Temperature Range
Programmable Soft-Start Time
Pre-Bias Start-Up
Programmable Switching Frequency from
200kHz to 1MHz
OCP, OVP and Thermal Shutdown
Output Adjustable from 0.611V to 13V
APPLICATIONS
•
•
•
•
•
•
Telecom and Networking Systems
Base Stations
Servers
Personal Video Recorders
Flat-Panel Televisions and Monitors
Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number
Package
Top Marking
MPQ8636AGLE-10*
QFN-16(3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MPQ8636AGLE-10–Z):
TOP MARKING
MP: MPS prefix;
Y: year code;
W: week code:
8636: first four digits of the part number;
A: fifth digit of the part number;
LLL: lot number;
E: package type suffix;
10: part no, suffix
PACKAGE REFERENCE
TOP VIEW
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
(5)
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply Voltage VIN ....................................... 21V
VSW ........................................-0.3V to VIN + 0.3V
VSW (30ns)...................................-3V to VIN + 3V
VBST ...................................................... VSW + 6V
VBST (30ns) ........................................ VSW + 6.5V
Enable Current IEN(2)................................ 2.5mA
All Other Pins .................................–0.3V to +6V
(3)
Continuous Power Dissipation (TA=+25°)
QFN3X4……………………….…..…………2.7W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to the section “Configuring the EN Control”.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions
θJA
θJC
QFN-16 (3mmx4mm) ..............46 ....... 9 .... °C/W
(4)
Supply Voltage VIN ...........................4.5V to 18V
Output Voltage VOUT .....................0.611V to 13V
Enable Current IEN....................................... 1mA
Operating Junction Temp. (TJ). -40°C to +125°C
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
0
1
μA
860
1000
μA
Supply Current
Supply Current (Shutdown)
IIN
VEN = 0V
Supply Current (Quiescent)
IIN
VEN = 2V, VFB = 1V
MOSFET
High-Side Switch-On
Resistance
Low-Side Switch-On Resistance
Switch Leakage
700
HSRDS-ON
19.6
mΩ
LSRDS-ON
7.8
mΩ
SWLKG
VEN = 0V, VSW = 0V or 12V
0
10
μA
Current Limit
High-Side Peak Current Limit
Low-Side Valley Current Limit
Low-Side Negative Current
Limit(6)
(6)
ILIMIT_PEAK
13
17.3
21.6
A
ILIMIT_VALLEY
9.5
11
12.5
A
ILIMIT_NEGATIVE
-6.5
-5
-4.5
A
Timer
One-Shot ON Time
Minimum On Time
(6)
Minimum OFF Time(6)
τON
RFREQ=453kΩ, VOUT=1.2V
250
ns
τON_MIN
20
30
40
ns
τOFF_MIN
50
100
150
ns
VOVP_LATCH
127%
130%
133%
VFB
VUVP
47%
50%
53%
VFB
TJ = 0°C to +70°C
608
611
614
mV
TJ = 0°C to +125°C
605
611
617
mV
TJ = -40°C to +125°C
602
611
620
mV
Over-Voltage and Under-Voltage Protection
OVP Latch Threshold(6)
UVP Threshold
(6)
Reference and Soft Start
Reference Voltage
VREF
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Feedback Current
Soft Start Charging Current
Symbol
IFB
ISS
Condition
VFB = 611mV
VSS=0V
Min
16
Typ
50
20
Max
100
25
Units
nA
μA
1.3
250
0
0
1.5
V
mV
Enable And UVLO
Enable Input, Low Voltage
Enable, Hysteresis
Enable, Input Current
VILEN
VEN-HYS
IEN
1.1
VEN = 2V
VEN = 0V
μA
VCC Regulator
VCC Under-Voltage Lockout,
Threshold Rising
VCC Under-Voltage Lockout,
Threshold Hysteresis
VCC Regulator
VCC Load Regulation
Power-Good
Power-Good, Rising Threshold
Power-Good, Falling Threshold
Power-Good, Low-to High-Delay
Power Good, Sink Current
Capability
Power Good, Leakage Current
VCCVth
4.0
V
VCCHYS
500
mV
VCC
5.0
0.5
V
%
Icc=5mA
PGVth-Hi
PGVth-Lo
PGTd
87%
IOL
VOL=600mA
IPG_LEAK
VPG = 3.3V
91%
80%
2.5
94%
VFB
VFB
ms
12
mA
10
nA
25
°C
°C
Thermal Protection
Thermal Shutdown(6)
Thermal Shutdown, Hysteresis
TSD
150
Note:
6) Guaranteed by design.
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
MPQ8636A-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25°C, unless otherwise noted.
Supply Current (Shutdown)
vs. Input Voltage
2
Supply Current (Quiescent)
vs. Input Voltage
EN= 0V
1000
SS Charge Current vs.
Temperature
EN= 2V, VFB= 1V
25
TJ=125°C
TJ=25°C
1.5
800
TJ=125°C
1
TJ=-40°C
600
TJ=-40°C
5
10
15
20
400
25
0
INPUT VOLTAGE (V)
15
20
10
-50
25
EN THRESHOLD (V)
7
4
50
100
PG RISING DELAY (ms)
Rising_Threshold
90
80
Falling_Threshold
70
100
1
150
Rising_Threshold
Falling_Threshold
0.5
3
100
50
1.5
0
-50
150
PG Threshold vs.
Temperature
0
50
100
150
5
2
0
0
VCC UVLO Threshold vs.
Temperature
EN Threshold vs.
Temperature
EN= 2V
60
-50
10
INPUT VOLTAGE (V)
EN Leakage Current vs.
Temperature
1
-50
5
VCC UVLO THRESHOLD (V)
0
0
EN LEAKAGE CURRENT (nA)
15
TJ=25°C
0.5
10
20
0
50
100
150
4
3
2
-50
Rising_Threshold
Falling_Threshold
0
50
100
150
PG Rising Delay vs.
Temperature
2.5
2
1.5
1
-50
0
50
100
150
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS (continued)
MPQ8636A-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25°C, unless otherwise noted.
20
15
5
18
13
4.8
16
11
4.6
14
9
4.4
12
7
4.2
10
0
5
10
15
20
25
5
0
5
10
15
20
25
4
-50
5
700
1100
4.8
600
900
4.6
500
700
4.4
400
500
4.2
300
300
4
-50
0
50
100
150
200
-50
600
35
500
30
0
50
100
150
100
100
0
300
50
500
100
700
150
900
25
400
20
300
15
200
10
100
0
5
1
3
5
7
9
0
0
2
4
6
8
10
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
95
95
1980
90
90
1585
85
1190
80
795
75
400
EFFICIENCY (%)
EFFICIENCY (%)
MPQ8636A-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25°C, unless otherwise noted.
85
80
75
70
1
2
3
4
5
6
7
8
9 10
70
1
2
OUTPUT CURRENT (A)
3
4
5
6
7
8
9 10
5
1
OUTPUT CURRENT (A)
2
3
4
5
6
7
8
9 10
OUTPUT CURRENT (A)
Load Regulation vs.
Output Current
100
1980
0.4
0.3
95
1585
0.2
90
1190
0.1
85
795
0
-0.1
80
-0.2
400
75
5
1
2
3 4 5 6 7 8 9 10
OUTPUT CURRENT (A)
70
1
-0.3
2
3 4 5 6 7 8 9 10
OUTPUT CURRENT (A)
-0.4
0
2
4
6
8
OUTPUT CURRENT (A)
10
Line Regulation vs.
Input Voltage
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
0
5
10
15
INPUT VOLTAGE (V)
20
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8636A-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
Dead Time (on)
Dead Time (off)
Input/Output Voltage Ripple
IOUT = 10A
IOUT = 10A
IOUT = 0A
VOUT (AC)
20mV/div.
VIN (AC)
20mV/div.
SW
2V/div.
SW
10V/div.
SW
2V/div.
IL
2A/div.
Input/Output Voltage Ripple
IOUT = 10A
VOUT (AC)
20mV/div.
Power Good
through EN Start Up
Power Good
through EN Shutdown
IOUT = 0.5A, CSS = 33nF,
IOUT = 0.5A, CSS = 33nF,
EN
5V/div.
EN
5V/div.
SW
10V/div.
VOUT
500mV/div.
VOUT
500mV/div.
IL
10A/div.
PG
5V/div.
PG
5V/div.
VIN (AC)
100mV/div.
Start Up Through VIN
Start Up Through VIN
VOUT
500mV/div.
VIN
5V/div.
SW
10V/div.
IL
2A/div.
Shutdown Through VIN
IOUT = 0A
IOUT = 10A
IOUT = 0A
VOUT
500mV/div.
VIN
10V/div.
SW
10V/div.
IL
10A/div.
VOUT
500mV/div.
VIN
5V/div.
SW
10V/div.
IL
2A/div.
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8636AGLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
Shutdown Through VIN
IOUT = 10A
Start up through EN
Start up through EN
IOUT = 0A
IOUT = 10A
VOUT
1V/div.
VOUT
500mV/div.
VOUT
500mV/div.
EN
5V/div.
VIN
5V/div.
SW
10V/div.
EN
5V/div.
SW
10V/div.
SW
10V/div.
IL
2A/div.
IL
10A/div.
IL
10A/div.
Shutdown Through EN
Shutdown Through EN
IOUT = 0A
IOUT = 10A
VOUT
1V/div.
VOUT
500mV/div.
VOUT (AC)
100mV/div.
EN
5V/div.
EN
5V/div.
SW
10V/div.
SW
10V/div.
IL
2A/div.
IL
10A/div.
IL
5A/div.
Thermal Shutdown
Thermal Recovery
IOUT = 0A
IOUT = 0A
VOUT
500mV/div.
VOUT
500mV/div.
SW
10V/div.
SW
10V/div.
IL
2A/div.
IL
2A/div.
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
PIN FUNCTIONS
PIN #
Name
1
EN
2
FREQ
3
FB
4
SS
5
AGND
6
PG
7
VCC
8
BST
9, 14
IN
10, 11, 12,
13
PGND
15, 16
SW
Description
Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the
regulator; drive it low to turn it off. Connect EN to IN through a pull-up resistor or a
resistive voltage divider for automatic startup. Do not float this pin.
Frequency Set. Require a resistor connected between FREQ and IN to set the switching
frequency. The input voltage and the resistor connected to the FREQ pin determine the
ON time. The connection to the IN pin provides line feed-forward and stabilizes the
frequency during input voltage’s variation.
Feedback. Connect to the tap of an external resistor divider from the output to GND to
set the output voltage. FB is also configured to realize over-voltage protection (OVP) by
monitoring output voltage. MPQ8636A-10 provide Latch-OFF OVP mode. Please refer to
the section “Over-Voltage-Protection (OVP)”. Place the resistor divider as close to FB
pin as possible. Avoid using vias on the FB traces.
Soft-Start. Connect an external capacitor to program the soft start time for the switch
mode regulator.
Analog Ground. The control circuit reference.
Power-Good. The output is an open drain signal. Requires a pull-up resistor to a DC
voltage to indicate HIGH if the output voltage exceeds 91% of the nominal voltage.
There is a delay from FB ≥ 91% to when PG goes high.
Internal 5V LDO Output. Powers the driver and control circuits. Decouple with a ≥1µF
ceramic capacitor as close to the pin as possible. For best results, use X7R or X5R
dielectric ceramic capacitors for their stable temperature characteristics.
Bootstrap. Require a capacitor connected between SW and BST pins to form a floating
supply across the high-side switch driver.
Supply Voltage. Supplies power to the internal MOSFET and regulator. The MPQ8636A10 operates from a 4.5V-to-18V input rail. Requires an input decoupling capacitor.
Connect using wide PCB traces and multiple vias.
System Ground. Reference ground of the regulated output voltage. PCB layout requires
extra care. Connect using wide PCB traces.
Switch Output. Connect to the inductor and bootstrap capacitor. The high-side switch
drives the pin up to the VIN during the PWM duty cycle’s ON time. The inductor current
drives the SW pin negative during the OFF-time. The low-side switch’s ON-resistance
and the internal Schottky diode clamp the negative voltage. Connect using wide PCB
traces.
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 1— Functional Block Diagram
MPQ8636A-10 Rev. 1.01
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
OPERATION
The MPQ8636A-10 is a fully-integrated,
synchronous, rectified, step-down, switch-mode
converter. It uses constant-on-time (COT) control
to provide a fast transient response and ease
loop stabilization.
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns ON when the feedback
voltage (VFB) drops below the reference voltage
(VREF), which indicates an insufficient output
voltage. The input voltage and the frequency-set
resistor determine the ON period as follows:
6.1× RFREQ (kΩ )
τON (ns) =
VIN (V) − 0.4
(1)
After the ON period elapses, the HS-FET turns
off. It turns ON again when VFB drops below
VREF. By repeating this operation, the converter
regulates the output voltage. The integrated lowside MOSFET (LS-FET) turns on when the HSFET is OFF to minimize the conduction loss.
There is a dead short (or shoot-through) between
input and GND if both HS-FET and LS-FET turn
on at the same time. A dead-time (DT) internally
generated between HS-FET OFF and LS-FET
ON, or LS-FET OFF and HS-FET ON avoids
shoot-through.
PWM Operation
MPQ8636A-10 always functions in continuousconduction mode (CCM), meaning the inductor
current can go negative in light-load conditions.
Figure 2 shows CCM operation. When VFB is
below VREF, HS-FET turns on for a fixed interval
determined by the one- shot on-timer, as per
equation 1. When the HS-FET turns off, the LSFET turns on until the next period.
In CCM operation, the switching frequency is
fairly constant and is also called PWM mode.
Switching Frequency
Selecting the switching frequency requires
trading off between efficiency and component
size.
Low-frequency
operation
increases
efficiency by reducing MOSFET switching losses,
but requires larger inductor and capacitor values
to minimize the output voltage ripple.
For MPQ8636A-10，set the ON time using the
FREQ pin to set the frequency for steady-state
operation on CCM.
The MPQ8636A-10 uses adaptive constant-ontime (COT) control, though the IC lacks a
dedicated oscillator. Connect the FREQ pin to
the IN pin through the resistor (RFREQ) so that the
input voltage is feed-forwarded to the one-shot
ON-time timer. When operating in steady state at
CCM, the duty ratio stays at VOUT/VIN, so the
switching frequency is fairly constant over the
input voltage range. Set the switching frequency
as follows:
fSW (kHz) =
106
6.1× RFREQ (kΩ) VIN (V)
×
+ τDELAY (ns)
VIN (V) − 0.4
VOUT (V)
(2)
Where τDELAY is the comparator delay of about
5ns.
Typically, the MPQ8636A-10 is set to 200kHz to
1MHz applications. It is optimized to operate at
high switching frequencies at high efficiency: high
switching frequencies allow for physically smaller
LC filter components to reduce the PCB footprint.
Jitter and FB Ramp Slope
Figure 3 shows jitter occurring in PWM mode.
When there is noise on the VFB descending slope,
the HS-FET ON time deviates from its intended
point and produces jitter, and influences system
stability. The VFB ripple’s slope steepness
dominates the noise immunity, though its
magnitude has no direct effect.
Figure 2—PWM Operation
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
VOUT
L
SW
R4
C4
IR4
IC4
R9
R1
IFB
Ceramic
FB
Figure 5—Simplified Circuit in PWM Mode with
External Ramp Compensation
Figure 3—Jitter in PWM Mode
Ramp with a Large ESR Capacitor
Using POSCAPs or other large-ESR capacitors
as the output capacitor results in the ESR ripple
dominating the output ripple . The ESR also
significantly influences the VFB slope. Figure 4
shows the simplified equivalent circuit in PWM
mode with the HS-FET OFF and without an
external ramp circuit.
SW
L
FB
Figure 5 shows the simplified equivalent circuit in
PWM mode with the HS-FET OFF and an
external ramp compensation circuit (R4, C4).
Design the external ramp based on the inductor
ripple current. Select C4, R9, R1 and R2 to meet
the following condition:
1
2π × f SW × C4
(4)
(5)
Then estimate the ramp on VFB as:
POSCAP
VRAMP =
R2
Figure 4—Simplified Circuit in PWM Mode without
External Ramp Compensation
(3)
Where τSW is the switching period.
Ramp with a Small ESR Capacitor
Use an external ramp when using ceramic output
capacitors because the ESR ripple is not high
enough to stabilize the system.
VIN − VOUT
⎛ R1//R2 ⎞ (6)
× τ ON × ⎜
⎟
R4 × C4
⎝ R1//R2 + R9 ⎠
The descending slope of the VFB ripple then
follows:
To realize the stability without an external ramp,
usually select the ESR value as follows:
R ESR
1 ⎛ R1× R2
⎞
+ R9 ⎟
×⎜
5 ⎝ R1 + R2
⎠
IR 4 = IC 4 + IFB ≈ IC 4
ESR
τ SW
τ
+ ON
2
≥ 0.7 × π
C OUT
<
Where:
VOUT
R1
R2
VSLOPE =
− VOUT
VRAMP
=
τ OFF
R4 × C4
(7)
Equation 7 shows that if there is instability in
PWM mode, reduce either R4 or C4. If C4 is
irreducible due to equation 4 limitations, then
reduce R4. For a stable PWM operation, design
Vslope based on equation 8.
− VSLOPE
τSW
τ
+ ON − RESR × COUT
I × 10-3
0.7
×
π
2
≥
× VOUT + OUT
2 × L × COUT
τSW − τON
(8)
Where IOUT is the load current.
Configuring the EN Control
The regulator turns on when EN goes high;
conversely it turns off when EN goes low. Do not
float the pin.
For automatic start-up. pull the EN pin up to input
voltage through a resistive voltage divider.
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
Choose the values of the pull-up resistor (RUP
from the IN pin to the EN pin) and the pull-down
resistor (RDOWN from the EN pin to GND) to
determine the automatic start-up voltage:
VIN−START = 1.5 ×
(RUP + RDOWN )
(V)
RDOWN
(9)
For example, for RUP=100kΩ and RDOWN=51kΩ,
the VIN-START is set at 4. 44V.
To reduce noise, add a 10nF ceramic capacitor
from EN to GND.
An internal zener diode on the EN pin clamps the
EN pin voltage to prevent runaway. The
maximum pull-up current, assuming the worstcase 6V, for the internal zener clamp should be
less than 1mA.
Therefore, when driving EN with an external logic
signal, use an EN voltage less than 6V. When
connecting EN to IN through a pull-up resistor or
a resistive voltage divider, select a resistance
that ensures a maximum pull-up current of less
than 1mA.
If using a resistive voltage divider and VIN
exceeds 6V, then the minimum resistance for the
pull-up resistor, RUP, should meet:
VIN − 6V
6V
−
≤ 1mA
RUP
RDOWN
(10)
With only RUP (the pull-down resistor, RDOWN, is
not connected), then the VCC UVLO threshold
determines VIN-START, so the minimum resistor
value is:
RUP ≥
VIN − 6V
(Ω)
1mA
(11)
A typical pull-up resistor is 100kΩ.
Soft Start
The MPQ8636A-10 employs a soft start (SS)
mechanism to ensure a smooth output during
power-up. When the EN pin goes HIGH, an
internal current source (20μA) charges the SS
capacitor. The SS capacitor voltage overtakes
the REF voltage to the PWM comparator. The
output voltage smoothly ramps up with the SS
voltage. Once the SS voltage reaches the REF
voltage, it continues ramping up while VREF takes
over the PWM comparator. At this point, soft-start
finishes and the device enters steady-state
operation.
Determine the SS capacitor value as follows:
CSS ( nF ) =
τSS ( ms ) × ISS ( μA )
VREF ( V )
(12)
If the output capacitors are large, then avoid
setting a short SS time or risk hitting the current
limit during SS. Use a minimum value of 4.7nF if
the output capacitance value exceeds 330μF.
Pre-Bias Startup
The MPQ8636A-10 has been designed for
monotonic startup into pre-biased loads. If the
output is pre-biased to a certain voltage during
startup, the IC will disable switching for both
high-side and low-side switches until the voltage
on the soft-start capacitor exceeds the sensed
output voltage at the FB pin.
Power Good (PG)
The MPQ8636A-10 has a power-good (PG)
output. The PG pin is the open drain of a
MOSFET. Connect it to VCC or some other
voltage source that measures less than 5.5V
through a pull-up resistor (typically 100kΩ). After
applying the input voltage, the MOSFET turns on
so that the PG pin is pulled to GND before the
SS is ready. After the FB voltage reaches 91% of
the REF voltage, the PG pin is pulled HIGH after
a 2.5ms delay.
When the FB voltage drops to 80% of the REF
voltage or exceeds 120% of the nominal REF
voltage, the PG pin is pulled LOW. If the input
DC source fails to power the MPQ8636A-10, the
PG pin is also pulled low even though this pin is
tied to an external DC source through a pull-up
resistor (typically 100kΩ).
Over-Current Protection (OCP)
The MPQ8636A-10 features three current-limit
levels for over-current conditions: high-side peak
current limit, low-side valley current limit and lowside negative current limit.
High-Side Peak Current Limit: The part has a
cycle-by-cycle over-current limiting function. The
device monitors the inductor current during the
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
HS-FET ON state. When the sensed inductor
current hits the peak current limit, the output of
over-current comparator goes high, the device
enters OCP mode immediately and turns off the
HS-FET and turns on the LS-FET.
Low-Side Valley Current Limit: The device also
monitors the inductor current during the LS-FET
ON state. When ILIM=1 and at the end of the
OFF time, the LS-FET sourcing current is
compared to the internal positive-valley–current
limit. If the valley current limit is less than the LSFET sourcing current, the HS-FET remains OFF
and the LS-FET remains ON for the next ON time.
When the LS-FET sourcing current drops below
the valley current limit, the HS-FET turns on
again.
In an over-current condition, the load current
exceeds the current to the output capacitor; thus
the output voltage tends to fall off. Eventually, it
will end up with crossing the under voltage
protection threshold and latch off.
Low-Side Negative Current Limit: If the sensed
LS-FET negative current exceeds the negative
current limit, the LS-FET turns off immediately
and stays OFF for the remainder of the OFF
period. In this situation, both MOSFETs are OFF
until the end of a fixed interval. The HS-FET body
diode conducts the inductor current for the fixed
time.
Over/Under-Voltage Protection (OVP/UVP)
The MPQ8636A-10 monitors the output voltage
using the FB pin connected to the tap of a
resistor divider to detect output over-voltage. If
the FB voltage exceeds the nominal REF voltage
but remains lower than 120% of the REF voltage
(0.611V), both MOSFETs are off.
If the FB voltage exceeds 120% of the REF
voltage but remains below 130%, the LS-FET
turns on while the HS-FET remains off. The LSFET remains on until the FB voltage drops below
110% of the REF voltage or the low-side
negative current limit is hit.
If the FB voltage exceeds 130% of the REF
voltage, then the device is latched off. Need
cycle the input power supply or EN to restart.
If the FB voltage becomes lower than 50% of the
REF voltage, the UVP comparator output goes
high; then the device is latched off. Need cycle
the input power supply or EN to restart.
UVLO Protection
The MPQ8636A-10 has under-voltage lockout
protection (UVLO). When the VCC voltage
exceeds the UVLO rising-threshold voltage, the
MPQ8636A-10 powers up. It shuts off when the
VCC voltage falls below the UVLO falling
threshold voltage. This is non-latch protection.
The MPQ8636A-10 is disabled when the VCC
voltage falls below 3.3 V. If an application
requires a higher UVLO threshold, use the two
external resistors connected to the EN pin as
shown in Figure 6 to adjust the startup input
voltage. For best results, use the enable resistors
to set the input-voltage falling threshold (VSTOP)
above 3.6V. Set the rising threshold (VSTART) to
provide enough hysteresis to account for any
input supply variations.
IN
R UP
R DOWN
EN Comparator
EN
Figure 6—Adjustable UVLO Threshold
Thermal Shutdown
The MPQ8636A-10 has thermal shutdown. The
IC internally monitors the junction temperature. If
the junction temperature exceeds the threshold
value (minimum 150°C), the converter shuts off.
This is a non-latch protection. There is about
25°C hysteresis. Once the junction temperature
drops to about 125°C, it initiates a soft startup.
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16
MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
APPLICATION INFORMATION
Selecting the Output-Voltage-Large-ESR
Capacitors
For applications that electrolytic capacitor or POS
capacitor with a large ESR is set as output
capacitors. The feedback resistors—R1 and R2,
as shown in Figure 7—set the output voltage.
SW
POSCAP
Figure 7—Simplified POSCAP Circuit
First, choose a value for R2 that balances
between high quiescent current loss (low R2) and
high noise sensitivity on FB (high R2). A typical
value falls within 5kΩ to 50kΩ, using a
comparatively larger R2 when VOUT is low, and a
smaller R2 when VOUT is high. Then calculate R1
as follows, which considers the output ripple:
1
× ΔVOUT − VREF
2
× R2
VREF
Selecting the Output-Voltage Small-ESR
Capacitors
FB
R4
VOUT
C4
R9
R2
−
R4 + R9
(14)
For PWM operation, estimate VFB(AVG) from
equation 15.
VFB( AVG ) = VREF +
R1
R9 <
R1 =
When using a low-ESR ceramic capacitor on the
output, add an external voltage ramp to the FB
pin consisting of R4 and C4. The ramp voltage,
VRAMP, and the resistor divider influence the
output voltage, as shown in Figure 8. Calculate
VRAMP as shown in equation 6. Select R2 to
1
× VRAMP
2
× R2
1
+ × VRAMP
2
VOUT − VREF −
VREF
Figure 8—Simplified Ceramic Capacitor Circuit
1 R1× R2
×
5 R1 + R2
(16)
Using equations 14 and 15 to calculate the
output voltage can be complicated. To simplify
the R1 calculation in equation 14, add a DCblocking capacitor, CDC, to filter the DC influence
from R4 and R9. Figure 9 shows a simplified
circuit with external ramp compensation and a
DC-blocking capacitor. The addition of this
capacitor, simplifies the R1 calculation as per
equation 17 for PWM mode operation.
Ceramic
R2
1
R1 // R2
(15)
× VRAMP ×
2
R1 // R2 + R9
Usually, R9 is 0Ω, though it can also be set
following equation 16 for better noise immunity. It
should also be less than 20% of R1//R2 to
minimize its influence on VRAMP.
(13)
Where ΔVOUT is the output ripple determined by
equation 22.
L
VFB(AVG)
Where VFB(AVG) is the average FB voltage. VFB(AVG)
varies with the VIN, VOUT, and load condition,
where the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG); improving the load or line regulation
involves a lower VRAMP that meets equation 8.
R2
VOUT −
R2
VOUT − VFB(AVG)
ESR
R1
SW
R1 =
VOUT
L
FB
R1 =
balance between high quiescent current loss and
FB noise sensitivity. Choose R2 within 5kΩ to
50kΩ, using a larger R2 when VOUT is low, and a
smaller R2 when VOUT is high. Determine the
value of R1 as follows:
(17)
For best results, select a CDC value at least
10×C4 for better DC-blocking performance, but
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
smaller than 0.47µF to account for start-up
performance. To use a larger CDC for better FB
noise immunity, reduce R1 and R2 to limit effects
on system start-up. Note that even with CDC, the
load and line regulation are still related to VRAMP.
SW
FB
L
R4
VOUT
C4
The worst-case condition occurs at VIN = 2VOUT,
where:
IOUT
1
×
4 f SW × CIN
The output capacitor maintains the DC output
voltage. Use ceramic capacitors or POSCAPs.
Estimate the output voltage ripple as:
Figure 9—Simplified Ceramic Capacitor Circuit
with DC-Blocking Capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore, requires a
capacitor to supply the AC current to the stepdown converter while maintaining the DC input
voltage. Use ceramic capacitors for best
performance. During layout, place the input
capacitors as close to the IN pin as possible.
The capacitance can vary significantly with
temperature. Use capacitors with X5R and X7R
ceramic dielectrics because they are fairly stable
over a wide temperature range.
The capacitors must also have a ripple current
rating that exceeds the converter’s maximum
input ripple current. Estimate the input ripple
current as follows:
VOUT
V
× (1 − OUT )
VIN
VIN
(21)
Output Capacitor
Ceramic
(18)
The worst-case condition occurs at VIN = 2VOUT,
where:
I
= OUT
2
IOUT
V
V
× OUT × (1 − OUT ) (20)
fSW × CIN VIN
VIN
ΔVIN =
R2
ICIN
ΔVIN =
R1
C DC
ICIN = IOUT ×
Estimate the input voltage ripple as follows:
ΔVOUT =
VOUT
V
1
× (1 − OUT ) × (R ESR +
) (22)
f SW × L
VIN
8 × f SW × C OUT
When using ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The capacitance also dominates the
output voltage ripple. For simplification, estimate
the output voltage ripple as:
ΔVOUT =
VOUT
8 × fSW × L × C OUT
For simplification, choose an input capacitor with
an RMS current rating that exceeds half the
maximum load current.
× (1 −
VOUT
) (23)
VIN
The ESR only contributes minimally to the output
voltage ripple, thus requiring an external ramp to
stabilize the system. Design the external ramp
with R4 and C4 as per equations 4, 7 and 8.
The ESR dominates the switching-frequency
impedence for POSCAPs. The ESR ramp
voltage is high enough to stabilize the system,
thus eliminating the need for an external ramp.
Select a minimum ESR value around 12mΩ to
ensure
stable
converter
operation.
For
simplification, the output ripple can be
approximated as:
ΔVOUT =
(19)
2
VOUT
V
× (1 − OUT ) × R ESR
f SW × L
VIN
(24)
Inductor
The inductor supplies constant current to the
output load while being driven by the switching
input voltage. A larger-value inductor results in
The input capacitance value determines the
converter input voltage ripple. Select a capacitor
value that meets any input-voltage–ripple
requirements.
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
less ripple current and lower output-ripple voltage,
but is larger physical size, has a higher series
resistance, and/or lower saturation current.
Generally, select an inductor value that allows
the inductor peak-to-peak ripple current to equal
30% to 40% of the maximum switch current limit.
Also, design for a peak inductor current that is
below the maximum switch current limit. The
inductance value can be calculated as:
VOUT
V
L=
× (1 − OUT )
f SW × ΔIL
VIN
(25)
Where ΔIL is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
ILP = IOUT +
VOUT
V
× (1 − OUT )
2 × f SW × L
VIN
(26)
Table 1 lists a few highly-recommended highefficiency inductors.
Table 1—Inductor Selector Guide
Part Number
Manufacturer
Inductance
(µH)
DCR
(mΩ)
Current
Rating (A)
Dimensions L
x W x H (mm3)
Switching
Frequency
(kHz)
744325072
Wurth
0.72
1.35
35
10.2 x 10.5 x 4.7
500
FDU1250C-1R0M
FDA1055-1R5M
744325180
TOKO
TOKO
Wurth
1
1.5
1.8
1.72
2.8
3.5
31.3
24
18
13.3 x 12.1 x 5
11.6 x 10.8 x 5.5
10.2 x 10.5 x 4.7
500
500
500
Typical Design Parameter Tables
The following tables include recommended
component values for typical output voltages (1V,
2.5V, 3.3V) and switching frequency (500kHz).
Refer to Table 2 for design cases without
external ramp compensation and Table 3 for
design cases with external ramp compensation.
An external ramp is not needed when using highESR capacitors, such as electrolytic or
POSCAPs. Use an external ramp when using
low-ESR capacitors, such as ceramic capacitors.
For cases not listed in this datasheet, an excel
spreadsheet
provided
by
local
sales
representatives can assist with the calculations.
Table 2—fSW=500kHz, VIN=12V
VOUT
(V)
1
2.5
3.3
L
(μH)
0.72
1.5
1.8
R1
(kΩ)
13.3
63.4
91
R2
(kΩ)
20
20
20
R7
(kΩ)
357
887
1200
Table 3—fSW=500kHz, VIN=12V
VOUT
(V)
1
2.5
3.3
L
(μH)
0.72
1.5
1.8
R1
(kΩ)
13.7
66.5
95.3
R2
(kΩ)
20
20
20
R4
(kΩ)
750
1000
1200
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C4
(pF)
220
220
220
R7
(kΩ)
357
887
1200
19
MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION (7)
V IN
C1A
10uF
C1B
10uF
C1C
C1D
R3
BST
IN
R7
0
C3
0.1uF L1
1uH, TOKO FDU1250C-1R0M
R5
0.1uF 0.1uF
100K
357K
VOUT
SW
FREQ
R1
MPQ8636A-10
13.7K
EN
R6
1uF
100K
C2B
C2A
220uF/20mƒ‚ 0.1uF
FB
VCC
C5
+
R2
SS
20K
C6
33nF
PG
PGND
AGND
Figure 10 — Typical Application Circuit with No External Ramp
MPQ8636A-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=500kHz
V IN
C1A
10uF
C1B
10uF
C1C
C1D
0.1uF 0.1uF
R7
BST
IN
R3
0
R5
100K
357K
C3
0.1uF
L1
1uH, TOKO FDU1250C-1R0M
VOUT
SW
FREQ
R4
MPQ8636A-10
330K
EN
FB
VCC
C5
R6
1uF
100K
C4
220pF
R9
100
R1
13.7K
C2A
C2B
C2C
47uF
47uF
47uF 0.1uF
C2D
C2E
0.1uF
R2
SS
20K
C6
33nF
PG
PGND
AGND
Figure 11 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8636A-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=500kHz
V IN
C1A
10uF
C1B
10uF
C1C
R7
C1D
0.1uF 0.1uF
BST
IN
R5
100K
357K
0
C3
0.1uF
FREQ
VOUT
R4
MPQ8636A-10
330K
EN
FB
VCC
C5
R6
1uF
100K
L1
1uH, TOKO FDU1250C-1R0M
SW
C4
220pF
CDC
10nF
R1
13.7K
C2A
C2B
C2C
47uF
47uF
47uF 0.1uF
C2D
C2E
0.1uF
R2
SS
C6
33nF
PG
PGND
20K
AGND
Figure 12 — Typical Application Circuit with Low ESR Ceramic Capacitor
and DC-Blocking Capacitor.
MPQ8636A-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=500kHz
NOTE:
7) The all application circuits’ steady states are OK, but other performances are not tested.
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
LAYOUT RECOMMENDATION
1. Place high current paths (GND, IN, and SW)
very close to the device with short, direct and
wide traces.
2. Two-layer IN copper layers are required to
achieve better performance. Respectively put
at least a decoupling capacitor on both Top
and Bottom layers and as close to the IN and
GND pins as possible. Also, several vias with
18mil diameter and 8mil hole- size are
required to be placed under the device and
near input capacitors to help on the thermal
dissipation, also reduce the parasitic
inductance.
3. Put a decoupling capacitor as close to the
VCC and AGND pins as possible.
4. Keep the switching node (SW) plane as small
as possible and far away from the feedback
network.
5. Place the external feedback resistors next to
the FB pin. Make sure that there are no vias
on the FB trace. The feedback resistors
should refer to AGND instead of PGND.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Recommend strongly a four-layer layout to
improve thermal performance.
VIN
RFREQ
C1C C1D C1E
C3
VOUT
R4
C4
R1
EN
C2
MPQ8636A-10
FB
VCC
C5
The detailed application schematic is shown in
Figure 11. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheets.
L1
SW
FREQ
R5
Table 4—Design Example
4.5-18V
VIN
1V
VOUT
500kHz
fSW
BST
IN
C1A C1B
Design Example
Below is a design example following the
application guidelines for the specifications:
R3
SS
R2
C6
PG
PGND
AGND
Figure 13—Schematic for PCB Layout Guide
Top Layer
Figure 14—Recommend Input Capacitor
Placement for QFN 3mmx4mm
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MPQ8636A-10 –10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-16 (3mm×4mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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